DIGITAL-TO-TIME CONVERTER (DTC) ASSISTED ALL DIGITAL PHASE LOCKED LOOP (ADPLL) CIRCUIT

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EP 3 701 631 B8

(12)	CORRECTED EUROPEAN PATENT SPECIFICATION
	Note: Bibliography reflects the latest situation

(15)	Correction information:
	Corrected version no 1 (W1 B1)

(48)	Corrigendum issued on:
	27.04.2022 Bulletin 2022/17

(45)	Mention of the grant of the patent:
	26.01.2022 Bulletin 2022/04

(21)	Application number: 17822055.4

(22)	Date of filing: 19.12.2017

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International Patent Classification (IPC):

H03L 7/085^(2006.01)
H03L 7/08^(2006.01)

H03L 7/093^(2006.01)

(52)	Cooperative Patent Classification (CPC):
	H03L 7/0802; H03L 7/085; H03L 7/093; H03L 2207/50

(86)	International application number:
	PCT/SG2017/050627

(87)	International publication number:
	WO 2019/125300 (27.06.2019 Gazette 2019/26)

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DIGITAL-TO-TIME CONVERTER (DTC) ASSISTED ALL DIGITAL PHASE LOCKED LOOP (ADPLL) CIRCUIT

VON DIGITAL-ZEIT-WANDLER (DTC) UNTERSTÜTZTE SCHALTUNG MIT KOMPLETT DIGITALEM PHASENREGELKREIS (ADPLL)

CIRCUIT TOUT NUMÉRIQUE À BOUCLE À VERROUILLAGE DE PHASE (ADPLL) ASSISTÉ PAR UN CONVERTISSEUR NUMÉRIQUE-TEMPS (DTC)

(84)	Designated Contracting States:
	AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(43)	Date of publication of application:
	02.09.2020 Bulletin 2020/36

(73)	Proprietor: Huawei International Pte. Ltd.
	Singapore 486066 (SG)

(72)	Inventors:
	YEO, Theng Tee Shenzhen 518129 (CN) CHEN, Xuesong Shenzhen 518129 (CN) YU, Rui Shenzhen 518129 (CN) LIU, Supeng Shenzhen 518129 (CN) YUAN, Chao Shenzhen 518129 (CN)

(74)	Representative: Epping - Hermann - Fischer
	Patentanwaltsgesellschaft mbH Schloßschmidstraße 5 80639 München 80639 München (DE)

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References cited: :

EP-A1- 3 119 000

LIU YAO-HONG ET AL: "An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and Modulator for IoT Applications in 40 nm CMOS", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, IEEE, US, vol. 64, no. 5, 1 May 2017 (2017-05-01), pages 1094-1105, XP011647144, ISSN: 1549-8328, DOI: 10.1109/TCSI.2016.2625462 [retrieved on 2017-04-21]
JINGCHENG ZHUANG ET AL: "A low-power all-digital PLL architecture based on phase prediction", ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2012 19TH IEEE INTERNATIONAL CONFERENCE ON, IEEE, 9 December 2012 (2012-12-09), pages 797-800, XP032331578, DOI: 10.1109/ICECS.2012.6463539 ISBN: 978-1-4673-1261-5
CHEN PENG ET AL: "Fractional spur suppression in all-digital phase-locked loops", 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE, 24 May 2015 (2015-05-24), pages 2565-2568, XP033183740, DOI: 10.1109/ISCAS.2015.7169209 [retrieved on 2015-07-27]

Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).