ATBECHDEDKESFR..GRITLILUNLSEMCPTIESILTLVFIROMKCYALTRBGCZEEHUPLSK..HRIS..MTNORS..SM..................J0009290-CORR01202411153955106CORRECTED EUROPEAN PATENT SPECIFICATIONB8B120250319W184deBibliographieenBibliographyfrBibliographieEP21200598.72018110220220816enenen20171829620171103GB2025031920251220220216202207202402142024072023091120240214AT20240214BG20240214CZ20240214DK20240214EE20240214ES20240214FI20240515GR20240214HR20240614IS20240214IT20240214LT20240214LV20240214NL20240514NO20240214PL20240614PT20240214RO20240514RS20240214SE20240214SK20240214SM20250319202512G06F 7/544 20060101AFI20211214BHEP G06F 7/5443 20130101 FI20190318BHEP G06N 3/063 20130101 LI20190724BHEP G06N 3/045 20230101 LI20230101RHEP deHARDWARE-EINHEIT ZUR DURCHFÜHRUNG VON MATRIXMULTIPLIKATION MIT CLOCK-GATINGenHARDWARE UNIT FOR PERFORMING MATRIX MULTIPLICATION WITH CLOCK GATINGfrUNITÉ MATÉRIELLE POUR EFFECTUER UNE MULTIPLICATION MATRICIELLE AVEC LE DÉCLENCHEMENT D'HORLOGEGB-A- 2 490 914DAVID BROOKS ET AL: "Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance", ACM TRANSACTIONS ON COMPUTER SYSTEMS (TOCS), vol. 18, no. 2, 1 May 2000 (2000-05-01), US, pages 89 - 126, XP055571292, ISSN: 0734-2071, DOI: 10.1145/350853.350856PREISS J ET AL: "Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units", COMPUTER ARITHMETIC, 2009. ARITH 2009. 19TH IEEE SYMPOSIUM ON, IEEE, PISCATAWAY, NJ, USA, 8 June 2009 (2009-06-08), pages 48 - 56, XP031519705, ISBN: 978-0-7695-3670-520197062.137707492020091818204166.5348069120181102MARTIN, ChrisBedfordshire, LU7 2PFGBPULIMENO, AzzurraWatford, Hertfordshire WD18 0FQGBImagination Technologies Limited101910187IMA01-130338EP2Imagination House Home Park EstateKings Langley, Hertfordshire WD4 8LZGBSlingsby Partners LLP1013950291 KingswayLondon WC2B 6ANGBALATBEBGCHCYCZDEDKEEESFIFRGRHRHUIEISITLILTLULVMCMKMTNLNOPLPTRORSSESISKSMTR