ATBECHDEDKESFRGBGRITLILUNLSEMCPTIESILTLVFIROMKCYALTRBGCZEEHUPLSK..HRIS..MTNORS..SM..................*JBDM Ver 2.0.24 - 2999001/03991305CORRECTED EUROPEAN PATENT SPECIFICATIONB8B120240103W173deBibliographieenBibliographyfrBibliographieEP20735576.92020063020220126enenen20190948920190701GB20200550120200415GB2024010320240120220504202218202311292023482023060920240103202401H03M 13/09 20060101AFI20230504BHEP H04L 1/00 20060101ALI20230504BHEP H03M 13/00 20060101ALI20230504BHEP H03M 13/091 20130101 FI20200908BHEP H03M 13/617 20130101 LI20200908BHEP H04L 1/0061 20130101 LA20210215BHEP H04L 1/0052 20130101 LA20210215BHEP deZYKLISCHE REDUNDANZ-PRÜFUNGSDEKODIERUNG UNTER VERWENDUNG DES INVERSEN GENERATOR POLYNOMS DES ZYKLISCHEN REDUNDANZKODESenCYCLIC REDUNDANCY CHECK, CRC, DECODING USING THE INVERSE CRC GENERATOR POLYNOMIALfrDÈCODAGE DE CODE À CONTRÔLE DE REDONDANCE CYCLIQUE, CRC, UTILISANT L'INVERSE POLYNÔME DE GÉNÉRATEUR CRCWO-A1-2016/050323JUNHO CHO ET AL: "Block-interleaving based parallel CRC computation for multi-processor systems", PROC., IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEM, SIPS 2010, SAN FRANCISCO, CALIFORNIA, USA, 6 October 2010 (2010-10-06), - 8 October 2010 (2010-10-08), pages 311-316, XP031792425, ISBN: 978-1-4244-8932-9RAMABADRAN T V ET AL: "A tutorial on CRC computations", IEEE MICRO, IEEE SERVICE CENTER, LOS ALAMITOS, CA, US, vol. 8, no. 4, 1 August 1988 (1988-08-01), pages 62-75, XP011437005, ISSN: 0272-1732, DOI: 10.1109/40.7773MAUNDER, RobertC/O Accelercomm Limited Epsilon House, Enterprise RoadSouthampton Science Park, Chilworth Southampton Hampshire SO16 7NSGBBREJZA, MatthewC/O Accelercomm Limited Epsilon House, Enterprise RoadSouthampton Science Park, Chilworth Southampton Hampshire SO16 7NSGBAccelerComm Ltd102020598ACL-2018-002 EP-15 Benham RdChilworth, Southampton SO16 7QJGBOptimus Patents Limited101427889Peak Hill House SteventonBasingstoke, Hampshire RG25 3AZGBALATBEBGCHCYCZDEDKEEESFIFRGBGRHRHUIEISITLILTLULVMCMKMTNLNOPLPTRORSSESISKSMTREP202006842620200630enWO202100138220210107202101