SOLAR CELL STACK PASSIVATION STRUCTURE AND PREPARATION METHOD THEREFOR

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EP 4 060 752 A8

(12)	CORRECTED EUROPEAN PATENT APPLICATION
	published in accordance with Art. 153(4) EPC

(15)	Correction information:
	Corrected version no 1 (W1 A1)

(48)	Corrigendum issued on:
	21.12.2022 Bulletin 2022/51

(43)	Date of publication:
	21.09.2022 Bulletin 2022/38

(21)	Application number: 21751735.8

(22)	Date of filing: 21.05.2021

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International Patent Classification (IPC):

H01L 31/0216^(2014.01)

H01L 31/18^(2006.01)

(52)	Cooperative Patent Classification (CPC):
	Y02P 70/50; Y02E 10/50; Y02E 10/547

(86)	International application number:
	PCT/CN2021/095127

(87)	International publication number:
	WO 2022/156101 (28.07.2022 Gazette 2022/30)

(84)	Designated Contracting States:
	AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
	Designated Extension States:
	BA ME
	Designated Validation States:
	KH MA MD TN

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Priority:

19.01.2021 CN 202110065887
14.04.2021 CN 202110396613

(71)	Applicant: Trina Solar Co., Ltd
	Changzhou, Jiangsu 213031 (CN)

(72)	Inventors:
	ZHANG, Xueling Changzhou, Jiangsu 213031 (CN) LIU, Wei Changzhou, Jiangsu 213031 (CN) CHEN, Hong Changzhou, Jiangsu 213031 (CN) JIAN, Lei Changzhou, Jiangsu 213031 (CN) CHEN, Yifeng Changzhou, Jiangsu 213031 (CN)

(74)	Representative: Cabinet Beaumont
	4, Place Robert Schuman B.P. 1529 38025 Grenoble Cedex 1 38025 Grenoble Cedex 1 (FR)

(54)	SOLAR CELL STACK PASSIVATION STRUCTURE AND PREPARATION METHOD THEREFOR

(57) A laminated passivation structure of solar cell and a preparation method thereof are disclosed herein. The laminated passivation structure of solar cell comprises a P-type silicon substrate, and a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer sequentially arranged on the back surface of the P-type silicon substrate from inside to outside. The preparation method comprises: generating a first dielectric layer on the back surface of the P-type silicon substrate, and then sequentially depositing a second dielectric layer, a third dielectric layer and a fourth dielectric layer on the first dielectric layer.