SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND PROVIDING REDUCED GATE LEAKAGE AND ASSOCIATED METHODS - Patent 4139964

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EP 4 139 964 A1

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(43)	Date of publication:
	01.03.2023 Bulletin 2023/09

(21)	Application number: 21737867.8

(22)	Date of filing: 10.06.2021

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International Patent Classification (IPC):

H01L 29/15^(2006.01)
H01L 29/06^(2006.01)
H01L 29/66^(2006.01)

H01L 21/762^(2006.01)
H01L 29/78^(2006.01)

(52)	Cooperative Patent Classification (CPC):
	H01L 29/152; H01L 29/78; H01L 29/06; H01L 21/76232; H01L 29/66651

(86)	International application number:
	PCT/US2021/036711

(87)	International publication number:
	WO 2021/252704 (16.12.2021 Gazette 2021/50)

(84)	Designated Contracting States:
	AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
	Designated Extension States:
	BA ME
	Designated Validation States:
	KH MA MD TN

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Priority:

11.06.2020 US 202016898589
11.06.2020 US 202016898564

(71)	Applicant: Atomera Incorporated
	Los Gatos, CA 95032 (US)

(72)	Inventors:
	TAKEUCHI, Hideki San Jose, California 95129 (US) YANG, Yung-Hsuan San Jose, California 95131 (US)

(74)	Representative: Roberts, David et al
	Page White & Farrer Limited Bedford House 21A John Street London WC1N 2BF London WC1N 2BF (GB)

(54)	SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND PROVIDING REDUCED GATE LEAKAGE AND ASSOCIATED METHODS