(19)
(11) EP 4 183 219 A1

(12)

(43) Date of publication:
24.05.2023 Bulletin 2023/21

(21) Application number: 21841565.1

(22) Date of filing: 15.07.2021
(51) International Patent Classification (IPC): 
H04W 76/15(2018.01)
H04W 88/08(2009.01)
H04L 9/40(2022.01)
H04W 84/12(2009.01)
(52) Cooperative Patent Classification (CPC):
H04W 88/08; H04W 84/12; H04W 76/15; H04W 92/20
(86) International application number:
PCT/US2021/041871
(87) International publication number:
WO 2022/016005 (20.01.2022 Gazette 2022/03)
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(30) Priority: 15.07.2020 US 202063052112 P

(71) Applicant: Intel Corporation
Santa Clara, CA 95054 (US)

(72) Inventors:
  • DAS, Dibakar
    Hillsboro, Oregon 97123 (US)
  • CARIOU, Laurent
    29290 Milizac (FR)
  • AKHMETOV, Dmitry
    Hillsboro, Oregon 97124 (US)
  • HUANG, Po-Kai
    San Jose, California 95131 (US)

(74) Representative: Viering, Jentschura & Partner mbB Patent- und Rechtsanwälte 
Am Brauhaus 8
01099 Dresden
01099 Dresden (DE)

   


(54) MECHANISM TO SIGNAL SIMULTANEOUS TRANSMIT RECEIVE OR NON-SIMULTANEOUS TRANSMIT RECEIVE CONSTRAINTS