METHOD OF FORMING A DEVICE WITH PLANAR SPLIT GATE NON-VOLATILE MEMORY CELLS, HIGH VOLTAGE DEVICES AND FINFET LOGIC DEVICES - Patent 4214756

(19)

(11)

EP 4 214 756 A1

(12)

(43)	Date of publication:
	26.07.2023 Bulletin 2023/30

(21)	Application number: 21706421.1

(22)	Date of filing: 20.01.2021

(51)

International Patent Classification (IPC):

H01L 27/11546^(2017.01)

H01L 29/423^(2006.01)

(52)	Cooperative Patent Classification (CPC):
	H01L 29/42328; H10B 41/49

(86)	International application number:
	PCT/US2021/014244

(87)	International publication number:
	WO 2022/060402 (24.03.2022 Gazette 2022/12)

(84)	Designated Contracting States:
	AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
	Designated Extension States:
	BA ME
	Designated Validation States:
	KH MA MD TN

(30)

Priority:

21.09.2020 CN 202010993707
19.01.2021 US 202117151944

(71)	Applicant: Silicon Storage Technology, Inc.
	San Jose, CA 95134 (US)

(72)	Inventors:
	WANG, Chunming Shanghai 201203 (CN) SONG, Guo Xiang Shanghai 201203 (CN) XING, Leo Shanghai 201203 (CN) SUN, Jack Shanghai 201203 (CN) LIU, Xian Sunnyvale, California 94087 (US) DO, Nhan Saratoga, California 95070 (US)

(74)	Representative: Betten & Resch
	Patent- und Rechtsanwälte PartGmbB Maximiliansplatz 14 80333 München 80333 München (DE)

(54)	METHOD OF FORMING A DEVICE WITH PLANAR SPLIT GATE NON-VOLATILE MEMORY CELLS, HIGH VOLTAGE DEVICES AND FINFET LOGIC DEVICES