REFERENCE VOLTAGE GENERATOR FOR RESISTIVE MEMORY ARRAY

(19)

(11)

EP 4 235 668 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	06.12.2023 Bulletin 2023/49

(43)	Date of publication A2:
	30.08.2023 Bulletin 2023/35

(21)	Application number: 23185744.2

(22)	Date of filing: 02.11.2018

(51)

International Patent Classification (IPC):

G11C 11/16^(2006.01)
G11C 11/00^(2006.01)
G11C 11/14^(2006.01)
G11C 5/14^(2006.01)

G11C 7/02^(2006.01)
G11C 11/02^(2006.01)
G11C 11/15^(2006.01)
G11C 13/00^(2006.01)

(52)	Cooperative Patent Classification (CPC):
	G11C 11/1655; G11C 13/0023; G11C 13/0026; G11C 13/004; G11C 2013/0054; G11C 11/1653; G11C 5/147; G11C 11/1673

(84)	Designated Contracting States:
	AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)

Priority:

02.11.2017 US 201762580968 P

(62)	Application number of the earlier application in accordance with Art. 76 EPC:
	18872763.0 / 3704697

(71)	Applicant: Numem Inc.
	Sunnyvale, California 94085 (US)

(72)	Inventor:
	HENDRICKSON, Nicholas T. Burnsville Minnesota, 55306 (US)

(74)	Representative: Herrero & Asociados, S.L.
	Edificio Aqua - Agustín de Foxá, 4-10 28036 Madrid 28036 Madrid (ES)

(54)	REFERENCE VOLTAGE GENERATOR FOR RESISTIVE MEMORY ARRAY

(57) An apparatus for storing data in a magnetic random access memory (MRAM) is provided. The MRAM may store data in one or more resistance-based memory cells and may include a plurality of comparators to compare a voltage generated based on the resistance-based memory cells to a reference voltage to determine a stored logic state. In some implementations, the reference voltage may be generated by a plurality resistance-based memory cells. The reference voltage may be adjusted higher or lower by storing different logic states within the resistance-based memory cells.

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