(19)
(11) EP 4 246 519 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
13.12.2023 Bulletin 2023/50

(43) Date of publication A2:
20.09.2023 Bulletin 2023/38

(21) Application number: 22195333.4

(22) Date of filing: 13.09.2022
(51) International Patent Classification (IPC): 
G11C 11/16(2006.01)
 G11C 13/00(2006.01)
(52) Cooperative Patent Classification (CPC):
G11C 11/161; G11C 11/1659; G11C 11/1673; G11C 13/004; G11C 2013/0054; G11C 2013/0057
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(30) Priority: 18.03.2022 JP 2022044263

(71) Applicant: Kioxia Corporation
Tokyo 108-0023 (JP)

(72) Inventor:
  • Takizawa, Ryousuke
    Tokyo, 108-0023 (JP)

(74) Representative: Hoffmann Eitle 
Patent- und Rechtsanwälte PartmbB Arabellastraße 30
81925 München
81925 München (DE)

   


(54) MEMORY DEVICE


(57) A first switching element in a memory cell is configured to transition from an ON state to an OFF state in response to a voltage applied between its two terminals being decreased. A read circuit is configured to place the second interconnect in a floating state, and, after placing the second interconnect in the floating state and based on a comparison between a first voltage of the second interconnect at a time point of the first switching element becoming the OFF state and a second voltage, either apply a third voltage to the second interconnect and then place the second interconnect in the floating state, or apply a fourth voltage lower than the third voltage to the second interconnect without applying the third voltage to the second interconnect.







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