(19)
(11) EP 4 329 252 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
13.03.2024 Bulletin 2024/11

(43) Date of publication A2:
28.02.2024 Bulletin 2024/09

(21) Application number: 23191477.1

(22) Date of filing: 15.08.2023
(51) International Patent Classification (IPC): 
H04L 25/03(2006.01)
G11C 11/40(2006.01)
(52) Cooperative Patent Classification (CPC):
H04L 25/03878; G11C 11/40; H04L 25/03012
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC ME MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA
Designated Validation States:
KH MA MD TN

(30) Priority: 26.08.2022 KR 20220107558
08.06.2023 US 202318331223

(71) Applicant: Samsung Electronics Co., Ltd.
Suwon-si, Gyeonggi-do 16677 (KR)

(72) Inventors:
  • NA, Daehoon
    16677 Suwon-si (KR)
  • LEE, Seonkyoo
    16677 Suwon-si (KR)
  • BAE, Seungjun
    16677 Suwon-si (KR)
  • LEE, Taesung
    16677 Suwon-si (KR)

(74) Representative: Marks & Clerk LLP 
15 Fetter Lane
London EC4A 1BW
London EC4A 1BW (GB)

   


(54) EQUALIZER FOR REMOVING INTER SYMBOL INTERFERENCE OF DATA SIGNAL BY INCREASING PULSE WIDTHS OF LOGIC LOW LEVEL AND LOGIC HIGH LEVEL OF DATA SIGNAL


(57) An equalizer includes a first pulse width controller that is configured to generate a first signal by increasing a first pulse width of a first data signal having a first logic level, the first data signal corresponding to a current data bit, a second pulse width controller that is configured to generate a second signal by increasing a second pulse width of the first data signal having a second logic level, a first sampler that is configured to generate a first sampled signal by sampling the first signal, a second sampler that is configured to generate a second sampled signal by sampling the second signal, and a multiplexer that is configured to output the first sampled signal or the second sampled signal based on a value of a previous data bit.







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