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(11) | EP 4 418 136 A3 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | SYSTEMS, APPARATUSES, AND METHODS FOR FUSED MULTIPLY ADD |
| (57) In some embodiments, an apparatus comprises: circuitry to fetch one or more instructions,
the one or more instructions to indicate a first source vector comprising a first
plurality of integer data elements, a second source vector comprising a second plurality
of integer data elements, and one or more accumulation integer data elements, wherein
each of the one or more accumulation integer data elements is four times larger than
each data element of the first plurality of integer data elements and the second plurality
of integer data elements, and wherein the first plurality of integer data elements
and the one or more accumulation integer data elements are signed integer data elements
and the second plurality of integer data elements are unsigned integer data elements;
on-chip storage to store the first plurality of integer data elements, the second
plurality of integer data elements, and the one or more accumulation integer data
elements; and execution circuitry to execute the one or more instructions to generate
one or more result integer data elements. To generate the one or more result integer
data elements, the execution circuitry is to: multiply each data element of the first
plurality of integer data elements with a corresponding data element of the second
plurality of integer data elements to generate a plurality of products, and accumulate
the plurality of products in groups of four, each group of four products to be accumulated
with a corresponding accumulation integer data element of the one or more accumulation
integer data elements with saturation to generate a corresponding one or more result
integer data elements.
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