HIGH-RESOLUTION TIME-BASED JUNCTION TEMPERATURE ESTIMATION AND CALIBRATION

Abstract

 A measurement method for estimating junction temperatures of a power semi-conductor module (1) comprising:
a. duplicating a pulse current;
b. injecting simultaneously
- a first duplicated pulse current to a control electrode (G) of a power transistor (TR) of said power semi-conductor module (1), and
- a second duplicated pulse current to an emulator circuit (EMU) comprising a resistance (R_emu) in series with a capacitor (C_emu);

c. comparing a voltage signal (V_ge) of said power transistor (TR) and a voltage signal (V_emu) of said emulator circuit (EMU) in such a way to generate a comparison signal (V_CMP);
d. in function of said comparison signal (V_CMP), measuring duration (Δt) of said voltage signal (V_ge) of said power transistor (TR) to reach the same value as said voltage signal (V_emu) of said emulator circuit (EMU);
e. converting said measured duration (Δt) into an estimated value of a junction temperature (T_J).

Description

Technical Field

[0001] This disclosure pertains to the field of power semiconductor monitoring, and related calibration method, that are applicable during the operational life of such components.

Background Art

[0002] It is known to monitor temperature in power semiconductor devices/modules, like multichip power modules, for protection, condition and health monitoring because the temperature is one of the main failure origins. The datasheet of power semiconductor provides the maximum junction temperature where it can operate without thermal runaway and consequent catastrophic failure. Therefore, monitoring the junction temperature, or at least the maximum junction temperature measurement, is a great interest to ensure the safe operation of the device.

[0003] Generally, the free surface of a die is very small. To fix a sensor on it is difficult, and even impossible in some cases. The number of external connections is high, and the acquisition system is complex. To do it in laboratory conditions is very difficult. In real, industrial and operational situations, to use individual PN junction sensors is not realistic. In addition, sensors have to be integrated inside the power module packaging which means that the presence of sensors have to be initially planned during the conception of the module and to retrofit to the existing power modules is impossible.

[0004] Many Temperature Sensitive Electrical Parameters (TSEP) based methods and in-chip sensors for on-line junction temperature estimation on power semiconductor are known. This allows to have direct access to the junction temperature without the need of an external sensor. Typically, the measurement of the TSEP of a transistor is performed with an Analog-to-Digital Converter (ADC). The use of an ADC can be a limitation for low-cost systems since the resolution and sampling speed of the ADC directly relate to the quality of the temperature estimation. A TSEP of a transistor can be a time. More specifically, a TSEP of a transistor can be measured as a time duration relative to a detection threshold. A measurement of time may be a problem because of low temperature to time sensitivity. A simplest way is to monitor the passing of the temperature above a critical, safety-related, temperature value. This can be made with an analogue comparator comparing the TSEP value to a threshold value. Such a technic is described in EP 3 855 145 A1. In this way, an ADC is not required but this limits the measurement to one specific temperature value. The specific temperature value is adjusted to correspond to the over-temperature of a specific power transistor. However, such a method presents the following limitations:

• Only one temperature is monitored. The predetermined temperature threshold is selected, generally according to a datasheet provided by the manufacturer.
• Monitoring multiple temperature values is possible but has a direct impact on the circuit and calibration complexity. Multiple temperatures can indeed be monitored by duplicating the monitoring circuit. The number of emulator components is thus multiplied, as well as the calibration effort.
• The Over-Temperature-Detection (OTD) circuit hardware needs to be specific for each monitored device. The TSEP characteristics being unique for each device, a calibration must be done for each OTD circuit. This limits the functionality of the OTD for one specific transistor.
• The OTD circuit is not modifiable, it cannot be adjusted during operation. A deviation of the TSEP during the mission profile of the device cannot be excluded which may alter the operation of the OTD, for example by modifying the measured temperature value.
• When the TSEP of a power transistor is the time, the time-to-temperature sensitivity is low. This will either lead to low precision/accuracy and/or require costly signal conditioning circuits.

Summary

[0005] This disclosure improves the situation.

[0006] It is proposed a measurement method for estimating junction temperatures of a power semi-conductor module comprising:

a. duplicating a pulse current in two duplicated pulse currents;

b. injecting simultaneously

• a first duplicated pulse current to a control electrode of a power transistor of said power semi-conductor module, and
• a second duplicated pulse current to an emulator circuit comprising a resistance in series with a capacitor;

c. comparing a voltage signal of said power transistor and a voltage signal of said emulator circuit in such a way to generate a comparison signal;

d. in function of said comparison signal, measuring duration of said voltage signal of said power transistor to reach the same value as said voltage signal of said emulator circuit;

e. converting said measured duration into an estimated value of a junction temperature.

[0007] In another aspect, it is proposed a power semi-conductor module comprising:

• at least one power transistor;
• a current pulse source that is provided through a control electrode of said power transistor;
• a current copier arranged to duplicate the current provided by the current pulse source;
• an emulator circuit comprising a resistance in series with a capacitor;
• a comparator arranged to compare a voltage signal of said power transistor and a voltage signal of said emulator circuit in such a way to generate a comparison signal.

[0008] In another aspect, it is proposed a computer software comprising instructions to implement the method as defined here when the software is executed by a processor. In another aspect, it is proposed a computer-readable non-transient recording medium on which a software is registered to implement the method as defined here when the software is executed by a processor.

[0009] The following features, can be optionally implemented, separately or in combination one with the others:

[0010] The resistance of said emulator circuit is tunable and the value of said resistance is set in such a way that the temperature estimation range amplitude is selected.

[0011] The capacitor of said emulator circuit is tunable and the value of said capacitor is set in such a way that the temperature estimation range position is selected.

[0012] The method further comprises the following calibration step:

• if the generated comparison signal corresponds to a situation wherein said voltage signal of said power transistor is inferior to said voltage signal of said emulator circuit, during a portion of the duration of the pulse injection which is superior to a predetermined maximum,
  increasing the value of said capacitor of said emulator circuit ;
  and
• if the generated comparison signal corresponds to a situation wherein said voltage signal of said power transistor is superior to said voltage signal of said emulator circuit, during a portion of the duration of the pulse injection which is inferior to a predetermined maximum,

decreasing the value of said capacitor of said emulator circuit.

[0013] The module further comprises:

• a controller arranged to tune said resistance and/or said capacitor.

Brief Description of Drawings

[0014] Other features, details and advantages will be shown in the following detailed description and on the figures, on which:

Fig. 1
[Fig. 1] is a schematic view of a module according to some embodiments.

Fig. 2
[Fig. 2] is a graphical representation of the measured output voltages during a current pulse and a corresponding comparison signal.

Fig. 3
[Fig. 3] is a graphical representation of the measured output voltages during a current pulse and a corresponding comparison signal.

Fig. 4
[Fig. 4] is a graphical representation of the linear relationship of the signal duration as a function of the temperature deduced from comparisons like in [Fig. 2] and [Fig. 3].

Fig. 5
[Fig. 5] is similar to [Fig. 2] or [Fig. 3] in a situation where C_g > C_emu.

Fig. 6
[Fig. 6] is similar to [Fig. 2] or [Fig. 3] in a situation where C_g < C_emu.

Fig. 7
[Fig. 7] is a graphic view of the temperature-to-time resolution as a function of the emulator capacitance.

Fig. 8
[Fig. 8] is a schematic representation of a controller arrangement to tune an emulator circuit.

Fig. 9
[Fig. 9] is a flowchart of an algorithm that can be executed during an embodiment.

Fig. 10
[Fig. 10] is a flowchart of an algorithm that can be executed during an embodiment.

Fig. 11
[Fig. 11] is a flowchart of an algorithm that can be executed during an embodiment.

Fig. 12
[Fig. 12] is a graphical representation of a dynamic adaptation of an emulator circuit.

Fig. 13
[Fig. 13] is a flowchart of an algorithm that can be executed during an embodiment.

Fig. 14
[Fig. 14] is a flowchart of an algorithm that can be executed during an embodiment.

Fig. 15
[Fig. 15] is a schematic representation of an embodiment of a dynamic adaptation of an emulator circuit.

Description of Embodiments

[0015] Here, the word "power" is used in its general meaning of the technical field of energy conversion (power electronics). In addition, the solutions described hereinafter are made to be used during operational lifetime of the power semi-conductor modules under "normal" conditions, which means that it is not limited to the context of a laboratory or a test bench under ideal and controlled conditions like post-production quality control phases.

[0016] It is now referred to [Fig. 1] showing a module power semi-conductor module 1. The power semi-conductor module 1 comprises:

• at least one power transistor TR;
• a current pulse source CPS that is provided through a control electrode G of said power transistor TR;
• a current copier CC arranged to duplicate the current provided by the current pulse source;
• an emulator circuit EMU comprising a resistance R_emu in series with a capacitor C_emu;
• a comparator COMP arranged to compare a voltage signal V_ge of said power transistor TR and a voltage signal V_emu of said emulator circuit EMU, here in such a way to generate a comparison signal V_CMP.

[0017] On [Fig. 1], the module 1 further comprises a time detector CHR. The time detector CHR is arranged to measure a time duration of the comparison signal V_CMP. Structurally, the time detector CHR can be a specific module by itself or can be a sub-module functionally integrated to the Comparator COMP.

[0018] Examples of measurement method for estimating junction temperatures of a power semi-conductor module like the one shown on [Fig. 1] will now be described.

[0019] In a first operation, a pulse current is duplicated in two identical pulse currents. In the example of [Fig. 1], a pulse current from the current pulse source CPS is duplicated by the current copier CC, for example a "current mirror circuit". The aim is to inject the same current pulse, simultaneously, in the transistor TR and in the emulator circuit EMU.

[0020] In a second operation, the first and second duplicated pulses currents are injected simultaneously respectively in a control electrode of the power transistor TR and in the emulator circuit EMU. In the example of [Fig. 1], the control electrode is the gate G of the transistor TR. Doing this, the internal gate resistance of the transistor (present within the structure of the transistor) is used as a TSEP.

[0021] In a third operation, the resulting voltages V_ge and V_emu are compared. In the example of [Fig. 1], the comparison is made by means of the comparator COMP between the gate-emitter voltage V_ge of the transistor TR and the output voltage V_emu of the emulator circuit EMU.

[0022] The resulting voltages V_ge and V_emu can be described respectively by the following equations [Math. 1] and [Math. 2].






where I is the current, t is the time and R_g(T_j) is the gate resistor.

[0023] The gate resistor R_g depends linearly on the temperature and can be described by the following equation [Math. 3].

[0024] In the example, the comparison is binary: the output signal V_CMP is equal to "1" when the transistor voltage is superior or equal to the emulator circuit voltage (V_ge ≥ V_emu), and "0" in the other cases (V_ge < V_emu). Thus, the time duration of the situation wherein the transistor voltage is superior or equal to the emulator circuit voltage (V_CMP = 1) can be measured using equations [Math. 1] and [Math. 2], according to the following equation [Math. 4].

[0025] Here, the difference is analyzed with a binary value ("1" or "0") because the value of the difference is not relevant by itself. Only the duration of the sign of the difference is. In various embodiments, the comparison of the two voltages can be made differently and can be analogic for example.

[0026] The relation between time and temperature is independent of the value of the current injection. Thus, the method is robust to the imperfections of the current pulse source CPS and allows a good precision and a low-drift even if a low-cost current injection circuit is used. The temperature can be measured without additional ADC, considerably reducing the cost of the junction temperature T_j measurement. Instead, a Time-to-Digital Converter (TDC) can be used, or even the time to digital conversion can be implemented in an FPGA, eventually in the same FPGA that generates control signals of a switch and other functions of the module 1.

[0027] The comparison of V_ge and V_emu is graphically represented on [Fig. 2], [Fig. 3] and [Fig. 4]. [Fig. 2] corresponds to the implementation under a first temperature T₁ while [Fig. 3] corresponds to the implementation under a second temperature T₂.

[0028] In a fourth operation, the measured duration Δt is converted into a junction temperature T thanks to the linear relationship of the duration Δt as a function of the temperature T. As it is represented on [Fig. 4], the said relationship can be deduced from plurality of measurement at various temperatures T_n.

[0029] A Time-to-Digital Converter (TDC) can be used to implement the conversion, including TDC known by themselves. Some TDC offer resolutions better than 1ns. For example, the component having the commercial reference "TDC7401ZAXRé has a resolution of 55ps. The temperature resolution can be expressed as a function of the TDC resolution with the following equation [Math. 5].

[0030] The temperature-to-time resolution can easily be less than 1°C/ns, meaning that a TDC with a resolution of 55ps would allow to obtain a temperature resolution of less than 0.055°C. To be convinced of the great resolution that can be reached by such a method, we should compare it to a current injection known in the art of 1 00mA and a resistance to temperature resolution of 0.013Ω/°C: in such a case, the temperature resolution is in the order of 0.5°C with a known 14bit ADC and a ±5V rail.

[0031] The temperature resolution, and subsequent accuracy and precision can be much lower than state of the art methods.

[0032] In the proposed example, the output signal value of the comparator COMP can be either 0 or 1. Depending on the value of R_emu and C_emu; two cases can be considered. The two cases are shown respectively on [Fig. 5] and [Fig. 6]. In a first case ([Fig. 5]), C_g and R_g are higher than C_emu and R_emu respectively. The output signal V_CMP of the comparator COMP is equal to "1" and the length (duration) of the signal will be proportional to the temperature T_j. In a second case ([Fig. 6]), C_g and R_g are lower than C_emu and R_emu respectively. The output signal V_CMP of the comparator COMP is equal to "0" and the length (duration) of the signal will be proportional to the temperature T_j.

[0033] In the examples, the emulator circuit EMU is tunable: the value of the resistance R_emu can be set and the value of the capacitor C_emu can be set (independently one with respect to the other). In various embodiment, only the resistance is tunable or only the capacitor is tunable. In other embodiments, the emulator circuit EMU is not tunable.

[0034] When the capacitor value C_emu is settable, it is thus possible to estimate the temperature only by setting C_emu independently of the value of R_emu. When R_emu < R_g (see [Fig. 5]) and R_emu > R_g (see [Fig. 6]), C_emu < C_g and C_emu > C_g, respectively. Thus, for example, a calibration process only of C_emu at the end of the manufacturing of the module 1 can be performed, after the T_j estimation circuit is connected to the transistor TR.

[0035] For a given value of R_emu:

• if no signal ("0") is detected at the output of the comparator COMP, C_emu must be increased;
• if only a positive signal ("1") is detected at the output of the comparator COMP, C_emu must be decreased.

[0036] When the capacitor value C_emu is settable, it is thus possible to increase the temperature-to-time resolution by setting C_emu close to C_g. According to the equation [Math. 5], the closer the C_emu is and the higher the temperature-to-time resolution is. This is shown on [Fig. 7]: the temperature-to-time resolution as a function of C_emu-C_g is plotted. On can see that the resolution increases for C_emu closer to C_g.

[0037] Decreasing the capacitance C_emu (during the operational life of the module 1) can be made by use of a laser trimmable chip capacitor built up as multilayer plate capacitors. Vaporizing the top layer with a laser decreases the capacitance by reducing the area of the top electrode. Depending on the industrial context, the resistor trimming process can be replaced by a capacitor trimming process when it is more convenient.

Calibration

[0038] In some embodiments with an emulator circuit EMU having a tunable resistance R_emu and a tunable capacitor C_emu; further operations of calibration can be implemented. In such a case, the module 1 can further comprise a controller CONT.

[0039] As an example, tunable capacitor and resistor can be digitally potentiometers controlled by the controller CONT, such as an FPGA. Only as an example, the component having the commercial reference "NCD2400MTR" can be used and give a range of 200pF with 512 discrete 355fF steps. If this range is not sufficient to cover full range of different device capacitance, the range can be increase by adding several bigger capacitances in parallel with one "NCD2400MTR" and controlled by the FPGA, as shown on [Fig. 8].

[0040] As a second example, a n-bit R-2R resistor ladder network controlled by an FPGA can be used. This allows to get 2n resistors steps directly tunable by the FPGA. As a third example, digital potentiometer such as the component having the commercial reference "AD5258" with 64 resistor steps can be used.

[0041] A person skilled in the art would choose an emulator circuit EMU, including the controller CONT, adapted in function of the transistors to drive and the operational conditions, to adapt the range of capacitance. By using tunable capacitor and resistor, the TSEP of the transistor can be automatically calibrated using different algorithms. This allows to change (only) the transistor and keeping the temperature measurement operational. In addition, during the operational lifetime of the transistor (not only in laboratory conditions on a test bench), calibration procedures can be made regularly to balance any TSEP parameters variation.

[0042] [Fig. 9], [Fig. 10] and [Fig. 11] are three examples of algorithms of calibration that can be used.

[0043] In the example of [Fig. 9], the transistor is exposed at two different temperatures T1 and T2. The capacitor C_emu and the resistor R_emu are initially set at their lower values in order to obtain different output voltages between the transistor and the emulator circuit. This situation corresponds to V_CMP = 1 if this algorithm of calibration is combined with the comparator COMP above described. The assembly is set at one first fixed temperature T1 and the time detection is set at one time t1. The resistance R_emu is gradually increased until obtaining the same output voltages between the transistor and the emulator circuit (V_CMP = 0). Then, the time detection is set at another time t2 and the capacitance C_emu is gradually increased until obtaining different output voltages between the transistor and the emulator circuit (V_CMP = 1). Doing this, the time detection sensitivity is set. Finally, the temperature is fixed at a second temperature T2 and a time scan is performed until obtaining the same output voltages between the transistor and the emulator circuit (V_CMP = 0).

[0044] The example of [Fig. 9] enables to reduce the calibration effort because the module 1 has to be exposed to only two different temperatures T1 and T2. A usual (cheap) FPGA is sufficient to do that.

[0045] In the example of [Fig. 10], only the value of the capacitor C_emu is modified. The time detection is gradually increased to set the time detection corresponding to a first temperature T1. Then, the capacitor C_emu is gradually increased to fix the resolution of the detector. Finally, the temperature is fixed at a second temperature T2 and the time detection is gradually increased until obtaining different output voltages between the transistor and the emulator circuit (V_CMP = 1).

[0046] The example of [Fig. 10] enables to use a fixed (not tunable) resistance R_emu.

[0047] The example of [Fig. 11] is adapted to the two situations previously described when the resistance R_g of the transistor is superior to the resistance R_emu of the emulator circuit (R_g > R_emu ; see [Fig. 5]), and when the resistance R_g of the transistor is inferior to the resistance R_emu of the emulator circuit (R_g < R_emu ; see [Fig. 6]). Initially, the capacitance C_emu is fixed at an intermediate value (for example a middle of the known range) and the temperature is fixed at one first known temperature T1. The time detection is gradually increased. If the output voltages between the transistor and the emulator circuit was different and become equal (V_CMP changes from 1 to 0), it means that R_g > R_emu and we are in the case of [Fig. 5]. On the contrary, if output voltages between the transistor and the emulator circuit was equal and become different (V_CMP changes from 0 to 1), it means that R_g < R_emu and we are in case of [Fig. 6]. Then, the capacitance C_emu is decreased in the first case (R_g > R_emu) and is increased in the second case (R_g < R_emu) to set the time sensitivity. Then, the temperature is fixed at a second known temperature T2 and the time detection is gradually increased until obtaining the same output voltages between the transistor and the emulator circuit (VCMP = 0) in the first case (R_g > R_emu), or until obtaining different output voltages between the transistor and the emulator circuit (V_CMP = 1) in the second case (R_g < R_emu).

[0048] In the example of [Fig. 11] the value of the resistance R_emu of the emulator circuit with respect to the resistance R_g of the transistor is less critical, and R_emu may be a fixed resistor value instead of a tunable value.

[0049] One way to expose a transistor to a known temperature (T1 or T2) is to consider the ambient (heat-sink) temperature when said transistor has been in off-state for several minutes. Another way to expose the transistor to a known temperature is to consider the baseplate temperature when said transistor has been in off-state for several seconds. The temperature exposure can be performed ex-situ (i.e. outside the module), with a heat-plate, and/or in-situ, by considering the temperature at two different instants.

Dynamic resolution of Time-based T_J estimation

[0050] As it is above explained, an emulator circuit EMU having a tunable resistance R_emu and a tunable capacitor C_emu enables to calibrate the emulator circuit EMU in function of the transistor, for example only one time after the manufacturing/assembling process, periodically during the operational life of the module (for example during maintenance operations) or even during the "normal" operations of the modules. In the following, we will focus on solutions specifically adapted to be implemented dynamically, during the operational life of the module, to dynamically adapt the resolution of the temperature estimation when the temperature changes by mean of an embedded controller.

[0051] The range of temperature that can be estimated is related to the resistance R_emu of the emulator circuit EMU while the amplitude (the sensitivity) of the temperature that can be deduced from the time t is related to the conductance C_emu of the emulator circuit EMU. In other words, contrary to the prior art solutions where a definitive compromise must be made between a large amplitude and a high resolution, the solutions that we propose here enable to automatically and dynamically optimize the range and the resolution to each transistor and to each state of life (changing characteristics) of each transistor.

[0052] As an example, one target of the calibration can be to cover a range of temperatures comprised between 125°C and 200°C (i.e. for protection). Alternatively, the target is to cover a range comprised between -40°C and 200°C (i.e. for counting the temperature cycles). For a specified temperature range, the sensitivity can be optimized to be the highest. The performance of the junction temperature T_J estimation circuit can be optimized to get the best precision in each range of temperatures.

[0053] Since a junction temperature T_J has been estimated, the following operation can be implemented:

f. modify the value of said resistance R_emu of the emulator circuit EMU such that a corresponding temperature estimation range is modified and that the estimated value of a junction temperature T_J get closer to the middle of the modified temperature estimation range;

g1. if the estimated value of the junction temperature T_J is sufficiently centered in the middle of the modified temperature estimation range according to predefined criteria, modify the value of said capacitor C_emu of the emulator circuit EMU such that the sensitivity is increased (and the range is reduced);

g2. if the estimated value of the junction temperature T_J is not sufficiently centered in the middle of the modified temperature estimation range according to predefined criteria, modify the value of said capacitor C_emu of the emulator circuit EMU such that the sensitivity is decreased (and the range is increased).

[0054] The above operations are graphically illustrated on [Fig. 12]. In a first scenario (left part of [Fig. 12]), the junction temperature T_J is estimated as being T_J1. The value T_J1 is sufficiently centered in the measured range (curve "A"). Then, the time-to-temperature sensitivity is increased, and the value T_J1 is kept centered in the measured range (curve "B"). The time-to-temperature sensitivity is increased again, and the value T_J1 is again kept centered in the measured range (curve "C"). In a second scenario (right part of [Fig. 12]), the junction temperature T_J changes (increases in the example) and is estimated as being T_J2. The junction temperature T_J=T_J2 is not in the measurement range anymore (curve "C"). The time-to-temperature sensitivity is decreased (by modifying the value of the capacitor C_emu of the emulator circuit): the temperature T_J2 is in the measurement range but is not centered (Curve "D"). The temperature range is moved to center the estimated temperature T_J2 (by modifying the value of the resistance R_emu of the emulator circuit; Curve "E")), and the sensitivity is increased (by modifying the value of the capacitor C_emu of the emulator circuit; Curve "F").

[0055] In the example of [Fig. 12], the temperature range is maximized to know the approximate temperature range of the transistor. Once the range of the temperature is known, the controller applies the algorithm to set the value of R_emu to focus on the temperature and C_emu is adjusted to optimize the resolution. When the temperature of the transistor changes, the algorithm readjusts R_emu and C_emu to focus the measurement on the new temperature.

[0056] To summarize, by approaching C_emu close to C_g, the time sensitivity can be increased. This allows to precisely measure a large range of temperature and over-passed the trade-off range/sensitivity by using different algorithms. Dynamic iterations are implemented to set the emulator circuit (R_emu and C_emu). The range/sensitivity trade-off is over-passed. In other words, using several iterations, both a high measurement range and a high sensitivity can be reached.

[0057] Only as examples, [Fig. 13] and [Fig. 14] show examples of dynamic estimation/calibration algorithm implementations. The example of [Fig. 13] is general and the example of [Fig. 14] is more detailed to consider the two cases above described with respect to [Fig. 5], [Fig. 6] and [Fig. 11].

[0058] In various embodiments, dynamic estimation of the temperature by using tunable R_emu and C_emu parameters can also be done by fixing the time duration t close to "0" (to obtain R_g(T) ; see [Math. 1]). This method is shown on [Fig. 15], where C_emu is constant and R_emu is tuned until obtaining different output voltages between the transistor and the emulator circuit (V_CMP = 1). This allows to determinate the temperature and the gate resistance R_g(T) value by using a regulator, for example a Proportional, Integral one ("PI" on [Fig. 15]). The value R_g and the temperature T_J can be estimated without measuring the time duration of the output signal of the comparator COMP.

Industrial Applicability

[0059] An aim of the previous description is to measure a junction temperature of a power transistor using the internal gate resistance R_g as TSEP at high resolution, low circuit cost, low calibration effort, and with a high circuit genericity. Optionally, calibrations can be made. Two equal currents are injected simultaneously through a control electrode of the transistor (generally the gate) and through an equivalent RC circuit called "emulator circuit". In the embodiments wherein we want to do more than a measure/estimation on a specific transistor, we can further implement calibration steps by using tunable emulator circuit (the resistance R_emu and/or the capacitance C_emu being tuned to be in the same range of respectively R_g and C_g of the transistor). The voltages V_ge and V_emu are compared with an analogue comparator. The time duration (not the amplitude by itself) of the output signal of the comparator is linearly proportional to the temperature of the transistor. This allows to measure the junction temperature of the transistor without ADC. In addition, by using tunable resistor and capacitor controlled by a controller, for example an FPGA, it is possible to make calibration in situ for different components properties and to repeat the calibration during the operational life of the module to compensate deviation.

[0060] Without limitation, modules according to the above can be used, for example, as power modules and inverters in automotive and powertrain technical fields, in factory automation, air-conditioning systems, HVDC and renewable energies.

[0061] This disclosure is not limited to the methods, modules, components and computer software described here, which are only examples. The invention encompasses every alternative that a person skilled in the art would envisage when reading this text.

Reference Signs List

[0062] 

• 1: module
• CPS: current pulse source
• CC: current copier
• TR: transistor
• EMU: emulator circuit
• COMP: comparator
• CHR: time detector
• CONT: Controller.

Claims

1. A measurement method for estimating junction temperatures of a power semi-conductor module (1) comprising:

a. duplicating a pulse current in two duplicated pulse currents;

b. injecting simultaneously

- a first duplicated pulse current to a control electrode (G) of a power transistor (TR) of said power semi-conductor module (1), and

- a second duplicated pulse current to an emulator circuit (EMU) comprising a resistance (R_emu) in series with a capacitor (C_emu);

c. comparing a voltage signal (V_ge) of said power transistor (TR) and a voltage signal (V_emu) of said emulator circuit (EMU) in such a way to generate a comparison signal (V_CMP);

d. in function of said comparison signal (V_CMP), measuring duration (Δt) of said voltage signal (V_ge) of said power transistor (TR) to reach the same value as said voltage signal (V_emu) of said emulator circuit (EMU);

e. converting said measured duration (Δt) into an estimated value of a junction temperature (T_J).

2. Method according to the preceding claim, wherein said resistance (R_emu of said emulator circuit (EMU) is tunable and wherein the value of said resistance (R_emu) is set in such a way that the temperature estimation range amplitude is selected.

3. Method according to one of the preceding claims, wherein said capacitor (C_emu of said emulator circuit (EMU) is tunable and wherein the value of said capacitor (C_emu) is set in such a way that the temperature estimation range position is selected.

4. Method according to claim 3 further comprising the following calibration step:

- if the generated comparison signal (V_CMP) corresponds to a situation wherein said voltage signal (V_ge) of said power transistor (TR) is inferior to said voltage signal (V_emu) of said emulator circuit (EMU), during a portion of the duration of the pulse injection which is superior to a predetermined maximum,
increasing the value of said capacitor (C_emu) of said emulator circuit (EMU) ;
and

- if the generated comparison signal (V_CMP) corresponds to a situation wherein said voltage signal (V_ge) of said power transistor (TR) is superior to said voltage signal (V_emu) of said emulator circuit (EMU), during a portion of the duration of the pulse injection which is inferior to a predetermined maximum,

decreasing the value of said capacitor (C_emu) of said emulator circuit (EMU).

5. A power semi-conductor module (1) comprising:

- at least one power transistor (TR);

- a current pulse source (CPS) that is provided through a control electrode (G) of said power transistor (TR);

- a current copier (CC) arranged to duplicate the current provided by the current pulse source;

- an emulator circuit (EMU) comprising a resistance (R_emu) in series with a capacitor (C_emu);

- a comparator (COMP) arranged to compare a voltage signal (V_ge) of said power transistor (TR) and a voltage signal (V_emu) of said emulator circuit (EMU) in such a way to generate a comparison signal (V_CMP).

6. A power semi-conductor module (1) according to the preceding claim further comprising:

- a controller (CONT) arranged to tune said resistance (R_emu) and/or said capacitor (C_emu).

7. Computer software comprising instructions to cause the module (1) of claims 5 or 6 to implement the method according to one of claims 1 to 4 when the software is executed by a processor.

8. Computer-readable non-transient recording medium on which a software is registered to implement a method according to one of claims 1 to 4 when the software is executed by a processor.

Drawing