(19)
(11) EP 4 478 409 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
09.04.2025 Bulletin 2025/15

(43) Date of publication A2:
18.12.2024 Bulletin 2024/51

(21) Application number: 24208359.0

(22) Date of filing: 19.04.2019
(51) International Patent Classification (IPC): 
H10D 84/01(2025.01)
H10D 84/83(2025.01)
H01L 23/485(2006.01)
H10D 88/00(2025.01)
H01L 25/065(2023.01)
H01L 21/56(2006.01)
 H10D 84/03(2025.01)
H10D 30/62(2025.01)
H01L 21/768(2006.01)
H01L 23/528(2006.01)
H01L 23/31(2006.01)
H01L 23/00(2006.01)
(52) Cooperative Patent Classification (CPC):
H01L 21/563; H01L 23/3128; H01L 21/76897; H01L 21/76898; H01L 23/485; H01L 2224/131; H01L 24/13; H01L 2224/81191; H01L 2924/15311; H01L 2224/16227; H01L 2224/73204; H01L 2224/32225; H01L 24/16; H01L 24/32; H01L 2224/291; H01L 24/29; H01L 2224/16145; H01L 25/0652; H01L 23/5286; H10D 84/0158; H10D 84/038; H10D 84/0149; H10D 84/834; H10D 30/6219
 
C-Sets:
  1. H01L 2224/131, H01L 2924/014;
  2. H01L 2224/291, H01L 2924/0665;
  3. H01L 2224/73204, H01L 2224/16225, H01L 2224/32225, H01L 2924/00;
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30) Priority: 07.06.2018 US 201816003031

(62) Application number of the earlier application in accordance with Art. 76 EPC:
19170433.7 / 3629368

(71) Applicant: Intel Corporation
Santa Clara, CA 95054 (US)

(72) Inventors:
  • Bohr, Mark
    Aloha, OR 97007 (US)
  • Kobrinsky, Mauro
    Portland, OR 97229 (US)
  • Nabors, Marni
    Portland, OR 97229 (US)

(74) Representative: Goddar, Heinz J. 
Boehmert & Boehmert Anwaltspartnerschaft mbB Pettenkoferstrasse 22
80336 München
80336 München (DE)

   


(54) DEEP VIA CONNECTIONS FOR TYCHE INTERCONNECTS


(57) Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.










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Search report