REFERENCE VOLTAGE GENERATION CIRCUIT AND AUTOMOTIVE-GRADE CHIP

Abstract

 The present invention provides a reference voltage generation circuit (30) and an automotive-grade chip. The reference voltage generation circuit (30) includes a biasing and voltage-limiting circuit (34), a PTAT current generation circuit (31), a zero-temperature coefficient reference voltage generation circuit (32), and a start-up circuit (33). The PTAT current generation circuit (31) includes a first P-channel MOS transistor (MP1), a second P-channel MOS transistor (MP2), a first N-channel MOS transistor (MN1), a second N-channel MOS transistor (MN2), and a first resistor (R1). An output end of the start-up circuit (33) is connected to a drain of the first N-channel MOS transistor (MN1). The biasing and voltage-limiting circuit (34) is connected to the drain of the first N-channel MOS transistor (MN1) to limit an operating voltage of the first N-channel MOS transistor (MN1). The zero-temperature coefficient reference voltage generation circuit (32) includes a second resistor (R2) and a bipolar junction transistor (B1). A PTAT current generated by the PTAT current generation circuit (31) flows through the second resistor (R2) to generate a PTAT voltage, and the PTAT voltage is superposed with a negative temperature coefficient voltage between a base electrode and an emitter electrode of the bipolar junction transistor (B1) to generate a zero-temperature coefficient reference voltage.

Description

TECHNICAL FIELD

[0001] This invention relates to the field of analog circuit design technology, and in particular to a reference voltage generation circuit and an automotive-grade chip.

BACKGROUND

[0002] With the rapid development of automobile industry and semiconductor industry, the automobile industry is in the era of scientific and technological innovation. In the future, automobiles will mainly develop in the direction of new energy, safety and intelligence, and new energy vehicles, intelligent networking and driverless technology will become the main trends. Automotive-grade chips are the basis of automotive electronics. At present, electronic products account for more than 50% of the vehicle cost, which has led to extensive investment in the design and development of the automotive-grade chips in the semiconductor industry in recent years.

[0003] Requirements for a temperature tolerance of a chip vary with the position and environment of the chip in the vehicle body. AEC_Q100, an automotive-grade standard launched by the North American automotive industry, divides a temperature tolerance of the automotive-grade chip into four grades. For Grade 0, a normal operating temperature of the chip is -40°C~150°C; for Grade 1, the normal operating temperature of the chip is - 40°C~125°C; for Grade 2, the normal operating temperature of the chip is -40°C~105°C; and for Grade 3, the normal operating temperature of the chip is -40°C~85°C. At high temperatures exceeding 125°C, the leakage problem of MOS (abbreviation of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)) devices becomes more and more significant, and seriously affects the performance of analog circuits, which is one of the design difficulties that distinguish the automotive-grade chips from ordinary consumer-grade chips.

SUMMARY

[0004] This invention aims to provide a reference voltage generation circuit and an automotive-grade chip, which can effectively solve the leakage problem of MOS devices.

[0005] An aspect of the present invention provides a reference voltage generation circuit. The reference voltage generation circuit comprises a biasing and voltage-limiting circuit, a proportional to absolute temperature (PTAT) current generation circuit, a zero-temperature coefficient reference voltage generation circuit, and a start-up circuit. The PTAT current generation circuit is configured to generate a PTAT current and comprises a first branch circuit, a second branch circuit, and a first resistor, the first branch circuit and the second branch circuit forming a current mirror, the first branch circuit comprising a first P-channel MOS transistor and a first N-channel MOS transistor, and the second branch circuit comprising a second P-channel MOS transistor and a second N-channel MOS transistor, wherein a source of the first P-channel MOS transistor and a source of the second P-channel MOS transistor are both connected to a power supply, and a gate of the first P-channel MOS transistor is connected to a gate of the second P-channel MOS transistor; a source of the first N-channel MOS transistor is connected to ground, a source of the second N-channel MOS transistor is connected to one end of the first resistor, the other end of the first resistor is connected to the ground, a gate of the first N-channel MOS transistor is connected to a gate of the second N-channel MOS transistor, a substrate of the first N-channel MOS transistor and a substrate of the second N-channel MOS transistor are connected to the ground, and the gate of the second N-channel MOS transistor is connected to a drain of the second N-channel MOS transistor. An input end of the start-up circuit is connected to the power supply and the gate of the first P-channel MOS transistor, and an output end of the start-up circuit is connected to a drain of the first N-channel MOS transistor. The biasing and voltage-limiting circuit is connected to the drain of the first N-channel MOS transistor to limit an operating voltage of the first N-channel MOS transistor. The zero-temperature coefficient reference voltage generation circuit comprises a second resistor and a bipolar junction transistor, wherein one end of the second resistor is connected to a reference voltage output end, the other end of the second resistor is connected to an emitter electrode of the bipolar junction transistor, and a collector electrode and a base electrode of the bipolar junction transistor are connected to the ground. The PTAT current generated by the PTAT current generation circuit flows through the second resistor to generate a PTAT voltage, which is superposed with a negative temperature coefficient voltage between the base electrode and the emitter electrode of the bipolar junction transistor to generate a zero-temperature coefficient reference voltage at the reference voltage output end.

[0006] In a particular embodiment, the first branch circuit further comprises a third P-channel MOS transistor, and the second branch circuit further comprises a fourth P-channel MOS transistor, wherein a drain of the first P-channel MOS transistor is connected to a source of the third P-channel MOS transistor, a drain of the second P-channel MOS transistor is connected to a source of the fourth P-channel MOS transistor, a gate of the third P-channel MOS transistor is connected to a gate of the fourth P-channel MOS transistor, a drain of the third P-channel MOS transistor is connected to the drain of the first N-channel MOS transistor, and a drain of the fourth P-channel MOS transistor is connected to the drain of the second N-channel MOS transistor.

[0007] In a particular embodiment, the zero-temperature coefficient reference voltage generation circuit further comprises a fifth P-channel MOS transistor and a sixth P-channel MOS transistor, wherein a source of the fifth P-channel MOS transistor is connected to the power supply, a drain of the fifth P-channel MOS transistor is connected to a source of the sixth P-channel MOS transistor, and a gate of the fifth P-channel MOS transistor is connected to the gate of the second P-channel MOS transistor; and a gate of the sixth P-channel MOS transistor is connected to the gate of the fourth P-channel MOS transistor, and a drain of the sixth P-channel MOS transistor is connected to the end of the second resistor connected to the reference voltage output end.

[0008] In a particular embodiment, the zero-temperature coefficient reference voltage generation circuit further comprises a third resistor, wherein the third resistor is connected in parallel with the second resistor and the bipolar junction transistor between the end of the second resistor connected to the reference voltage output end and the ground.

[0009] In a particular embodiment, different zero-temperature coefficient reference voltages are generated by adjusting a ratio of a resistance value of the third resistor to a sum of a resistance value of the second resistor and the resistance value of the third resistor, so as to adjust the minimum power supply voltage required for the reference voltage generation circuit.

[0010] In a particular embodiment, the biasing and voltage-limiting circuit comprises a third N-channel MOS transistor and a fourth resistor, wherein a source of the third N-channel MOS transistor is connected to one end of the fourth resistor, a drain of the third N-channel MOS transistor is connected to the gate of the third P-channel MOS transistor, a gate of the third N-channel MOS transistor is connected to the output end of the start-up circuit, and a substrate of the third N-channel MOS transistor is connected to the ground; and the other end of the fourth resistor is connected to the ground.

[0011] In a particular embodiment, the biasing and voltage-limiting circuit further comprises a seventh P-channel MOS transistor, an eighth P-channel MOS transistor, and a fifth resistor, wherein a source of the seventh P-channel MOS transistor is connected to the power supply, a drain of the seventh P-channel MOS transistor is connected to a source of the eighth P-channel MOS transistor, and a gate of the seventh P-channel MOS transistor is connected to a drain of the eighth P-channel MOS transistor and one end of the fifth resistor; and a gate of the eighth P-channel MOS transistor is connected to the other end of the fifth resistor and the drain of the third N-channel MOS transistor.

[0012] In a particular embodiment, at the beginning of power-up of the power supply, the start-up circuit pulls up the gate of the third N-channel MOS transistor; and upon completion of start-up of the reference voltage generation circuit, the start-up circuit is turned off through voltage feedback at the gate of the first P-channel MOS transistor.

[0013] In a particular embodiment, in the PTAT current generation circuit, the first P-channel MOS transistor, the third P-channel MOS transistor, the second P-channel MOS transistor, and the fourth P-channel MOS transistor form a current mirror with a mirror ratio of 1:1, and the second N-channel MOS transistor and the first N-channel MOS transistor are mirrored in a ratio of 5:1.

[0014] In a particular embodiment, the seventh P-channel MOS transistor and the eighth P-channel MOS transistor in the biasing and voltage-limiting circuit and the first P-channel MOS transistor and the third P-channel MOS transistor in the PTAT current generation circuit form a current mirror with a mirror ratio of 1:1, and the fourth resistor has a resistance value equal to that of the first resistor.

[0015] In a particular embodiment, the fifth P-channel MOS transistor and the sixth P-channel MOS transistor in the zero-temperature coefficient reference voltage generation circuit and the first P-channel MOS transistor and the third P-channel MOS transistor in the PTAT current generation circuit form a current mirror with a mirror ratio of 3:1, the third resistor has a resistance value three times that of the second resistor, and the resistance value of the second resistor is 7.2 times that of the first resistor.

[0016] Another aspect of the present invention provides an automotive-grade chip, comprising the reference voltage generation circuit as described above.

[0017] With the reference voltage generation circuit and the automotive-grade chip comprising the reference voltage generation circuit according to the present invention, the leakage problem of MOS devices can be effectively solved, and thus the problem that the zero-temperature coefficient reference voltage varies with the power supply voltage and temperature due to an increase in the power supply voltage or the temperature can be solved.

[0018] In addition, with the reference voltage generation circuit and the automotive-grade chip comprising the reference voltage generation circuit according to the present invention, the limitation on the minimum operating voltage in the circuit structure can be overcome.

BRIEF DESCRIPTION OF DRAWINGS

[0019] 

FIG. 1 is a circuit structure diagram of a reference voltage generation circuit.

FIG. 2 is a circuit structure diagram of another reference voltage generation circuit.

FIG. 3 is a circuit structure diagram of a reference voltage generation circuit according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0020] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, the same numerals in different drawings indicate the same or similar elements, unless otherwise indicated. Embodiments described in the following exemplary embodiments are not intended to be representative of all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses consistent with some aspects of the present invention as detailed in the appended claims.

[0021] Terminology used in the embodiments of the present invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. Unless otherwise defined, technical or scientific terms used in the embodiments of the present invention shall have their ordinary meanings as understood by a person of ordinary skill in the art to which the present invention belongs. The terms "first," "second," and the like, as used in the specification and claims of the present invention are not intended to denote any order, quantity, or importance, but are merely used to distinguish one element from another. Similarly, the terms "a" or "an" and the like are not intended to denote a limitation on quantity, but rather denote the presence of at least one. "A plurality of" or "several" means two or more. Unless otherwise indicated, the terms "front," "rear," "left," "right," "away from," "close to," "top," and/or "bottom" and the like are for convenience of description only and are not limited to a position or a spatial orientation. The terms "include" or "comprise" and the like are intended to mean that an element or item before "include" or "comprise" encompasses elements or items listed after "include" or "comprise" and equivalents thereof, without excluding other elements or items. The terms "connect" or "couple" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in the specification and the appended claims of the present invention, singular forms of "a," "an," "said," and "the" are intended to include plural forms as well, unless clearly indicated otherwise in the context. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

[0022] FIG. 1 illustrates a circuit structure diagram of a reference voltage generation circuit 10. The reference voltage generation circuit 10 has a simple structure, low power consumption, and small area. The reference voltage generation circuit 10 is widely used in scenarios where requirement for the accuracy of the reference voltage is not so high.

[0023] As shown in FIG. 1, the reference voltage generation circuit 10 generates a zero-temperature coefficient reference voltage expressed as follows:



where VREF is the zero-temperature coefficient reference voltage generated by the reference voltage generation circuit 10, VBE is a negative temperature coefficient voltage between a base electrode and an emitter electrode of a bipolar junction transistor B1, VGS_MN1 is a voltage between a gate and a source of a first N-channel MOS transistor MN1, VGS_MN2 is a voltage between a gate and a source of a second N-channel MOS transistor MN2, and (VGS_MN1-VGS_MN2) is a PTAT (Proportional To Absolute Temperature) voltage generated by the reference voltage generation circuit 10.

[0024] The zero-temperature coefficient reference voltage VREF can be obtained by superposing the negative temperature coefficient voltage VBE and the PTAT voltage (VGS_MN1-VGS_MN2), and appropriately setting a ratio of a resistance value of a second resistor R2 to a resistance value of a first resistor R1.

[0025] However, in the reference voltage generation circuit 10 as shown in FIG. 1, the voltage at point A is VGS_MN1, and the voltage at point B is (VDD-VGS_MP2), where VDD is a power supply voltage, and VGS_MP2 is a voltage between a gate and a source of a second P-channel MOS transistor MP2. When the power supply voltage VDD is relatively higher, for example, greater than 5V, a voltage difference between the point A and the point B is relatively larger, which may lead to a mirror mismatch in a current mirror formed by the first N-channel MOS transistor MN1 and the second N-channel MOS transistor MN2, resulting in a variation of the zero-temperature coefficient reference voltage VREF with the power supply voltage VDD.

[0026] FIG. 2 illustrates a circuit structure diagram of another reference voltage generation circuit 20. As shown in FIG. 2, in order to solve the above problem, a third N-channel MOS transistor MN3 is usually superposed at the second N-channel MOS transistor MN2 to form a cascode structure to shield the high voltage of (VDD-VGS_MP2). In this way, the voltage at the point B becomes (VB-VGS_MN3), where VB is a bias voltage applied to a gate of the third N-channel MOS transistor MN3, and VGS_MN3 is a voltage between the gate and a source of the third N-channel MOS transistor MN3. The design in which the third N-channel MOS transistor MN3 is added as shown in FIG. 2 is autonomously controllable, and the voltage at the point B can be close to the voltage at the point A by adjusting a voltage value of the bias voltage VB at the gate of the third N-channel MOS transistor MN3.

[0027] The design as shown in FIG. 2 can be used in application environments for consumer-grade produces with operating temperatures ranging from -40°C to 85°C. However, for industrial-grade products or even automotive-grade products, after the high temperature reaches 125°C or more, (VB-VGS_MN3) is generally designed to have a value of several hundred millivolts due to the fact that a source voltage of the third N-channel MOS transistor MN3 is greater than a substrate voltage of the third N-channel MOS transistor MN3. As a result, the third N-channel MOS transistor MN3 exhibits a significant substrate bias effect, generating a leakage current on the order of tens to hundreds of nanoamperes at a substrate thereof. A value of the leakage current increases as the power supply voltage VDD increases, and increases as the temperature increases, which, in turn, causes the zero-temperature coefficient reference voltage, VREF, to vary with the power supply voltage VDD and the temperature.

[0028] In the above circuit structure, in addition to an increase in the leakage current due to high temperature, the PTAT voltage (VGS_MN1-VGS_MN2) is relatively low, resulting in a relatively high voltage value of the operating voltage in the circuit structure, which exceeds 1.4V in practice, in order to obtain the zero-temperature coefficient reference voltage, VREF. This greatly limits the minimum operating voltage in the circuit structure.

[0029] In view of this, the present invention provides a reference voltage generation circuit 30 capable of solving the problem that the zero-temperature coefficient reference voltage VREF varies with the power supply voltage VDD and temperature due to an increase in the power supply voltage VDD or the temperature. In addition, the reference voltage generation circuit 30 according to the present invention can overcome the limitation on the minimum operating voltage in the circuit structure.

[0030] FIG. 3 illustrates a circuit structure diagram of a reference voltage generation circuit 30 according to an embodiment of the present invention. The reference voltage generation circuit 30 can be applied to automotive-grade chips and can withstand high temperature and high voltage. As shown in FIG. 3, the reference voltage generation circuit 30 according to an embodiment of the present invention includes a biasing and voltage-limiting circuit 34, a proportional to absolute temperature (PTAT) current generation circuit 31, a zero-temperature coefficient reference voltage generation circuit 32, and a start-up circuit 33.

[0031] The PTAT current generation circuit 31 is configured to generate a PTAT current. The PTAT current generation circuit 31 includes a first branch circuit, a second branch circuit, and a first resistor R1, with the first branch circuit and the second branch circuit forming a current mirror. The first branch circuit includes a first P-channel MOS transistor MP1 and a first N-channel MOS transistor MN1, and the second branch circuit includes a second P-channel MOS transistor MP2 and a second N-channel MOS transistor MN2. A source of the first P-channel MOS transistor MP1 and a source of the second P-channel MOS transistor MP2 are both connected to a power supply, and a gate of the first P-channel MOS transistor MP1 is connected to a gate of the second P-channel MOS transistor MP2. A source of the first N-channel MOS transistor MN1 is connected to ground VSS, a source of the second N-channel MOS transistor MN2 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to the ground VSS, a gate of the first N-channel MOS transistor MN1 is connected to a gate of the second N-channel MOS transistor MN2, a substrate of the first N-channel MOS transistor MN1 and a substrate of the second N-channel MOS transistor MN2 are connected to the ground VSS, and the gate of the second N-channel MOS transistor MN2 is connected to a drain of the second N-channel MOS transistor MN2.

[0032] An input end of the start-up circuit 33 is connected to the power supply and the gate of the first P-channel MOS transistor MP1, and an output end of the start-up circuit 33 is connected to a drain of the first N-channel MOS transistor MN1.

[0033] The biasing and voltage-limiting circuit 34 is connected to the drain of the first N-channel MOS transistor MN1 to limit an operating voltage of the first N-channel MOS transistor MN1.

[0034] The zero-temperature coefficient reference voltage generation circuit 32 includes a second resistor R2 and a bipolar junction transistor B1, where one end of the second resistor R2 is connected to a reference voltage output end, the other end of the second resistor R2 is connected to an emitter electrode of the bipolar junction transistor B, and a collector electrode and a base electrode of the bipolar junction transistor B1 are connected to the ground VSS.

[0035] The PTAT current generated by the PTAT current generation circuit 31 flows through the second resistor R2 to generate a PTAT voltage, which is superposed with a negative temperature coefficient voltage between the base electrode and the emitter electrode of the bipolar junction transistor B1 to generate a zero-temperature coefficient reference voltage VREF at the reference voltage output end.

[0036] In the circuit structure of the reference voltage generation circuit 30 according to the present invention, the first N-channel MOS transistor MN1 and the second N-channel MOS transistor MN2, as the core devices, both operate under the condition of a low substrate bias, and the voltage-limiting circuit is used to limit the operating voltage of the key MOS devices, such that the leakage of the key MOS devices under the condition of high temperature and high voltage can be ignored.

[0037] In some embodiments, the first branch circuit in the PTAT current generation circuit 31 further includes a third P-channel MOS transistor MP3, and the second branch circuit in the PTAT current generation circuit 31 further includes a fourth P-channel MOS transistor MP4. A drain of the first P-channel MOS transistor MP1 is connected to a source of the third P-channel MOS transistor MP3, a drain of the second P-channel MOS transistor MP2 is connected to a source of the fourth P-channel MOS transistor MP4, a gate of the third P-channel MOS transistor MP3 is connected to a gate of the fourth P-channel MOS transistor MP4, a drain of the third P-channel MOS transistor MP3 is connected to the drain of the first N-channel MOS transistor MN1, and a drain of the fourth P-channel MOS transistor MP4 is connected to the drain of the second N-channel MOS transistor MN2. Therefore, the mirror accuracy of the current mirror formed by the first branch circuit and the second branch circuit can be improved.

[0038] In some embodiments, the zero-temperature coefficient reference voltage generation circuit 32 further includes a fifth P-channel MOS transistor MP5 and a sixth P-channel MOS transistor MP6. A source of the fifth P-channel MOS transistor MP5 is connected to the power supply, a drain of the fifth P-channel MOS transistor MP5 is connected to a source of the sixth P-channel MOS transistor MP6, and a gate of the fifth P-channel MOS transistor MP5 is connected to the gate of the second P-channel MOS transistor MP2. A gate of the sixth P-channel MOS transistor MP6 is connected to the gate of the fourth P-channel MOS transistor MP4, and a drain of the sixth P-channel MOS transistor MP6 is connected to the end of the second resistor R2 connected to the reference voltage output end.

[0039] In some embodiments, the zero-temperature coefficient reference voltage generation circuit 32 further includes a third resistor R3. The third resistor R3 is connected in parallel with the second resistor R2 and the bipolar junction transistor B1 between the end of the second resistor R2 connected to the reference voltage output end and the ground VSS.

[0040] Therefore, with the second resistor R2 and the third resistor R3, the generated zero-temperature coefficient reference voltage VREF has a voltage division ratio, that is, a ratio of a resistance value of the third resistor R3 to a sum of a resistance value of the second resistor R2 and the resistance value of the third resistor R3, which can reduce a voltage value of the zero-temperature coefficient reference voltage VREF. Different zero-temperature coefficient reference voltages VREF can be generated by adjusting the ratio of the resistance value of the third resistor R3 to the sum of the resistance value of the second resistor R2 and the resistance value of the third resistor R3, so as to adjust the minimum power supply voltage VDD required for the reference voltage generation circuit 30, which is beneficial for the reference voltage generation circuit 30 to operate at a low power supply voltage VDD.

[0041] In some embodiments, the biasing and voltage-limiting circuit 34 may include a third N-channel MOS transistor MN3 and a fourth resistor R4. A source of the third N-channel MOS transistor MN3 is connected to one end of the fourth resistor R4, a drain of the third N-channel MOS transistor MN3 is connected to the gate of the third P-channel MOS transistor MP3, a gate of the third N-channel MOS transistor MN3 is connected to the output end of the start-up circuit 33, and a substrate of the third N-channel MOS transistor MN3 is connected to the ground VSS; and the other end of the fourth resistor R4 is connected to the ground VSS.

[0042] In some embodiments, the biasing and voltage-limiting circuit 34 further includes a seventh P-channel MOS transistor MP7, an eighth P-channel MOS transistor MP8, and a fifth resistor R5. A source of the seventh P-channel MOS transistor MP7 is connected to the power supply, a drain of the seventh P-channel MOS transistor MP7 is connected to a source of the eighth P-channel MOS transistor MP8, and a gate of the seventh P-channel MOS transistor MP7 is connected to a drain of the eighth P-channel MOS transistor MP8 and one end of the fifth resistor R5; and a gate of the eighth P-channel MOS transistor MP8 is connected to the other end of the fifth resistor R5 and the drain of the third N-channel MOS transistor MN3.

[0043] The output end of the start-up circuit 33 is connected to the gate of the third N-channel MOS transistor MN3. At the beginning of power-up of the power supply, the start-up circuit 33 may pull up the gate of the third N-channel MOS transistor MN3. Upon completion of start-up of the reference voltage generation circuit 30, the start-up circuit 33 may be turned off through voltage feedback at the gate of the first P-channel MOS transistor MP1, so as not to affect the normal operation of the reference voltage generation circuit 30.

[0044] The operation principle of the reference voltage generation circuit 30 according to the present invention will be described below with reference to FIG. 3.

[0045] As shown in FIG. 3, the PTAT current generated by the PTAT current generation circuit 31 is as follows:



where I_PTAT is the PTAT current generated by the PTAT current generation circuit 31, VGS_MN1 is the voltage between the gate and source of the first N-channel MOS transistor MN1, and VGS_MN2 is the voltage between the gate and source of the second N-channel MOS transistor MN2.

[0046] The fifth P-channel MOS transistor MP5 mirrors the PTAT current of the second P-channel MOS transistor MP2, and the zero-temperature coefficient reference voltage generation circuit 32 superposes the PTAT current I_PTAT with a negative temperature coefficient current VBE/R₂ to obtain the zero-temperature coefficient reference voltage VREF, as shown below:



where VBE is a negative temperature coefficient voltage between the base electrode and emitter electrode of the bipolar junction transistor B1, and (VGS_MN1-VGS_MN2) is the PTAT voltage.

[0047] The zero-temperature coefficient reference voltage VREF can be obtained by superposing the negative temperature coefficient voltage VBE with the PTAT voltage (VGS_MN1-VGS_MN2) and appropriately setting a ratio of the resistance value of the second resistor R2 to a resistance value of the first resistor R1.

[0048] By appropriately setting the ratio of the resistance value of the third resistor R3 to the sum of the resistance value of the second resistor R2 and the resistance value of the third resistor R3, the voltage value of the zero-temperature coefficient reference voltage VREF can be reduced, such that the minimum power supply voltage VDD required for the reference voltage generation circuit 30 can be reduced.

[0049] At the beginning of power-up of the power supply, the start-up circuit 33 pulls up the voltage at point A as the power supply voltage VDD increases until the third N-channel MOS transistor MN3 is turned on, and pulls down gate voltages of all the P-channel MOS transistors, and the voltage at point B increases accordingly. Upon the PTAT current generation circuit 31 is powered up, the start-up circuit 33 may be turned off through the voltage feedback at the gate of the first P-channel MOS transistor MP1. Thus, the start-up process of the reference voltage generation circuit 30 is completed.

[0050] The third N-channel MOS transistor MN3 and the fourth resistor R4 may limit the voltage at the point A to (ΔVGS₃+I₃×R₄), where ΔVGS₃ is a voltage difference between a gate voltage and a source voltage of the third N-channel MOS transistor MN3, I₃ is a value of current flowing through the fourth resistor R4, and R₄ is a resistance value of the fourth resistor R4. The voltage at the point B is (ΔVGS₂+I₁xR₁), where ΔVGS₂ is a voltage difference between a gate voltage and a source voltage of the second N-channel MOS transistor MN2, I₁ is a value of current flowing through the first resistor R1, and R₁ is the resistance value of the first resistor R1. The voltage at the point A is close to the voltage at the point B, and a current mirror formed by the first N-channel MOS transistor MN1 and the second N-channel MOS transistor MN2 has a relatively high mirror accuracy. A drain voltage of the first N-channel MOS transistor MN1 (i.e., the voltage at the point A) is limited, and meanwhile, the source and substrate of the first N-channel MOS transistor MN1 are both connected to the ground VSS, thus the first N-channel MOS transistor MN1 exhibits no substrate bias effect, and the influence of leakage of the first N-channel MOS transistor MN1 can be ignored.

[0051] The voltage at the point B is limited by the second N-channel MOS transistor MN2, and has a value of (ΔVGS₂+I₁×R₁), and the second N-channel MOS transistor MN2 has a substrate bias voltage of (I₁×R₁), which is usually several tens of millivolts. The voltage at the point B is limited, and meanwhile, the substrate bias voltage of the second N-channel MOS transistor MN2 is very low, and thus the influence of leakage of the second N-channel MOS transistor MN2 can be ignored.

[0052] Although the voltage at point C increases with the increase in the power supply voltage VDD, the third N-channel MOS transistor MN3 has a substrate bias voltage of (I₃×R₄), which is usually several tens of millivolts, and thus the influence of leakage of the third N-channel MOS transistor MN3 can also be ignored.

[0053] Therefore, the reference voltage generation circuit 30 according to the present invention can realize higher performance, reliability, and service life under higher power supply voltages VDD and automotive-grade high temperature standards.

[0054] Specific examples of the reference voltage generation circuit 30 according to the present invention are provided below.

[0055] In an embodiment, in the PTAT current generation circuit 31, the first P-channel MOS transistor MP1, the third P-channel MOS transistor MP3, the second P-channel MOS transistor MP2, and the fourth P-channel MOS transistor MP4 form a current mirror with a mirror ratio of 1:1, and the second N-channel MOS transistor MN2 and the first N-channel MOS transistor MN1 are mirrored in a ratio of 5:1.

[0056] In order to make the voltage at the point A and the voltage at the point B as equal as possible, the seventh P-channel MOS transistor MP7 and the eighth P-channel MOS transistor MP8 in the biasing and voltage-limiting circuit 34 and the first P-channel MOS transistor MP1 and the third P-channel MOS transistor MP3 in the PTAT current generation circuit 31 form a current mirror with a mirror ratio of 1:1, and the fourth resistor R4 has a resistance value equal to that of the first resistor R1.

[0057] The fifth P-channel MOS transistor MP5 and the sixth P-channel MOS transistor MP6 in the zero-temperature coefficient reference voltage generation circuit 32 and the first P-channel MOS transistor MP1 and the third P-channel MOS transistor MP3 in the PTAT current generation circuit 31 form a current mirror with a mirror ratio of 3:1, the third resistor R3 has a resistance value three times that of the second resistor R2, and the resistance value of the second resistor R2 is 7.2 times that of the first resistor R1.

[0058] At the beginning of power-up of the power supply, the start-up circuit 33 pulls up the gate of the third N-channel MOS transistor MN3. When current is generated in the reference voltage generation circuit 30 and the start-up of the reference voltage generation circuit 30 is completed, the start-up circuit 33 is turned off through the voltage feedback at the gate of the first P-channel MOS transistor MP1.

[0059] The PTAT current generation circuit 31 generates the PTAT current I_PTAT, the fifth P-channel MOS transistor MP5 mirrors the PTAT current of the second P-channel MOS transistor MP2, and the zero-temperature coefficient reference voltage generation circuit 32 superposes the PTAT current with the negative temperature coefficient current to obtain the zero-temperature coefficient reference voltage VREF, as shown below:

[0060] In this specific example, the resistance value of the third resistor R3 is three times the resistance value of the second resistor R2, and the resistance value of the second resistor R2 is 7.2 times the resistance value of the first resistor R1, resulting in the zero-temperature coefficient reference voltage VREF with a voltage value of 1.1V or less. By adjusting the ratio of the resistance value of the third resistor R3 to the sum of the resistance value of the second resistor R2 and the resistance value of the third resistor R3, R₃/(R₂+R₃), different zero-temperature coefficient reference voltages VREF can be obtained.

[0061] The reference voltage generation circuit 30 according to the present invention can be used in automotive-grade chips, completing standard testing of AEC_Q100 automotive-grade chips, and achieving good market application results.

[0062] It should be noted that the above specific design ratio of the reference voltage generation circuit is only an example, and is not limiting of the reference voltage generation circuit according to the present invention. The present invention is not limited to the above specific ratio, and the reference voltage generation circuit according to the present invention may have different ratios according to different application scenarios during specific implementation.

[0063] The present invention further provides an automotive-grade chip. The automotive-grade chip includes the reference voltage generation circuit 30 according to various embodiments as described above.

[0064] The reference voltage generation circuit and the automotive-grade chip according to the embodiments of the present invention have been described in detail above. Specific examples are used herein to describe the reference voltage generation circuit and the automotive-grade chip according to the embodiments of the present invention. The description of the above examples is only used to help understand the core idea of the present invention, and is not intended to limit the present invention. It should be noted that, for those ordinary skilled in the art, a number of improvements and modifications may be made to the present invention without departing from the principles of the present invention, and these improvements and modifications shall fall within the scope of protection of the appended claims.

Claims

1. A reference voltage generation circuit (30), characterized in that, the reference voltage generation circuit (30) comprises a biasing and voltage-limiting circuit (34), a proportional to absolute temperature, PTAT, current generation circuit (31), a zero-temperature coefficient reference voltage generation circuit (32), and a start-up circuit (33), wherein

the PTAT current generation circuit (31) is configured to generate a PTAT current and comprises a first branch circuit, a second branch circuit, and a first resistor (R1), the first branch circuit and the second branch circuit forming a current mirror, the first branch circuit comprising a first P-channel MOS transistor (MP1) and a first N-channel MOS transistor (MN1), and the second branch circuit comprising a second P-channel MOS transistor (MP2) and a second N-channel MOS transistor (MN2), wherein a source of the first P-channel MOS transistor (MP1) and a source of the second P-channel MOS transistor (MP2) are both connected to a power supply, and a gate of the first P-channel MOS transistor (MP1) is connected to a gate of the second P-channel MOS transistor (MP2); a source of the first N-channel MOS transistor (MN1) is connected to ground (VSS), a source of the second N-channel MOS transistor (MN2) is connected to one end of the first resistor (R1), the other end of the first resistor (R1) is connected to the ground (VSS), a gate of the first N-channel MOS transistor (MN1) is connected to a gate of the second N-channel MOS transistor (MN2), a substrate of the first N-channel MOS transistor (MN1) and a substrate of the second N-channel MOS transistor (MN2) are connected to the ground (VSS), and the gate of the second N-channel MOS transistor (MN2) is connected to a drain of the second N-channel MOS transistor (MN2);

an input end of the start-up circuit (33) is connected to the power supply and the gate of the first P-channel MOS transistor (MP1), and an output end of the start-up circuit (33) is connected to a drain of the first N-channel MOS transistor (MN1);

the biasing and voltage-limiting circuit (34) is connected to the drain of the first N-channel MOS transistor (MN1) to limit an operating voltage of the first N-channel MOS transistor (MN1); and

the zero-temperature coefficient reference voltage generation circuit (32) comprises a second resistor (R2) and a bipolar junction transistor (B1), wherein one end of the second resistor (R2) is connected to a reference voltage output end, the other end of the second resistor (R2) is connected to an emitter electrode of the bipolar junction transistor (B1), and a collector electrode and a base electrode of the bipolar junction transistor (B1) are connected to the ground (VSS),

wherein the PTAT current generated by the PTAT current generation circuit (31) flows through the second resistor (R2) to generate a PTAT voltage, and the PTAT voltage is superposed with a negative temperature coefficient voltage between the base electrode and the emitter electrode of the bipolar junction transistor (B1) to generate a zero-temperature coefficient reference voltage at the reference voltage output end.

2. The reference voltage generation circuit (30) according to claim 1, characterized in that, the first branch circuit further comprises a third P-channel MOS transistor (MP3), and the second branch circuit further comprises a fourth P-channel MOS transistor (MP4), wherein a drain of the first P-channel MOS transistor (MP1) is connected to a source of the third P-channel MOS transistor (MP3), a drain of the second P-channel MOS transistor (MP2) is connected to a source of the fourth P-channel MOS transistor (MP4), a gate of the third P-channel MOS transistor (MP3) is connected to a gate of the fourth P-channel MOS transistor (MP4), a drain of the third P-channel MOS transistor (MP3) is connected to the drain of the first N-channel MOS transistor (MN1), and a drain of the fourth P-channel MOS transistor (MP4) is connected to the drain of the second N-channel MOS transistor (MN2).

3. The reference voltage generation circuit (30) according to claim 2, characterized in that, the zero-temperature coefficient reference voltage generation circuit (32) further comprises a fifth P-channel MOS transistor (MP5) and a sixth P-channel MOS transistor (MP6), wherein a source of the fifth P-channel MOS transistor (MP5) is connected to the power supply, a drain of the fifth P-channel MOS transistor (MP5) is connected to a source of the sixth P-channel MOS transistor (MP6), and a gate of the fifth P-channel MOS transistor (MP5) is connected to the gate of the second P-channel MOS transistor (MP2); and a gate of the sixth P-channel MOS transistor (MP6) is connected to the gate of the fourth P-channel MOS transistor (MP4), and a drain of the sixth P-channel MOS transistor (MP6) is connected to the end of the second resistor (R2) connected to the reference voltage output end.

4. The reference voltage generation circuit (30) according to claim 3, characterized in that, the zero-temperature coefficient reference voltage generation circuit (32) further comprises a third resistor (R3), wherein the third resistor (R3) is connected in parallel with the second resistor (R2) and the bipolar junction transistor (B1) between the end of the second resistor (R2) connected to the reference voltage output end and the ground (VSS).

5. The reference voltage generation circuit (30) according to claim 4, characterized in that, different zero-temperature coefficient reference voltages are generated by adjusting a ratio of a resistance value of the third resistor (R3) to a sum of a resistance value of the second resistor (R2) and the resistance value of the third resistor (R3), so as to adjust the minimum power supply voltage required for the reference voltage generation circuit (30).

6. The reference voltage generation circuit (30) according to claim 2, characterized in that, the biasing and voltage-limiting circuit (34) comprises a third N-channel MOS transistor (MN3) and a fourth resistor (R4), wherein a source of the third N-channel MOS transistor (MN3) is connected to one end of the fourth resistor (R4), a drain of the third N-channel MOS transistor (MN3) is connected to the gate of the third P-channel MOS transistor (MP3), a gate of the third N-channel MOS transistor (MN3) is connected to the output end of the start-up circuit (33), and a substrate of the third N-channel MOS transistor (MN3) is connected to the ground (VSS); and the other end of the fourth resistor (R4) is connected to the ground (VSS).

7. The reference voltage generation circuit (30) according to claim 6, characterized in that, the biasing and voltage-limiting circuit (34) further comprises a seventh P-channel MOS transistor (MP7), an eighth P-channel MOS transistor (MP8), and a fifth resistor (R5), wherein a source of the seventh P-channel MOS transistor (MP7) is connected to the power supply, a drain of the seventh P-channel MOS transistor (MP7) is connected to a source of the eighth P-channel MOS transistor (MP8), and a gate of the seventh P-channel MOS transistor (MP7) is connected to a drain of the eighth P-channel MOS transistor (MP8) and one end of the fifth resistor (R5); and a gate of the eighth P-channel MOS transistor (MP8) is connected to the other end of the fifth resistor (R5) and the drain of the third N-channel MOS transistor (MN3).

8. The reference voltage generation circuit (30) according to claim 6, characterized in that, at the beginning of power-up of the power supply, the start-up circuit (33) pulls up the gate of the third N-channel MOS transistor (MN3); and upon completion of start-up of the reference voltage generation circuit (30), the start-up circuit (33) is turned off through voltage feedback at the gate of the first P-channel MOS transistor (MP1).

9. The reference voltage generation circuit (30) according to claim 2, characterized in that, in the PTAT current generation circuit (31), the first P-channel MOS transistor (MP1), the third P-channel MOS transistor (MP3), the second P-channel MOS transistor (MP2), and the fourth P-channel MOS transistor (MP4) form a current mirror with a mirror ratio of 1:1, and the second N-channel MOS transistor (MN2) and the first N-channel MOS transistor (MN1) are mirrored in a ratio of 5:1.

10. The reference voltage generation circuit (30) according to claim 7, characterized in that, the seventh P-channel MOS transistor (MP7) and the eighth P-channel MOS transistor (MP8) in the biasing and voltage-limiting circuit (34) and the first P-channel MOS transistor (MP1) and the third P-channel MOS transistor (MP3) in the PTAT current generation circuit (31) form a current mirror with a mirror ratio of 1:1, and the fourth resistor (R4) has a resistance value equal to that of the first resistor (R1).

11. The reference voltage generation circuit (30) according to claim 4, characterized in that, the fifth P-channel MOS transistor (MP5) and the sixth P-channel MOS transistor (MP6) in the zero-temperature coefficient reference voltage generation circuit (32) and the first P-channel MOS transistor (MP1) and the third P-channel MOS transistor (MP3) in the PTAT current generation circuit (31) form a current mirror with a mirror ratio of 3:1, the third resistor (R3) has a resistance value three times that of the second resistor (R2), and the resistance value of the second resistor (R2) is 7.2 times that of the first resistor (R1).

12. An automotive-grade chip, characterized in that, the automotive-grade chip comprises the reference voltage generation circuit (30) according to any one of claims 1 to 11.

Drawing