(19)
(11) EP 4 573 603 A1

(12)

(43) Date of publication:
25.06.2025 Bulletin 2025/26

(21) Application number: 23855275.6

(22) Date of filing: 02.05.2023
(51) International Patent Classification (IPC): 
H01L 29/788(2006.01)
H01L 21/74(2006.01)
H01L 21/24(2006.01)
G11C 11/401(2006.01)
H10B 12/00(2023.01)
H01L 27/00(2006.01)
(52) Cooperative Patent Classification (CPC):
H10B 12/20
(86) International application number:
PCT/US2023/020750
(87) International publication number:
WO 2024/039417 (22.02.2024 Gazette 2024/08)
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC ME MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA
Designated Validation States:
KH MA MD TN

(30) Priority: 17.08.2022 US 202263398807 P
14.09.2022 US 202263406255 P
30.09.2022 US 202217937432
05.10.2022 US 202263413493 P
24.10.2022 US 202263418698 P
14.02.2023 US 202363445670 P
14.02.2023 US 202363445672 P
03.03.2023 US 202363449938 P
07.04.2023 US 202363458059 P
18.04.2023 US 202363460289 P

(71) Applicant: NEO Semiconductor, Inc.
San Jose, CA 95126 (US)

(72) Inventor:
  • HSU, Fu-Chang
    San Jose, California 95129 (US)

(74) Representative: Liedtke & Partner Patentanwälte 
Gerhart-Hauptmann-Straße 10/11
99096 Erfurt
99096 Erfurt (DE)

   


(54) 3D MEMORY CELLS AND ARRAY ARCHITECTURES AND PROCESSES