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<ep-patent-document id="EP25220708A8W1" file="EP25220708W1A8.xml" lang="en" country="EP" doc-number="4766067" kind="A8" correction-code="W1" date-publ="20261021" status="c" dtd-version="ep-patent-document-v1-7-1">
<SDOBI lang="en"><B000><eptags><B001EP>ATBECHDEDKESFRGBGRITLILUNLSEMCPTIESILTLVFIROMKCYALTRBGCZEEHUPLSKBAHRIS..MTNORSMESMMAKHTNMDGELA......</B001EP><B005EP>J</B005EP><B007EP>0009190-CORR01</B007EP></eptags></B000><B100><B110>4766067</B110><B120><B121>CORRECTED EUROPEAN PATENT APPLICATION</B121></B120><B130>A8</B130><B132EP>A2</B132EP><B140><date>20261021</date></B140><B150><B151>W1</B151><B153>71</B153><B155><B1551>de</B1551><B1552>Bibliographie</B1552><B1551>en</B1551><B1552>Bibliography</B1552><B1551>fr</B1551><B1552>Bibliographie</B1552></B155></B150><B190>EP</B190></B100><B200><B210>25220708.9</B210><B220><date>20251204</date></B220><B250>en</B250><B251EP>en</B251EP><B260>en</B260></B200><B300><B310>202411887429</B310><B320><date>20241219</date></B320><B330><ctry>CN</ctry></B330></B300><B400><B405><date>20261021</date><bnum>202643</bnum></B405><B430><date>20260624</date><bnum>202626</bnum></B430><B480><date>20261021</date><bnum>202643</bnum></B480></B400><B500><B510EP><classification-ipcr sequence="1"><text>H10B  41/30        20230101AFI20260731BHEP        </text></classification-ipcr><classification-ipcr sequence="2"><text>H10D  30/68        20250101ALI20260731BHEP        </text></classification-ipcr><classification-ipcr sequence="3"><text>H10D  64/01        20250101ALI20260731BHEP        </text></classification-ipcr><classification-ipcr sequence="4"><text>H10B  41/10        20230101ALI20260731BHEP        </text></classification-ipcr><classification-ipcr sequence="5"><text>H10D  30/01        20250101ALI20260731BHEP        </text></classification-ipcr></B510EP><B520EP><classifications-cpc><classification-cpc sequence="1"><text>H10B  41/30        20230201 FI20260414BHEP        </text></classification-cpc><classification-cpc sequence="2"><text>H10D  64/035       20250101 LI20260414BHEP        </text></classification-cpc><classification-cpc sequence="3"><text>H10D  30/6891      20250101 LI20260414BHEP        </text></classification-cpc><classification-cpc sequence="4"><text>H10B  41/10        20230201 LI20260625BGEP        </text></classification-cpc><classification-cpc sequence="5"><text>H10D  30/0411      20250101 LI20260625BGEP        </text></classification-cpc><classification-cpc sequence="6"><text>H10D  30/6894      20250101 LI20260625BGEP        </text></classification-cpc><classification-cpc sequence="7"><text>H10D  30/6892      20250101 LI20260625BGEP        </text></classification-cpc></classifications-cpc></B520EP><B540><B541>de</B541><B542>VERFAHREN ZUR HERSTELLUNG EINES HALBLEITERBAUELEMENTS, HALBLEITERBAUELEMENT UND SPEICHERVORRICHTUNG</B542><B541>en</B541><B542>METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND MEMORY DEVICE</B542><B541>fr</B541><B542>PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMI-CONDUCTEUR, DISPOSITIF À SEMI-CONDUCTEUR ET DISPOSITIF DE MÉMOIRE</B542></B540><B590><B598>14</B598></B590></B500><B700><B710><B711><snm>GigaDevice Semiconductor (Shanghai) Inc.</snm><iid>102111085</iid><irf>4520251118</irf><adr><str>No.505, Zhangjiang Road</str><city>Shanghai 201210</city><ctry>CN</ctry></adr></B711><B711><snm>GIGADEVICE SEMICONDUCTOR (HEFEI) INC.</snm><iid>102117536</iid><irf>4520251118</irf><adr><str>No. 368 Qinghua Road
Economic &amp; Technological
Development Area</str><city>Hefei Anhui 230031</city><ctry>CN</ctry></adr></B711><B711><snm>GIGADEVICE SEMICONDUCTOR (XIAN) INC.</snm><iid>102117553</iid><irf>4520251118</irf><adr><str>15F,Building G1, Xi'an Huanpu
Technology Industrial Park
No.211,Tiangu 8th Road
Hi-tech Industrial Development Zone</str><city>Xi'an Shaanxi 710065</city><ctry>CN</ctry></adr></B711><B711><snm>GigaDevice Semiconductor Inc.</snm><iid>102070163</iid><irf>4520251118</irf><adr><str>Building No.8, IC Park
No.9 Fenghao East Road</str><city>Haidian, Beijing 100094</city><ctry>CN</ctry></adr></B711><B711><snm>Suzhou Freethink Information Technology Co., Ltd.</snm><iid>102143984</iid><irf>4520251118</irf><adr><str>12th Floor, Building N1 Industrial Park
No.88 Dongchang Road
Suzhou</str><city>Jiangsu 215000</city><ctry>CN</ctry></adr></B711></B710><B720><B721><snm>XU, Jing</snm><adr><city>No.505 Zhangjiang Road, Shanghai, 201210</city><ctry>CN</ctry></adr></B721><B721><snm>QIAN, Meng</snm><adr><city>No.505 Zhangjiang Road, Shanghai, 201210</city><ctry>CN</ctry></adr></B721><B721><snm>XU, Yisheng</snm><adr><city>No.505 Zhangjiang Road, Shanghai, 201210</city><ctry>CN</ctry></adr></B721></B720><B740><B741><snm>Herrero &amp; Asociados, S.L.</snm><iid>101579463</iid><adr><str>Edificio Aqua - Calle Agustín de Foxá, 4-10, 2ºA</str><city>28036 Madrid</city><ctry>ES</ctry></adr></B741></B740></B700><B800><B840><ctry>AL</ctry><ctry>AT</ctry><ctry>BE</ctry><ctry>BG</ctry><ctry>CH</ctry><ctry>CY</ctry><ctry>CZ</ctry><ctry>DE</ctry><ctry>DK</ctry><ctry>EE</ctry><ctry>ES</ctry><ctry>FI</ctry><ctry>FR</ctry><ctry>GB</ctry><ctry>GR</ctry><ctry>HR</ctry><ctry>HU</ctry><ctry>IE</ctry><ctry>IS</ctry><ctry>IT</ctry><ctry>LI</ctry><ctry>LT</ctry><ctry>LU</ctry><ctry>LV</ctry><ctry>MC</ctry><ctry>ME</ctry><ctry>MK</ctry><ctry>MT</ctry><ctry>NL</ctry><ctry>NO</ctry><ctry>PL</ctry><ctry>PT</ctry><ctry>RO</ctry><ctry>RS</ctry><ctry>SE</ctry><ctry>SI</ctry><ctry>SK</ctry><ctry>SM</ctry><ctry>TR</ctry></B840><B844EP><B845EP><ctry>BA</ctry></B845EP></B844EP><B848EP><B849EP><ctry>GE</ctry></B849EP><B849EP><ctry>KH</ctry></B849EP><B849EP><ctry>LA</ctry></B849EP><B849EP><ctry>MA</ctry></B849EP><B849EP><ctry>MD</ctry></B849EP><B849EP><ctry>TN</ctry></B849EP></B848EP><B880><date>20260909</date><bnum>202637</bnum></B880></B800></SDOBI>
<abstract id="abst" lang="en">
<p id="pa01" num="0001">A method for manufacturing a semiconductor device (10), a semiconductor device (10), and a memory device (1) are provided. The method includes forming (11, 21) shallow trench isolation structures (400) in a substrate (100), where first trenches (B) are defined between adjacent protruding portions of the shallow trench isolation structures (400); forming (12, 22) floating gates (500) in first trenches (B) and performing a first etching on a part of the protruding portions to form second trenches (C) between the adjacent floating gates (500); performing (13, 23) a narrowing process on the floating gates (500); performing (14, 24) a second etching on a remaining part of the protruding portions to widen the second trenches (C); and forming (15, 26) a control gate (600) partially filled in the second trenches (C).
<img id="iaf01" file="imgaf001.png" wi="78" he="46" img-content="drawing" img-format="png"/></p>
</abstract>
</ep-patent-document>
