THREAD TILING FOR MEMORY LATENCY REDUCTION - Patent 4816921

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EP 4 816 921 A1

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(43)	Date of publication:
	07.10.2026 Bulletin 2026/41

(21)	Application number: 23843992.1

(22)	Date of filing: 27.11.2023

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International Patent Classification (IPC):

G06F 9/38^(2018.01)

G06F 9/50^(2006.01)

(52)	Cooperative Patent Classification (CPC):
	G06F 9/3851; G06F 9/3887; G06F 9/5066; G06F 2209/5017; G06F 17/16

(86)	International application number:
	PCT/GR2023/000063

(87)	International publication number:
	WO 2025/114731 (05.06.2025 Gazette 2025/23)

(84)	Designated Contracting States:
	AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC ME MK MT NL NO PL PT RO RS SE SI SK SM TR
	Designated Extension States:
	BA
	Designated Validation States:
	KH MA MD TN

(71)	Applicant: Qualcomm Incorporated
	San Diego, CA 92121 (US)

(72)	Inventors:
	BARTSOKAS, Anastasios 26504 Rion Achaias (GR) GEORGAKAKIS, Dimitrios 26504 Rion Achaias (GR) KERAMIDAS, Georgios 26504 Rion Achaias (GR)

(74)	Representative: Wagner & Geyer
	Partnerschaft mbB Patent- und Rechtsanwälte Gewürzmühlstrasse 5 80538 München 80538 München (DE)

(54)	THREAD TILING FOR MEMORY LATENCY REDUCTION