SEMICONDUCTOR DEVICES AND SYSTEMS INCLUDING STACKED LOGIC DIES - Patent 4817101

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EP 4 817 101 A1

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(43)	Date of publication:
	07.10.2026 Bulletin 2026/41

(21)	Application number: 24898501.2

(22)	Date of filing: 18.11.2024

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International Patent Classification (IPC):

H01L 25/065^(2023.01)

H10B 80/00^(2026.01)

(52)	Cooperative Patent Classification (CPC):
	H10W 20/20; H10W 90/792; H10W 80/312; H10W 90/00; H10W 90/297

(86)	International application number:
	PCT/US2024/056340

(87)	International publication number:
	WO 2025/117230 (05.06.2025 Gazette 2025/23)

(84)	Designated Contracting States:
	AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC ME MK MT NL NO PL PT RO RS SE SI SK SM TR
	Designated Extension States:
	BA
	Designated Validation States:
	GE KH MA MD TN

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Priority:

01.12.2023 US 202318526418

(71)	Applicant: Advanced Micro Devices, Inc.
	Santa Clara, CA 95054 (US)

(72)	Inventors:
	SCHREIBER, Russell Austin, Texas 78735 (US) WUU, John Fort Collins, Colorado 80528 (US) OLIVER, Spence Austin, Texas 78735 (US)

(74)	Representative: Marks & Clerk LLP
	15 Fetter Lane London EC4A 1BW London EC4A 1BW (GB)

(54)	SEMICONDUCTOR DEVICES AND SYSTEMS INCLUDING STACKED LOGIC DIES