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<ep-patent-document id="EP24897987A1" file="EP24897987NWA1.xml" lang="en" country="EP" doc-number="4819172" kind="A1" date-publ="20261007" status="n" dtd-version="ep-patent-document-v1-7-1">
<SDOBI lang="en"><B000><eptags><B001EP>ATBECHDEDKESFRGBGRITLILUNLSEMCPTIESILTLVFIROMKCYALTRBGCZEEHUPLSKBAHRIS..MTNORSMESMMAKHTNMDGE........</B001EP><B005EP>J</B005EP><B007EP>0009011-RPUB02</B007EP></eptags></B000><B100><B110>4819172</B110><B120><B121>EUROPEAN PATENT APPLICATION</B121><B121EP>published in accordance with Art. 153(4) EPC</B121EP></B120><B130>A1</B130><B140><date>20261007</date></B140><B190>EP</B190></B100><B200><B210>24897987.4</B210><B220><date>20241119</date></B220><B240><B241><date>20260630</date></B241></B240><B250>ko</B250><B251EP>en</B251EP><B260>en</B260></B200><B300><B310>20230172173</B310><B320><date>20231201</date></B320><B330><ctry>KR</ctry></B330></B300><B400><B405><date>20261007</date><bnum>202641</bnum></B405><B430><date>20261007</date><bnum>202641</bnum></B430></B400><B500><B510EP><classification-ipcr sequence="1"><text>H01F  17/00        20060101AFI20250607BHEP        </text></classification-ipcr><classification-ipcr sequence="2"><text>H01F  27/28        20060101ALI20250607BHEP        </text></classification-ipcr></B510EP><B520EP><classifications-cpc><classification-cpc sequence="1"><text>H01F  27/28        20130101 LI20250623BCEP        </text></classification-cpc><classification-cpc sequence="2"><text>H01F  17/00        20130101 LI20250623BCEP        </text></classification-cpc></classifications-cpc></B520EP><B540><B541>de</B541><B542>TRANSFORMATOR</B542><B541>en</B541><B542>TRANSFORMER</B542><B541>fr</B541><B542>TRANSFORMATEUR</B542></B540><B590><B598>4</B598></B590></B500><B700><B710><B711><snm>LG Innotek Co., Ltd.</snm><iid>101850186</iid><irf>24810120EP</irf><adr><str>30, Magokjungang 10-ro
Gangseo-gu</str><city>Seoul 07796</city><ctry>KR</ctry></adr></B711></B710><B720><B721><snm>LEE, Jung Eun</snm><adr><city>Seoul 07796</city><ctry>KR</ctry></adr></B721><B721><snm>KIM, Seung Jin</snm><adr><city>Seoul 07796</city><ctry>KR</ctry></adr></B721><B721><snm>SOHN, In Seong</snm><adr><city>Seoul 07796</city><ctry>KR</ctry></adr></B721></B720><B740><B741><snm>DREISS Patentanwälte PartG mbB</snm><iid>101204860</iid><adr><str>Friedrichstraße 6</str><city>70174 Stuttgart</city><ctry>DE</ctry></adr></B741></B740></B700><B800><B840><ctry>AL</ctry><ctry>AT</ctry><ctry>BE</ctry><ctry>BG</ctry><ctry>CH</ctry><ctry>CY</ctry><ctry>CZ</ctry><ctry>DE</ctry><ctry>DK</ctry><ctry>EE</ctry><ctry>ES</ctry><ctry>FI</ctry><ctry>FR</ctry><ctry>GB</ctry><ctry>GR</ctry><ctry>HR</ctry><ctry>HU</ctry><ctry>IE</ctry><ctry>IS</ctry><ctry>IT</ctry><ctry>LI</ctry><ctry>LT</ctry><ctry>LU</ctry><ctry>LV</ctry><ctry>MC</ctry><ctry>ME</ctry><ctry>MK</ctry><ctry>MT</ctry><ctry>NL</ctry><ctry>NO</ctry><ctry>PL</ctry><ctry>PT</ctry><ctry>RO</ctry><ctry>RS</ctry><ctry>SE</ctry><ctry>SI</ctry><ctry>SK</ctry><ctry>SM</ctry><ctry>TR</ctry></B840><B844EP><B845EP><ctry>BA</ctry></B845EP></B844EP><B848EP><B849EP><ctry>GE</ctry></B849EP><B849EP><ctry>KH</ctry></B849EP><B849EP><ctry>MA</ctry></B849EP><B849EP><ctry>MD</ctry></B849EP><B849EP><ctry>TN</ctry></B849EP></B848EP><B860><B861><dnum><anum>KR2024018206</anum></dnum><date>20241119</date></B861><B862>ko</B862></B860><B870><B871><dnum><pnum>WO2025116391</pnum></dnum><date>20250605</date><bnum>202523</bnum></B871></B870></B800></SDOBI>
<abstract id="abst" lang="en">
<p id="pa01" num="0001">The present invention relates to a transformer in which parasitic capacitance is reduced by dividing a second conductive pattern, the transformer including: a core unit including an upper core and a lower core; a first conductive pattern substrate printed with a first conductive pattern forming at least one turn around a through-hole through which a center leg of the core unit passes; and a second conductive pattern substrate that is printed with the second conductive pattern composed of a plurality of metal plates divided on one plane and is disposed on at least one of the upper portion or the lower portion of the first conductive pattern substrate. By dividing a secondary coil pattern into multiple parts and disposing the multiple parts on a single substrate and connecting the multiple parts using a center tap, it is possible to reduce the inter-winding capacitance between a primary coil and secondary coils and the capacitance (parasitic capacitance) between the secondary coils, and lower the temperature of the generated heat while designing the stack height of the secondary coils to be low.<img id="iaf01" file="imgaf001.png" wi="99" he="59" img-content="drawing" img-format="png"/></p>
</abstract>
<description id="desc" lang="en"><!-- EPO <DP n="1"> -->
<heading id="h0001">[Technical Field]</heading>
<p id="p0001" num="0001">The present disclosure relates to a transformer and, more particularly, to a transformer in which a second conductive pattern is divided to reduce parasitic capacitance.</p>
<heading id="h0002">[Background Art]</heading>
<p id="p0002" num="0002">Magnetic elements are also referred to as magnetic coupling devices, and representative examples of magnetic elements may include an inductor, a transformer, and an EMI filter in which an inductor and a capacitor are connected. Such magnetic elements may be mounted on various types of circuit boards, for example, on a board of a power supply unit (PSU).</p>
<p id="p0003" num="0003">Recently, according to a trend toward slimmer electronic products, a slim magnetic element in which a coil constituting the magnetic element has a printed circuit board (PCB) form and shares a center leg of a magnetic core has been widely adopted.</p>
<p id="p0004" num="0004">A transformer may include a core unit, a primary coil unit, and a secondary coil unit. The core unit may include an upper core and a lower core, and a coil unit in a PCB form shown in <figref idref="f0001">FIG. 1</figref> is disposed between the upper core and the lower core.</p>
<p id="p0005" num="0005">In the coil unit, conductive patterns of the primary<!-- EPO <DP n="2"> --> coil and the secondary coil are stacked to perform a function of a coil. However, the conductive patterns have a problem in that loss may increase due to increase in resistance caused by a skin effect or due to an influence of a proximity effect between the conductive patterns. Such a problem may be alleviated to some extent by increasing a thickness of the conductive patterns. However, because the conductive patterns are generally formed of copper, increase in the thickness leads to increase in cost of the magnetic element, and a thickness of a pattern formed on a substrate is also limited.</p>
<heading id="h0003">[Disclosure]</heading>
<heading id="h0004">[Technical Problem]</heading>
<p id="p0006" num="0006">An aspect of the present disclosure is to provide a transformer capable of increasing efficiency by reducing leakage inductance.</p>
<p id="p0007" num="0007">Another aspect of the present disclosure is to provide a transformer capable of reducing parasitic capacitance and heat generation.</p>
<heading id="h0005">[Technical Solution]</heading>
<p id="p0008" num="0008">According to an aspect of the present disclosure, a transformer includes a core unit including an upper core and a lower core and a coil unit at least partially disposed inside the core unit. The coil unit includes a first conductive pattern<!-- EPO <DP n="3"> --> substrate including a first through-hole formed to allow a center leg of the core unit to pass through the first through-hole and a first conductive pattern forming at least one turn around the first through-hole and a second conductive pattern substrate including a second through-hole formed to allow the center leg of the core unit to pass through the second through-hole and a plurality of second conductive patterns forming at least one turn around the second through-hole. The second conductive pattern substrate is disposed in at least one of a region above the first conductive pattern substrate or a region below the first conductive pattern substrate.</p>
<p id="p0009" num="0009">In the transformer according to the present disclosure, the second conductive patterns include a first metal plate pattern NS1 and second metal plate patterns NS2 disposed to be spaced apart from each other with the first metal plate pattern NS1 interposed between the second metal plate patterns NS2.</p>
<p id="p0010" num="0010">In the transformer according to the present disclosure, the plurality of second metal plate patterns NS2 includes a 2-1<sup>st</sup> metal plate pattern NS2-1 disposed between the first metal plate pattern NS1 and the second through-hole and a 2-2<sup>nd</sup> metal plate pattern NS2-2 disposed to be spaced apart from the 2-1<sup>st</sup> metal plate pattern NS2-1.</p>
<p id="p0011" num="0011">In the transformer according to the present disclosure, the first conductive pattern substrate includes a first connection pattern CP1 formed adjacent to the first conductive<!-- EPO <DP n="4"> --> pattern, and the first connection pattern CP1 includes a first via hole and a second via hole.</p>
<p id="p0012" num="0012">In the transformer according to the present disclosure, each of the plurality of second metal plate patterns NS2 includes a via hole. The via hole in the 2-1<sup>st</sup> metal plate pattern NS2-1 is electrically connected to the first via hole, and the via hole in the 2-2<sup>nd</sup> metal plate pattern NS2-2 is electrically connected to the second via hole.</p>
<p id="p0013" num="0013">In the transformer according to the present disclosure, the first conductive pattern substrate includes a first upper substrate including a first wire pattern having a center tap formed at one side of the first wire pattern and a first lower substrate disposed below the first upper substrate and including a second wire pattern formed symmetrically to the first wire pattern.</p>
<p id="p0014" num="0014">In the transformer according to the present disclosure, the second conductive pattern substrate includes a second upper substrate disposed above the first conductive pattern substrate and a second lower substrate disposed below the first conductive pattern substrate and including a plurality of second conductive patterns.</p>
<p id="p0015" num="0015">In the transformer according to the present disclosure, the plurality of second conductive patterns of the second lower substrate includes a third metal plate pattern NS3 and a plurality of fourth metal plate patterns NS4 disposed to be<!-- EPO <DP n="5"> --> spaced apart from each other with the third metal plate pattern NS3 interposed between the plurality of fourth metal plate patterns NS4.</p>
<p id="p0016" num="0016">In the transformer according to the present disclosure, the 4-1st metal plate pattern and the 4-2nd metal plate pattern are electrically connected to each other.</p>
<p id="p0017" num="0017">In the transformer according to the present disclosure, the first lower substrate includes a second connection pattern CP2 formed adjacent to the second wire pattern, and the second connection pattern CP2 includes a third via hole and a fourth via hole.</p>
<p id="p0018" num="0018">In the transformer according to the present disclosure, each of the 4-1<sup>st</sup> metal plate pattern and the 4-2<sup>nd</sup> metal plate pattern includes a via hole. The via hole in the 4-1<sup>st</sup> metal plate pattern is electrically connected to the third via hole, and the via hole in the 4-2<sup>nd</sup> metal plate pattern is electrically connected to the fourth via hole.</p>
<p id="p0019" num="0019">The transformer according to the present disclosure may further include a conductive line disposed on the second conductive pattern substrate and configured to electrically connect the 2-1<sup>st</sup> metal plate pattern and the 2-2<sup>nd</sup> metal plate pattern to each other.</p>
<p id="p0020" num="0020">In the transformer according to the present disclosure, the first metal plate pattern NS1 and the second metal plate patterns NS2 may have different areas.<!-- EPO <DP n="6"> --></p>
<heading id="h0006">[Advantageous Effects]</heading>
<p id="p0021" num="0021">In the transformer according to the present disclosure, distribution of magnetic flux may be uniform, and accordingly, heat generation may be reduced. Further, an overlapping area between coils may be minimized, and accordingly, parasitic capacitance may be reduced.</p>
<p id="p0022" num="0022">The effects achievable through the disclosure are not limited to the above-mentioned effects, and other effects not mentioned herein will be clearly understood by those skilled in the art from the following description.</p>
<heading id="h0007">[Description of Drawings]</heading>
<p id="p0023" num="0023">
<ul id="ul0001" list-style="none" compact="compact">
<li><figref idref="f0001">FIG. 1</figref> is a view showing an example of the configuration of a general transformer.</li>
<li><figref idref="f0001">FIG. 2</figref> is a perspective view of a transformer according to the present disclosure.</li>
<li><figref idref="f0002">FIG. 3</figref> is an exploded perspective view of the transformer according to the present disclosure.</li>
<li><figref idref="f0003">FIG. 4</figref> is a divided plan view schematically showing arrangement of conductive pattern substrates in a transformer according to a first embodiment of the present disclosure.</li>
<li><figref idref="f0003">FIG. 5</figref> is a view showing a cross-section of the transformer according to the first embodiment and distribution of magnetic flux.<!-- EPO <DP n="7"> --></li>
<li><figref idref="f0004">FIG. 6</figref> is a divided plan view schematically showing arrangement of conductive pattern substrates in a transformer according to a second embodiment of the present disclosure.</li>
<li><figref idref="f0004">FIG. 7</figref> is a view showing a cross-section of the transformer according to the related art and distribution of magnetic flux.</li>
<li><figref idref="f0005">FIG. 8</figref> is a divided plan view schematically showing arrangement of conductive pattern substrates in a transformer according to a third embodiment of the present disclosure.</li>
<li><figref idref="f0005">FIG. 9</figref> is a divided plan view schematically showing arrangement of conductive pattern substrates in a transformer according to a fourth embodiment of the present disclosure.</li>
<li><figref idref="f0006">FIG. 10</figref> is a divided plan view schematically showing arrangement of conductive pattern substrates in a transformer according to a fifth embodiment of the present disclosure.</li>
<li><figref idref="f0006">FIG. 11</figref> is a divided plan view schematically showing arrangement of conductive pattern substrates in a transformer according to a sixth embodiment of the present disclosure.</li>
<li><figref idref="f0007">FIG. 12A</figref> is a view showing a noise waveform in the transformer according to the related art, and <figref idref="f0007">FIG. 12B</figref> is a view showing a noise waveform in the transformer according to the first embodiment.</li>
</ul></p>
<heading id="h0008">[Best Mode]</heading>
<p id="p0024" num="0024">Various exemplary embodiments will now be described<!-- EPO <DP n="8"> --> more fully with reference to the accompanying drawings, in which only some exemplary embodiments are shown. Specific structural and functional details disclosed herein are merely representative for the purpose of describing exemplary embodiments. The present disclosure, however, may be embodied in many alternative forms, and should not be construed as being limited to the exemplary embodiments set forth herein.</p>
<p id="p0025" num="0025">Accordingly, while exemplary embodiments of the disclosure are capable of being variously modified and taking alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit the present disclosure to the particular exemplary embodiments disclosed. On the contrary, exemplary embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure.</p>
<p id="p0026" num="0026">It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of exemplary embodiments of the present disclosure.</p>
<p id="p0027" num="0027">It will be understood that when an element is referred<!-- EPO <DP n="9"> --> to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g. "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).</p>
<p id="p0028" num="0028">The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the term "include" or "have", when used herein, specifies the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.</p>
<p id="p0029" num="0029">Unless otherwise defined, all terms used herein, which include technical or scientific terms, have the same meanings as those generally appreciated by those skilled in the art. The terms, such as ones defined in common dictionaries, should<!-- EPO <DP n="10"> --> be interpreted as having the same meanings as terms in the context of pertinent technology, and should not be interpreted as having ideal or excessively formal meanings unless clearly defined in the specification.</p>
<p id="p0030" num="0030">Meanwhile, when a certain embodiment is capable of being realized in a different manner, functions or operations specified in a specific block may be executed in an order different from that shown in a flowchart. For example, two consecutive blocks may be executed simultaneously, or may be executed in the reverse order, depending on the related function or operation.</p>
<p id="p0031" num="0031">Hereinafter, a magnetic element according to an embodiment will be described in detail with reference to the accompanying drawings. For convenience of description, a transformer will be described as an example of a magnetic coupling device with reference to <figref idref="f0001 f0002 f0003 f0004 f0005 f0006">FIGs. 2 to 10</figref>. However, the transformer is merely an example of the magnetic element according to the embodiment, and the disclosure is not necessarily limited thereto. For example, the magnetic element according to the embodiment may be a component of an inductor or an EMI filter.</p>
<p id="p0032" num="0032"><figref idref="f0001">FIG. 2</figref> is a perspective view of the transformer according to the present disclosure, and <figref idref="f0002">FIG. 3</figref> is an exploded perspective view of the transformer according to the present disclosure.<!-- EPO <DP n="11"> --></p>
<p id="p0033" num="0033">As shown, the transformer according to the present disclosure includes a core unit 100 and a coil unit 200. The core unit 100 has a characteristic of a magnetic circuit and thus may serve as a path of magnetic flux. The core unit 100 may include an upper core 110 coupled at an upper side and a lower core 120 coupled at a lower side.</p>
<p id="p0034" num="0034">The two cores 110 and 120 may have shapes that are vertically symmetrical to each other or asymmetrical to each other. One of the upper core 110 and the lower core 120 may be removed. However, in the following description, for convenience of description, it is assumed that the two cores 110 and 120 have vertically symmetrical shapes.</p>
<p id="p0035" num="0035">Each of the upper core 110 and the lower core 120 may include a body portion having a plate shape and a plurality of leg portions OL1-1, OL1-2, OL2-1, OL2-2, CL1, and CL2 protruding from the body portion in a first direction (i.e., a first-axis direction) and extending in a predetermined direction. For example, the plurality of leg portions OL1-1, OL1-2, and CL1 of the upper core 110 may include two outer legs OL1-1 and OL1-2 spaced apart from each other in a second direction (i.e., a second-axis direction) intersecting the first direction in a plane and one center leg CL1 disposed between the two outer legs OL1-1 and OL1-2. In addition, each of the plurality of leg portions OL1-1, OL1-2, OL2-1, OL2-2, CL1, and CL2 may extend in a third direction (i.e., a thirdaxis<!-- EPO <DP n="12"> --> direction) intersecting the first and second directions in a plane.</p>
<p id="p0036" num="0036">When the upper core 110 and the lower core 120 are coupled in the vertical direction, each of the outer legs OL1-1 and OL1-2 and the center leg CL1 of the upper core 110 faces a corresponding one of the outer legs OL2-1 and OL2-2 and the center leg CL2 of the lower core 120. A pair of outer legs OL1-1 and OL2-1 facing each other on one side may be referred to as a first outer leg portion, a pair of outer legs OL1-2 and OL2-2 facing each other on the other side may be referred to as a second outer leg portion, and a pair of center legs CL1 and CL2 may be referred to as a center leg portion.</p>
<p id="p0037" num="0037">A gap having a predetermined distance (e.g., 10 to 200 m, but not necessarily limited thereto) may be defined between at least some of the pairs of outer legs facing each other or the pair of center legs facing each other. Inductance of the core unit 100 may be controlled by adjusting the size of the gap of each of one pair of center legs and two pairs of outer legs, and heat generation may be controlled according to the number of gaps.</p>
<p id="p0038" num="0038">In addition, the core unit 100 may include a magnetic material, for example, iron or ferrite, but is not necessarily limited thereto.</p>
<p id="p0039" num="0039">Since the core unit 100 surrounds a portion of the coil unit 200, the portion of the coil unit 200 may be considered<!-- EPO <DP n="13"> --> to be disposed within the core unit 100.</p>
<p id="p0040" num="0040">The coil unit 200 includes a first conductive pattern substrate 210 and a second conductive pattern substrate 220.</p>
<p id="p0041" num="0041">Each of the first conductive pattern substrate 210 and the second conductive pattern substrate 220 has a through-hole TH through which the center leg portion CL1 and CL2 of the core unit 100 passes.</p>
<p id="p0042" num="0042">The first conductive pattern substrate 210 includes a first upper conductive pattern substrate 211 and a first lower conductive pattern substrate 212 disposed below the first upper conductive pattern substrate 211.</p>
<p id="p0043" num="0043">The second conductive pattern substrate 220 includes a second upper conductive pattern substrate 221 stacked on the first upper conductive pattern substrate 211 of the first conductive pattern substrate 210 in an insulated manner and a second lower conductive pattern substrate 222 disposed below the first lower conductive pattern 212 of the first conductive pattern substrate 210 in an insulated manner. Alternatively, each of the first conductive pattern substrate 210 and the second conductive pattern substrate 220 may be implemented as a single substrate.</p>
<p id="p0044" num="0044">The first conductive pattern substrate 210 may constitute a primary coil of the transformer, and the second conductive pattern substrate 220 may constitute a secondary coil of the transformer. Alternatively, in some embodiments,<!-- EPO <DP n="14"> --> the first conductive pattern substrate 210 may constitute a secondary coil of the transformer, and the second conductive pattern substrate 220 may constitute a primary coil of the transformer.</p>
<p id="p0045" num="0045">The second conductive pattern substrate 220 may include the second upper conductive pattern substrate 221 and the second lower conductive pattern substrate 222.</p>
<p id="p0046" num="0046">At one end of the coil unit 200 in a long-axis direction, first terminal portions TP1 may be disposed side by side so as to be spaced apart from each other in a short-axis direction of the coil unit 200. At the other end of the coil unit 200 opposite the one end in the long-axis direction, second terminal portions TP2 may be disposed side by side so as to be spaced apart from each other in the short-axis direction.</p>
<p id="p0047" num="0047">The terminal portions TP1 and TP2 may include a plurality of terminal pads TP1_1 to TP1_4 and TP2_1 to TP2_8 in order to electrically connect the transformer to a circuit portion formed on a substrate of an apparatus.</p>
<p id="p0048" num="0048">The terminal pads TP1_1 to TP1_4 and TP2_1 to TP2_8 may be disposed on each of the plurality of conductive pattern substrates 211, 212, 221, and 222. The terminal pads of the conductive patterns may be vertically aligned and conductively connected to each other.</p>
<p id="p0049" num="0049"><figref idref="f0003">FIG. 4</figref> is a divided plan view schematically showing arrangement of conductive pattern substrates in a transformer<!-- EPO <DP n="15"> --> according to a first embodiment of the present disclosure. In the drawing, a plurality of conductive pattern substrates 221A, 211A, 212A, and 222A stacked from above to form the coil unit 200 is illustrated as being sequentially arranged from left to right. In this case, a first metal plate pattern NS1 and second metal plate patterns NS2-1 and NS2-2 on the second upper conductive pattern substrate 221A are disposed symmetrically to those on the second lower conductive pattern substrate 222A. In the transformer according to the present disclosure, the first metal plate pattern NS1 and the second metal plate patterns NS2 may have different areas.</p>
<p id="p0050" num="0050">On the second upper conductive pattern substrate 221A of the second conductive pattern substrate 220 that is disposed at an uppermost position, a 2-1<sup>st</sup> metal plate pattern NS2-1 and a 2-2<sup>nd</sup> metal plate pattern NS2-2 are disposed to be spaced apart from each other with the first metal plate pattern NS1 interposed therebetween. In this case, the 2-1<sup>st</sup> metal plate pattern NS2-1 is disposed to surround a second through-hole TH2. The 2-1<sup>st</sup> metal plate pattern NS2-1 and the 2-2<sup>nd</sup> metal plate pattern NS2-2 spaced apart from each other include via holes VH1 and VH2, respectively, through which the 2-1<sup>st</sup> metal plate pattern NS2-1 and the 2-2<sup>nd</sup> metal plate pattern NS2-2 are electrically connected to each other. In this case, electrical connection is achieved through first via holes VH1 and second via holes VH2 in a first connection pattern CP1 formed on the<!-- EPO <DP n="16"> --> first upper conductive pattern substrate 211A disposed below the second upper conductive pattern substrate 221A.</p>
<p id="p0051" num="0051">The first upper conductive pattern substrate 211A includes a first wire pattern 201A forming at least one turn in the counterclockwise direction around a first through-hole TH1 formed at a center thereof. The first lower conductive pattern substrate 212A includes a second wire pattern 202A forming at least one turn in the clockwise direction around the first through-hole TH1 formed at a center thereof. The first wire pattern 201A is electrically connected to the second wire pattern 202A disposed on the first lower conductive pattern substrate 212A. To this end, fifth via holes VH5 are formed at one end of the first wire pattern 201A and at one end of the second wire pattern 202A.</p>
<p id="p0052" num="0052">Among the first to fifth via holes formed in the conductive patterns and the wire patterns on the respective conductive pattern substrates, via holes that overlap in the vertical direction and are electrically connected to each other are denoted by the same reference numerals.</p>
<p id="p0053" num="0053">Meanwhile, for the same purpose as the first connection pattern CP1 formed on the first upper conductive pattern substrate 211A, a second connection pattern CP2 is formed on the first lower conductive pattern substrate 212A. Third via holes VH3 and fourth via holes VH4 are formed in the second connection pattern CP2. A 4-1<sup>st</sup> metal plate pattern NS4-1 and<!-- EPO <DP n="17"> --> a 4-2<sup>nd</sup> metal plate pattern NS4-2, which are formed to be spaced apart from each other on the second lower conductive pattern substrate 222A, are electrically connected to each other via the third via holes VH3 and the fourth via holes VH4. In this case, electrical connection is achieved through the third via holes VH3 and the fourth via holes VH4 formed in the first lower conductive pattern substrate 212A.</p>
<p id="p0054" num="0054"><figref idref="f0003">FIG. 5</figref> is a view showing a cross-section of the transformer according to the first embodiment and distribution of magnetic flux. As shown in <figref idref="f0003">FIG. 5</figref>, in the transformer according to the present disclosure, the first metal plate pattern NS1 and the second metal plate patterns NS2 disposed on the second upper conductive pattern substrate may have a structure symmetrical to the first metal plate pattern NS1 and the second metal plate patterns NS2 disposed on the second lower conductive pattern substrate with respect to the primary coil.</p>
<p id="p0055" num="0055"><figref idref="f0004">FIG. 6</figref> is a divided plan view schematically showing arrangement of conductive pattern substrates in a transformer according to a second embodiment of the present disclosure, and <figref idref="f0004">FIG. 7</figref> is a view showing a cross-section of the transformer according to the second embodiment and distribution of magnetic flux. In <figref idref="f0004">FIG. 6</figref>, a plurality of conductive pattern substrates 221B, 211B, 212B, and 222B stacked from above to form the coil unit, similarly to the first embodiment shown in <figref idref="f0003">FIG. 4</figref>, is<!-- EPO <DP n="18"> --> illustrated as being sequentially arranged from left to right. In this case, a first metal plate pattern NS1 and second metal plate patterns NS2-1 and NS2-2 on the second upper conductive pattern substrate 221B are disposed at the same positions as and vertically overlap those on the second lower conductive pattern substrate 222B.</p>
<p id="p0056" num="0056">On the second upper conductive pattern substrate 221B of the second conductive pattern substrate 220 that is disposed at an uppermost position, a first metal plate pattern NS1 and second metal plate patterns NS2 are formed. The second metal plate patterns NS2 include a 2-1<sup>st</sup> metal plate pattern NS2-1 and a 2-2<sup>nd</sup> metal plate pattern NS2-2 disposed to be spaced apart from each other with the first metal plate pattern NS1 interposed therebetween. In this case, the 2-1<sup>st</sup> metal plate pattern NS2-1, which is one of the second metal plate patterns, is disposed to surround a second through-hole TH2. The second metal plate patterns NS2-1 and NS2-2 spaced apart from each other are electrically connected to each other via first via holes VH1 and second via holes VH2 formed in the respective patterns. In this case, electrical connection is achieved through first via holes VH1 and second via holes VH2 in a first connection substrate CP1 formed on the first upper conductive pattern substrate 211B disposed below the second upper conductive pattern substrate 221B.</p>
<p id="p0057" num="0057">The first upper conductive pattern substrate 211B<!-- EPO <DP n="19"> --> includes a first wire pattern 201B forming at least one turn in the counterclockwise direction around a first through-hole TH1 formed at a center thereof. The first lower conductive pattern substrate 212B includes a second wire pattern 202B forming at least one turn in the clockwise direction around the first through-hole TH1 formed at a center thereof. The first wire pattern 201B is electrically connected to the second wire pattern 202B disposed on the first lower conductive pattern substrate 212B. To this end, fifth via holes VH5 are formed at one end of the first wire pattern 201B and at one end of the second wire pattern 202B.</p>
<p id="p0058" num="0058">Meanwhile, unlike the first embodiment, on the first lower conductive pattern substrate 212B according to the second embodiment, a second connection pattern CP2 having the same shape as the first connection pattern CP1 of the first upper conductive pattern substrate 211B is formed at the same position in the vertical direction as the first connection pattern CP1. Third via holes VH3 and fourth via holes VH4 for electrical connection to the second lower conductive pattern substrate 222B are formed in the second connection pattern CP2.</p>
<p id="p0059" num="0059">Fourth metal plate patterns NS4-1 and NS4-2, which are formed on the second lower conductive pattern substrate 222B so as to be spaced apart from each other, include three via holes VH3 and fourth via holes VH4 formed at positions overlapping the aforementioned third via holes VH3 and fourth<!-- EPO <DP n="20"> --> via holes VH4 in the vertical direction.</p>
<p id="p0060" num="0060">The via holes VH3 in the 4-1<sup>st</sup> metal plate pattern NS4-1 of the second lower conductive pattern substrate 222B are electrically connected to the third via holes VH3 in the first lower conductive pattern substrate 212B, and the fourth via holes VH4 in the 4-2<sup>nd</sup> metal plate pattern NS4-2 of the second lower conductive pattern substrate 222B are electrically connected to the fourth via holes VH4 in the first lower conductive pattern substrate 212B.</p>
<p id="p0061" num="0061">The transformer according to the present disclosure may have a structure in which the first metal plate pattern NS1 and the second metal plate patterns NS2-1 and NS2-2 disposed on the second upper conductive pattern substrate 221B are disposed to overlap the third metal pattern NS3 and the fourth metal plate patterns NS4-1 and NS4-2 disposed on the second lower conductive pattern substrate 222B in the vertical direction.</p>
<p id="p0062" num="0062">Referring to <figref idref="f0003">FIGs. 5</figref> and <figref idref="f0004">7</figref>, in the transformer according to the related art having the structure shown in <figref idref="f0004">FIG. 7</figref>, current flowing in the secondary coil alternately flows through the upper and lower portions NS1 and NS2. Accordingly, magnetic flux is not uniformly distributed throughout an entire core but is non-uniformly biased in one direction. However, in the first and second embodiments of the present disclosure, the secondary coil is configured such that the first metal<!-- EPO <DP n="21"> --> plate pattern NS1 and the second metal plate patterns NS2 are disposed on the same plane, and thus current alternately flows through the patterns NS1 disposed in vertically symmetrical positions and the patterns NS2 disposed in vertically symmetrical positions. Accordingly, as compared with the conventional structure, magnetic flux is distributed relatively uniformly, and heat generation is reduced.</p>
<p id="p0063" num="0063"><figref idref="f0005">FIG. 8</figref> is a divided plan view schematically showing arrangement of conductive pattern substrates in a transformer according to a third embodiment of the present disclosure, and <figref idref="f0005">FIG. 9</figref> is a divided plan view schematically showing arrangement of conductive pattern substrates in a transformer according to a fourth embodiment of the present disclosure.</p>
<p id="p0064" num="0064">The common feature of the first and second embodiments is that the second metal plate patterns NS2-1 and NS2-2 divided with the first metal plate pattern NS1 interposed therebetween on the second upper conductive pattern substrate 221A or 221B are electrically connected to each other via the first via holes VH1 and the second via holes VH2 formed in the first connection pattern CP1 formed on the first upper conductive pattern substrate 211A or 211B. In addition, the fourth metal plate patterns NS4-1 and NS4-2 divided with the third metal plate pattern NS3 interposed therebetween on the second lower conductive pattern substrate 222A or 222B are electrically connected to each other via the third via holes VH3 and the<!-- EPO <DP n="22"> --> fourth via holes VH4 formed in the second connection pattern CP2 formed on the first lower conductive pattern substrate 212A or 212B.</p>
<p id="p0065" num="0065">In the third and fourth embodiments shown in <figref idref="f0005">FIGs. 8 and 9</figref>, electrical connection between the divided second metal plate patterns NS2-1 and NS2-2 and between the divided fourth metal plate patterns NS4-1 and NS4-2 is achieved using conductive lines, for example, busbars.</p>
<p id="p0066" num="0066">Referring to <figref idref="f0005">FIG. 8</figref>, the third embodiment is configured such that a first metal plate pattern NS1 and second metal plate patterns NS2-1 and NS2-2 spaced apart from each other with the first metal plate pattern NS1 interposed therebetween are disposed on a second upper conductive pattern substrate 221C disposed at an uppermost position. In this case, the 2-1<sup>st</sup> metal plate pattern NS2-1, which is one of the second metal plate patterns, is disposed to surround a second through-hole TH2. In this case, the 2-1<sup>st</sup> metal plate pattern NS2-1 and the 2-2<sup>nd</sup> metal plate pattern NS2-2, which are spaced apart from each other, are electrically connected to each other via a first upper conductive line L11.</p>
<p id="p0067" num="0067">A first upper conductive pattern substrate 211C includes a first wire pattern 201C forming at least one turn in the counterclockwise direction around a first through-hole TH1 formed at a center thereof. A first lower conductive pattern substrate 212C includes a second wire pattern 202C<!-- EPO <DP n="23"> --> forming at least one turn in the clockwise direction around the first through-hole TH1 formed at a center thereof. The first wire pattern 201C of the first upper conductive pattern substrate 212C is electrically connected to the second wire pattern 202C disposed on the first lower conductive pattern substrate 212C. To this end, fifth via holes VH5 are formed at one end of the first wire pattern 201C and at one end of the second wire pattern 202C.</p>
<p id="p0068" num="0068">Metal plate patterns NS3, NS4-1, and NS4-2 are formed on a second lower conductive pattern substrate 222C so as to be symmetrical to those on the second upper conductive pattern substrate 221C in the second direction with respect to the second through-hole TH2. In this case, the 4-1<sup>st</sup> metal pattern NS4-1 and the 4-2<sup>nd</sup> metal plate pattern NS4-2, which are spaced apart from each other on the second lower substrate 222C, are electrically connected to each other via a first lower conductive line L21.</p>
<p id="p0069" num="0069">Referring to <figref idref="f0005">FIG. 9</figref>, the fourth embodiment is configured such that second metal plate patterns NS2-1 and NS2-2 spaced apart from each other with a first metal plate pattern NS1 interposed therebetween are disposed on a second upper conductive pattern substrate 221D disposed at an uppermost position. In this case, the 2-1<sup>st</sup> metal plate pattern NS2-1, which is one of the second metal plate patterns, is disposed to surround a second through-hole TH2. In this case, the 2-1<sup>st</sup><!-- EPO <DP n="24"> --> metal plate pattern NS2-1 and the 2-2<sup>nd</sup> metal plate pattern NS2-2, which are spaced apart from each other, are electrically connected to each other via a second upper conductive line L21.</p>
<p id="p0070" num="0070">A first upper conductive pattern substrate 211D includes a first wire pattern 201D forming at least one turn in the counterclockwise direction around a first through-hole TH1 formed at a center thereof. A first lower conductive pattern substrate 212D includes a second wire pattern 202D forming at least one turn in the clockwise direction around the first through-hole TH1 formed at a center thereof. The first wire pattern 201D is electrically connected to the second wire pattern 202D disposed on the first lower conductive pattern substrate 212D. To this end, fifth via holes VH5 are formed at one end of the first wire pattern 201D and at one end of the second wire pattern 202D. Metal plate patterns having the same shape as those on the second upper conductive pattern substrate 221D are disposed on a second lower conductive pattern substrate 222D. That is, on the second lower conductive pattern substrate 222D, a 4-1<sup>st</sup> metal plate pattern NS4-1 and a 4-2<sup>nd</sup> metal plate pattern NS4-2 are disposed to be spaced apart from each other with a third metal plate pattern NS3 interposed therebetween. In this case, the 4-1<sup>st</sup> metal plate pattern NS4-1 and the 4-2<sup>nd</sup> metal plate pattern NS4-2, which are spaced apart from each other on the second lower conductive pattern substrate 222D, are electrically<!-- EPO <DP n="25"> --> connected to each other via a second lower conductive line L22.</p>
<p id="p0071" num="0071"><figref idref="f0006">FIG. 10</figref> is a divided plan view schematically showing arrangement of conductive pattern substrates in a transformer according to a fifth embodiment of the present disclosure. Unlike the transformers according to the first to fourth embodiments, a second conductive pattern substrate is configured as a single second conductive pattern substrate 220E. A first conductive pattern substrate 210 includes a first upper conductive pattern substrate 211E and a first lower conductive pattern substrate 212E. A first metal plate pattern NS1 and second metal plate patterns NS2 are formed on the second conductive pattern substrate 220E. The second metal plate patterns NS2 include a 2-1<sup>st</sup> metal pattern NS2-1 and a 2-2<sup>nd</sup> metal pattern NS2-2. The 2-1<sup>st</sup> metal pattern NS2-1 and the 2-2<sup>nd</sup> metal pattern NS2-2 are disposed to be spaced apart from each other with the first metal plate pattern NS1 interposed therebetween. In this case, the 2-1<sup>st</sup> metal plate pattern NS2-1 is disposed to surround a second through-hole TH2. The 2-1<sup>st</sup> metal plate pattern NS2-1 and the 2-2<sup>nd</sup> metal plate pattern NS2-2, which are spaced apart from each other, are electrically connected to each other via first via holes VH1 and second via holes VH2 formed in the respective patterns. In this case, electrical connection is achieved through first via holes VH1 and second via holes VH2 in a first connection pattern CP1 formed on the first upper conductive pattern substrate 211E<!-- EPO <DP n="26"> --> disposed below the second conductive pattern substrate 220E.</p>
<p id="p0072" num="0072">The first upper conductive pattern substrate 211E includes a first wire pattern 201E forming at least one turn in the counterclockwise direction around a first through-hole TH1 formed at a center thereof. The first lower conductive pattern substrate 212E includes a second wire pattern 202E forming at least one turn in the clockwise direction around the first through-hole TH1 formed at a center thereof. The first wire pattern 201E is electrically connected to the second wire pattern 202E disposed on the first lower conductive pattern substrate 212EA. To this end, fifth via holes VH5 are formed at one end of the first wire pattern 201E and at one end of the second wire pattern 202E.</p>
<p id="p0073" num="0073"><figref idref="f0006">FIG. 11</figref> is a divided plan view schematically showing arrangement of conductive pattern substrates in a transformer according to a sixth embodiment of the present disclosure. In this embodiment, each of a first conductive pattern substrate and a second conductive pattern substrate is configured as a single substrate. In this case, the second conductive pattern substrate 220F includes a first metal plate pattern NS1 and second metal plate patterns NS2. The second metal plate patterns NS2 include a 2-1<sup>st</sup> metal plate pattern NS2-1 and a 2-2<sup>nd</sup> metal plate pattern NS2-2. The 2-1<sup>st</sup> metal plate pattern NS2-1 and the 2-2<sup>nd</sup> metal plate pattern NS2-2 are disposed to be spaced apart from each other with the first metal plate<!-- EPO <DP n="27"> --> pattern NS1 interposed therebetween. The 2-1<sup>st</sup> metal plate pattern NS2-1 and the 2-2<sup>nd</sup> metal plate pattern NS2-2, which are spaced apart from each other, are electrically connected to each other via first via holes VH1 and second via holes VH2 formed in the respective patterns. In this case, electrical connection is achieved through first via holes VH1 and second via holes VH2 in a first connection pattern CP1 formed on the first conductive pattern substrate 210F. The first conductive pattern substrate 210F includes a first wire pattern 201F forming at least one turn in the counterclockwise direction around a first through-hole TH1 formed at a center thereof.</p>
<p id="p0074" num="0074">In the transformer according to the related art having a structure in which pattern substrates of a printed circuit board-type secondary coil vertically overlap each other, when capacitance between the primary coil and the secondary coil is 230 pF, capacitance between the substrates of the secondary coil is measured to be 90.44 pF, and temperature is measured to be 81.2°C. <figref idref="f0007">FIG. 12A</figref> is a view showing a noise waveform in the transformer according to the related art.</p>
<p id="p0075" num="0075">Meanwhile, in the first embodiment of the present disclosure in which the secondary coil is configured such that the first metal plate pattern NS1 and the second metal plate patterns NS2 are disposed on the same plane and the second metal plate patterns NS2 include the 2-1<sup>st</sup> metal plate pattern NS2-1 and the 2-2<sup>nd</sup> metal plate pattern NS2-2 spaced apart from<!-- EPO <DP n="28"> --> each other with the first metal plate pattern NS1 interposed therebetween, when capacitance between the primary coil and the secondary coil is 120 pF, capacitance between the substrates of the secondary coil is measured to be 79.9 pF, and temperature is measured to be 73.7°C. That is, since current is transmitted in vertically symmetrical directions, distribution of magnetic flux becomes uniform as compared with the conventional structure, and thus parasitic capacitance and temperature are reduced as compared with the related art. Accordingly, referring to the noise waveform illustrated in <figref idref="f0007">FIG. 12B</figref>, it can be confirmed that noise in a waveform is reduced.</p>
<p id="p0076" num="0076">As described above, since the divided secondary coil patterns are disposed on one substrate and are connected to each other using a center tap, inter-winding capacitance between the primary coil and the secondary coil and parasitic capacitance between the substrates of the secondary coil may be reduced. Further, as a stacked height of the secondary coil is designed to be low, heat generation may be reduced.</p>
<p id="p0077" num="0077">Although the exemplary embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure as disclosed in the accompanying claims.<!-- EPO <DP n="29"> --></p>
<heading id="h0009">[Industrial Applicability]</heading>
<p id="p0078" num="0078">The transformer according to the present disclosure may be applied to various electronic devices.</p>
</description>
<claims id="claims01" lang="en"><!-- EPO <DP n="30"> -->
<claim id="c-en-0001" num="0001">
<claim-text>A transformer, comprising:
<claim-text>a core unit comprising an upper core and a lower core; and</claim-text>
<claim-text>a coil unit at least partially disposed inside the core unit,</claim-text>
<claim-text>wherein the coil unit comprises:
<claim-text>a first conductive pattern substrate comprising a first through-hole formed to allow a center leg of the core unit to pass through the first through-hole and a first conductive pattern forming at least one turn around the first through-hole; and</claim-text>
<claim-text>a second conductive pattern substrate comprising a second through-hole formed to allow the center leg of the core unit to pass through the second through-hole and a plurality of second conductive patterns forming at least one turn around the second through-hole,</claim-text>
<claim-text>wherein the second conductive pattern substrate is disposed in at least one of a region above the first conductive pattern substrate or a region below the first conductive pattern substrate.</claim-text></claim-text></claim-text></claim>
<claim id="c-en-0002" num="0002">
<claim-text>The transformer according to claim 1, wherein the plurality of second conductive patterns comprises:<!-- EPO <DP n="31"> -->
<claim-text>a first metal plate pattern (NS1); and</claim-text>
<claim-text>a plurality of second metal plate patterns (NS2) disposed to be spaced apart from each other with the first metal plate pattern (NS1) interposed between the plurality of second metal plate patterns (NS2).</claim-text></claim-text></claim>
<claim id="c-en-0003" num="0003">
<claim-text>The transformer according to claim 2, wherein the first metal plate pattern (NS1) and the second metal plate patterns (NS2) have different areas.</claim-text></claim>
<claim id="c-en-0004" num="0004">
<claim-text>The transformer according to claim 2, wherein the plurality of second metal plate patterns (NS2) comprises:
<claim-text>a 2-1<sup>st</sup> metal plate pattern (NS2-1) disposed between the first metal plate pattern (NS1) and the second through-hole; and</claim-text>
<claim-text>a 2-2<sup>nd</sup> metal plate pattern (NS2-2) disposed to be spaced apart from the 2-1<sup>st</sup> metal plate pattern (NS2-1).</claim-text></claim-text></claim>
<claim id="c-en-0005" num="0005">
<claim-text>The transformer according to claim 4, wherein the 2-1<sup>st</sup> metal plate pattern (NS2-1) and the 2-2<sup>nd</sup> metal plate pattern (NS2-2) are electrically connected to each other.</claim-text></claim>
<claim id="c-en-0006" num="0006">
<claim-text>The transformer according to claim 5, further comprising a conductive line disposed on the second conductive pattern substrate, the conductive line being configured to<!-- EPO <DP n="32"> --> electrically connect the 2-1<sup>st</sup> metal plate pattern and the 2-2<sup>nd</sup> metal plate pattern to each other.</claim-text></claim>
<claim id="c-en-0007" num="0007">
<claim-text>The transformer according to claim 5, wherein the first conductive pattern substrate comprises a first connection pattern (CP1) formed adjacent to the first conductive pattern, and the first connection pattern (CP1) comprises a first via hole and a second via hole.</claim-text></claim>
<claim id="c-en-0008" num="0008">
<claim-text>The transformer according to claim 7, wherein each of the plurality of second metal plate patterns (NS2) comprises a via hole, and<br/>
wherein the via hole in the 2-1<sup>st</sup> metal plate pattern (NS2-1) is electrically connected to the first via hole, and the via hole in the 2-2<sup>nd</sup> metal plate pattern (NS2-2) is electrically connected to the second via hole.</claim-text></claim>
<claim id="c-en-0009" num="0009">
<claim-text>The transformer according to claim 8, wherein the first conductive pattern substrate comprises:
<claim-text>a first upper substrate comprising a first wire pattern having a center tap formed at one side of the first wire pattern; and</claim-text>
<claim-text>a first lower substrate disposed below the first upper substrate, the first lower substrate comprising a second wire pattern formed symmetrically to the first wire pattern.</claim-text><!-- EPO <DP n="33"> --></claim-text></claim>
<claim id="c-en-0010" num="0010">
<claim-text>The transformer according to claim 9, wherein the second conductive pattern substrate comprises:
<claim-text>a second upper substrate disposed above the first conductive pattern substrate; and</claim-text>
<claim-text>a second lower substrate disposed below the first conductive pattern substrate, the second lower substrate comprising a plurality of second conductive patterns.</claim-text></claim-text></claim>
</claims>
<drawings id="draw" lang="en"><!-- EPO <DP n="34"> -->
<figure id="f0001" num="1,2"><img id="if0001" file="imgf0001.png" wi="164" he="218" img-content="drawing" img-format="png"/></figure><!-- EPO <DP n="35"> -->
<figure id="f0002" num="3"><img id="if0002" file="imgf0002.png" wi="145" he="227" img-content="drawing" img-format="png"/></figure><!-- EPO <DP n="36"> -->
<figure id="f0003" num="4,5"><img id="if0003" file="imgf0003.png" wi="163" he="228" img-content="drawing" img-format="png"/></figure><!-- EPO <DP n="37"> -->
<figure id="f0004" num="6,7"><img id="if0004" file="imgf0004.png" wi="163" he="228" img-content="drawing" img-format="png"/></figure><!-- EPO <DP n="38"> -->
<figure id="f0005" num="8,9"><img id="if0005" file="imgf0005.png" wi="161" he="215" img-content="drawing" img-format="png"/></figure><!-- EPO <DP n="39"> -->
<figure id="f0006" num="10,11"><img id="if0006" file="imgf0006.png" wi="141" he="226" img-content="drawing" img-format="png"/></figure><!-- EPO <DP n="40"> -->
<figure id="f0007" num="12a,12b"><img id="if0007" file="imgf0007.png" wi="165" he="226" img-content="drawing" img-format="png"/></figure>
</drawings>
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