(19)
(11) EP 4 824 632 A1

(12)

(43) Date of publication:
21.10.2026 Bulletin 2026/43

(21) Application number: 24905040.2

(22) Date of filing: 13.12.2024
(51) International Patent Classification (IPC): 
G05F 1/14(2006.01)
G06F 7/38(2006.01)
G06F 9/38(2018.01)
 G06F 1/3206(2019.01)
G06F 9/32(2018.01)
(52) Cooperative Patent Classification (CPC):
G06F 1/26
(86) International application number:
PCT/US2024/060227
(87) International publication number:
WO 2025/129134 (19.06.2025 Gazette 2025/25)
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC ME MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA
Designated Validation States:
GE KH MA MD TN

(30) Priority: 14.12.2023 US 202363610347 P
17.10.2024 US 202418919345

(71) Applicant: POWERLATTICE TECHNOLOGIES INC.
Camas, WA 98607 (US)

(72) Inventors:
  • ZOU, Peng
    Camas, WA 98607 (US)
  • REN, Gang
    Camas, WA 98607 (US)
  • DERMAL, Sujith
    Camas, WA 98607 (US)

(74) Representative: Mewburn Ellis LLP 
Aurora Building Counterslip
Bristol BS1 6BX
Bristol BS1 6BX (GB)

   


(54) POWER MANAGEMENT TECHNIQUES USING LOCATION-MAPPED CHIPLET CONFIGURATION