(19)
(11) EP 4 824 647 A1

(12)

(43) Date of publication:
21.10.2026 Bulletin 2026/43

(21) Application number: 24905036.0

(22) Date of filing: 13.12.2024
(51) International Patent Classification (IPC): 
G06F 3/06(2006.01)
G01K 1/02(2021.01)
(52) Cooperative Patent Classification (CPC):
G11C 29/12005; G11C 29/028
(86) International application number:
PCT/US2024/060222
(87) International publication number:
WO 2025/129129 (19.06.2025 Gazette 2025/25)
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC ME MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA
Designated Validation States:
GE KH MA MD TN

(30) Priority: 14.12.2023 US 202363610300 P
03.12.2024 US 202418967199

(71) Applicant: Micron Technology, Inc.
Boise, ID 83716 (US)

(72) Inventors:
  • LANG, Murong
    San Jose, California 95129 (US)
  • XU, Zhongguang
    San Jose, California 95133 (US)
  • CHANG, Li-Te
    San Jose, California 95117 (US)

(74) Representative: Marks & Clerk LLP 
15 Fetter Lane
London EC4A 1BW
London EC4A 1BW (GB)

   


(54) DIE-LEVEL BLOCK FAMILY ERROR AVOIDANCE