(19)
(11) EP 4 824 667 A2

(12)

(88) Date of publication A3:
22.05.2025

(43) Date of publication:
21.10.2026 Bulletin 2026/43

(21) Application number: 24801408.6

(22) Date of filing: 17.10.2024
(51) International Patent Classification (IPC): 
G06F 11/20(2006.01)
(52) Cooperative Patent Classification (CPC):
G06F 11/2033; G06F 11/2035; G06F 11/2048
(86) International application number:
PCT/US2024/051799
(87) International publication number:
WO 2025/085649 (24.04.2025 Gazette 2025/17)
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC ME MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA
Designated Validation States:
GE KH MA MD TN

(30) Priority: 20.10.2023 US 202363545153 P
28.12.2023 US 202318399469

(71) Applicant: Stratus Technologies Ireland Limited
Dublin 1 (IE)

(72) Inventors:
  • EGAN, Michael
    Groton, Massachusetts 01450 (US)
  • BROWN, Beverly
    Westford, Massachusetts 01886 (US)
  • CAO, Lei
    Westford, Massachusetts 01886 (US)
  • HAID, Steven
    Bolton, Massachusetts 01740 (US)
  • HORVATH, Charles
    Jamaica Plain, Massachusetts 02130 (US)
  • MACLEOD, John
    Cambridge, Massachusetts 02140 (US)

(74) Representative: Purdylucey Intellectual Property 
23 Ely Place
Dublin 2 D02 N285
Dublin 2 D02 N285 (IE)

   


(54) COST REDUCED HIGH RELIABILITY FAULT TOLERANT COMPUTER ARCHITECTURE