(19)
(11) EP 4 824 875 A1

(12)

(43) Date of publication:
21.10.2026 Bulletin 2026/43

(21) Application number: 24841338.7

(22) Date of filing: 13.12.2024
(51) International Patent Classification (IPC): 
H01L 23/522(2006.01)
H01L 23/00(2006.01)
(52) Cooperative Patent Classification (CPC):
H10D 1/40; H10W 20/498; H10W 72/90; H10W 72/50; H10W 72/59
(86) International application number:
PCT/US2024/059938
(87) International publication number:
WO 2025/128932 (19.06.2025 Gazette 2025/25)
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC ME MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA
Designated Validation States:
GE KH MA MD TN

(30) Priority: 13.12.2023 US 202363609410 P
30.04.2024 US 202418651018

(71) Applicant: Texas Instruments Incorporated
Dallas, TX 75265-5474 (US)

(72) Inventors:
  • WEST, Jeffrey A.
    Dallas, TX 75243 (US)
  • WILLIAMS, Byron Lovell
    Dallas, TX 75243 (US)
  • STEWART, Elizabeth
    Dallas, TX 75243 (US)
  • TAKEI, Yoshihiro
    Miho, Ibaraki, 300-0496 (JP)
  • INOUE, Hiroyuki
    Miho, Ibaraki, 300-0496 (JP)

(74) Representative: Zeller, Andreas 
Texas Instruments Deutschland GmbH EMEA Patent Department Haggertystraße 1
85356 Freising
85356 Freising (DE)

   


(54) FABRICATION METHOD FOR FORMING HIGH VOLTAGE RESISTOR NETWORKS OVER SILICON SUBSTRATES FOR USE WITHIN MULTICHIP MODULE ASSEMBLIES