PRECODER DESIGN FOR MINIMIZING THE IMPACT OF HYBRID TIME AND FREQUENCY-DOMAIN CYCLIC SHIFT-CODED PORT VIRTUALIZATION ON COMMUNICATION PERFORMANCE - Patent 4824963

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EP 4 824 963 A1

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(43)	Date of publication:
	21.10.2026 Bulletin 2026/43

(21)	Application number: 24902544.6

(22)	Date of filing: 26.11.2024

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International Patent Classification (IPC):

H04B 7/06^(2006.01)

(52)	Cooperative Patent Classification (CPC):
	H04B 7/0456; H04B 7/0617

(86)	International application number:
	PCT/CN2024/134401

(87)	International publication number:
	WO 2025/124122 (19.06.2025 Gazette 2025/25)

(84)	Designated Contracting States:
	AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC ME MK MT NL NO PL PT RO RS SE SI SK SM TR
	Designated Extension States:
	BA
	Designated Validation States:
	GE KH MA MD TN

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Priority:

12.12.2023 US 202363608893 P

(71)	Applicant: MediaTek Inc.
	Hsinchu City 30078, Taiwan (TW)

(72)	Inventors:
	REN, Jiaying San Jose California 95134 (US) TSAI, Shiauhe Shawn San Jose California 95134 (US)

(74)	Representative: Haseltine Lake Kempner LLP
	Cheapside House 138 Cheapside London EC2V 6BJ London EC2V 6BJ (GB)

(54)	PRECODER DESIGN FOR MINIMIZING THE IMPACT OF HYBRID TIME AND FREQUENCY-DOMAIN CYCLIC SHIFT-CODED PORT VIRTUALIZATION ON COMMUNICATION PERFORMANCE