Pulse generator circuit

Abstract

 A pulse generator circuit includes first and second capacitors (TR⁷, TR⁴), first and second switches (TR⁹, TR⁶) connected in parallel with each other, an inverter circuit (rl, TR1) for inverting an input signal, first switch control circuit (TR³, TR⁶, r⁵, r⁵) for charging the first capacitor (TR') in response to a high level input signal, discharging the first capacitor (TR') with a predetermined time constant in response to a low level input signal, and respectively setting the first switch (TR') to a conductive or nonconductive state in response to a voltage across the first capacitor (TR') whose level is higher or lower than the predetermined voltage level, and second switch control circuit (TR³, TR⁵, r², r') for charging the second capacitor (TR⁴) in response to a high level output signal (from the inverter circuit (r, TR1), discharging the second capacitor (TR⁴) at a predetermined time constant in response to a low level output signal, and respectively setting the second switch (TR⁶) to a conductive or nonconductive state in response to a voltage across the second capacitor (TR⁴) whose level is higher or lower than a predetermined voltage level.

Description

[0001] The present invention relates to a pulse generator circuit for generating a pulse signal capable of being used as a set signal and a reset signal to be supplied, for example, to a flip-flop circuit.

[0002] In a semiconductor integrated circuit device, a pulse generator circuit for generating a set signal and a reset signal for a RS flip-flop is generally composed as shown in Fig. 1. This pulse generator circuit has capacitors Cl and C2 respectively coupled between the input/output pins 2A and 2B as well as 2C and 2D of the semiconductor integrated circuit device, and a charge/discharge circuit formed in the semiconductor integrated circuit device for charging/discharging these capacitors Cl and C2. This charge/discharge circuit charges these capacitors Cl and C2, and then discharges the capacitors C1 and C2 at a predetermined timing, thereby generating pulses.

[0003] However, it is necessary to externally attach capacitors Cl and C2 having relatively large capacitances so as to compose a pulse generator circuit shown in Fig. 1, thereby complicating the fabricating steps of this pulse generator and increasing the cost. As a semiconductor integrated circuit is highly integrated, the number of input/output pins has a tendency to increase, and it is desired to reduce the number of the input/output pins exclusively for the pulse generator. If the capacitors Cl and C2 are formed in the semiconductor integrated circuit, it is not necessary to provide the input/output pins exclusively for the pulse generator. However, since these capacitors Cl and C2 have relatively large capacitances, a considerably large pattern area is needed when the capacitors Cl and C2 are formed in the semiconductor integrated circuit, resulting in the disturbance of the high integration.

[0004] It is an object of the present invention to provide a pulse generator circuit capable of being highly integrated without using externally attached capacitors.

[0005] In order to achieve the above object, there is provided according to the present invention a pulse generator circuit comprising first and second switching circuits coupled in parallel with one another, a signal level converter circuit for shifting the level of an input signal between the first level and the second level; first and second capacitors; a first switch control circuit for charging the first capacitor in response to the input signal of the first level, discharging the first capacitor in response to the input signal of the second level at a predetermined time constant, and setting the first switching circuit to conductive and nonconductive states respectively when the voltage across the first capacitor is higher and lower than a predetermined level; and a second switch control circuit for charging the second capacitor in response to the output signal of the first level from the signal level converter circuit, discharging the second capacitor in response to the output signal of the second level at a predetermined time constant, and setting the second switching circuit to conduotivc and nonconductive states respectively when the voltage across the second capacitor is higher and lower than a predetermined level.

[0006] Since the change of the switching position of the first or second switching circuit to the conductive state is delayed by the discharging characteristic of the first or second capacitor when the input signal is changed from the first level to the second level or vice versa to generate the pulse in the present invention, it is not necessary to use the capacitors with a large capacitance as the first and second capacitors, thereby improving the integration.

[0007] This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:

Fig. 1 is a schematic view of a semiconductor integrated circuit having a conventional pulse generator circuit;

Fig. 2 is a circuit diagram of α- pulse generator circuit according to an embodiment of the present invention;

Figs. 3A to 3F are signal waveform diagrams for describing the operation of the pulse generator circuit shown in Fig. 2;

Fig. 4 is a circuit diagram of a pulse generator circuit in which capacitors are added to the circuit shown in Fig. 2; and

Fig. 5 is a circuit diagram of a pulse generator circuit using MOS transistors instead of bipolar transistors in Fig. 2.

Fig. 2 shows a pulse generator circuit according to an embodiment of the present invention. This pulse generator circuit has a waveform shaper circuit 10 for shaping the waveform of an input signal supplied to an input terminal VI, and has transistors TR1 and TR2 which receive at the bases the first and second output voltages from the waveform shaper circuit 10.

[0008] This waveform shaper 10 has resistors Rl and R2 coupled in series between the input terminal VI and the ground, a transistor TRO connected at the base to the junction between the resistors Rl and R2, connected at the collector through a load resistor r0 to a power source terminal VC and grounded at the emitter, and a resistor R3 connected between the collector of the transistor TRO and the base of the transistor TR1. Further, the collector of this transistor TRO is connected to the base of the transistor TR2.

[0009] The collector of the transistor TR1 is connected through a load resistor rl to the power source terminal VC, connected to the base of a transistor TR3, and the emitter is grounded. The collector of the transistor TR3 is connected through a load resistor r2 to the power source terminal VC, and the emitter is connected to the base of a transistor TR5 and grounded through the collector-emitter path of a transistor TR4. The collector of the transistor TR5 is connected through a load resistor r3 to the power source terminal and connected to the base of a transistor TR6, and the emitter is grounded. The collector of the transistor TR6 is connected through a load resistor r4 to the power source terminal, and the emitter is grounded.

[0010] The collector of the transistor TR2 is connected through a load resistor r5 to the pOwer source terminal VC, and the emitter is connected to the base of a transistor TR8 and grounded through the collector-emitter path of a transistor TR7. The collector of this transistor TR8 is connected through a load resistor r6 to the power source terminal VC and connected to the base of a transistor TR9, and the emitter is grounded. The emitter-collector path of the transistor TR9 is connected in parallel with the emitter-collector path of the transistor TR6. The transistors TR1 to TR9 shown in Fig. 2 are all npn type.

[0011] An operation of the pulse generator circuit shown in Fig. 2 will be describcd with reference to the signal waveforms shown in Figs. 3A to 3F.

[0012] As shown in Fig. 3A, when an input signal ϕIN to be applied to the input terminal VI becomes high at a time t0, the transistor TRO is rendered conductive, and the collector voltage of the transistor TRO becomes low at a time tl which is slightly delayed from the rise of the input signal φ IN shown in Fig. 3B. Thus, the transistors TR1 and TR2 become nonconductive, and the collector voltage of the transistor TR1 becomes high at a time t2, with a slight delay time from the time tl as shown in Fig. 3C. As a result, the transistors TR3 and TR5 are sequentially made conductive, and the collector voltage of the transistor TR5 becomes low after the time required to conduct these transistors TR3 and TR5 has elapsed from the time t2, i.e., at a time t3 as shown in Fig. 3D. Thus, the transistor TR6 becomes nonconductive, and the output signal φ OUT rises to a high level at a time t4, as shown in Fig. 3E. In this case, the capacitor between the collector and the base of the transistor TR4 is charged through the load resistor r2 and the transistor TR3.

[0013] On the other hand, the transistors TR2 and TR8 are in a conductive state before the time tl, and the capacitor between the collector and the base of the transistor TR7 is charged through the load resistor r5 and the transistor TR2. When the collector voltage of the transistor TRO becomes low at the time t0, the transistor TR2 becomes nonconductive at the time tl. However, in this case, the transistor TR8 is held in the conductive state for a predetermined period of time by the charging voltage of the capacitor between the collector and the base of the transistor TR7 and gradually comes to be in a nonconductive state after the predetermined time has elapsed from the time tl. When this transistor TR8 gradually becomes nonconductive, the collector voltage of the transistor TR8 gradually becomes high as shown in Fig. 3F. When the collector voltage of the transistor TR8 reaches a predetermined level VTl, the transistor TR9 is made conductive, and the output signal φ OUT becomes low.

[0014] Then, assuming that the input signal ϕIN becomes low at a time t6, as shown in Fig. 3A, the transistor TRO becomes nonconductive, and the collector voltage of the transistor TRO becomes high at a time t7, as shown in Fig. 3B. Thus, the transistors TR1, TR2 and TR8 are conducted in the same manner as described above, and the collector voltage of the transistor TR1 becomes a low level voltage at a time t8, as shown in Fig. 3C. Therefore, the transistor TR3 becomes nonconductive. In this case, the transistor TR5 is maintained in the conductive state by the charging voltage of the capacitor between the base and the collector of the transistor TR4, thereby maintaining the transistor TR6 in the nonconductive state. Since the transistor TR8 is made conductive, the transistor TR9 becomes nonconductive, and the collector voltage of the transistor TR9 becomes low at a time t8, as shown in Fig. 3F, and the output signal ¢OUT becomes high at a time t9, as shown in Fig. 3E. Subsequently, the charging voltage of the capacitor between the collector and the base of the transistor TR4 gradually decreases, and when the charging voltage of the capacitor between the collector and the base of the transistor TR4 becomes a voltage lower than a predetermined value, the transistor TR5 gradually becomes nonconductive, and the collector voltage of the transistor TR5 gradually becomes high. When the collector voltage of the transistor TR5 becomes higher than a predetermined level VT2, the transistor TR6 is made conductive. Consequently, the output signal φ OUT becomes low.

[0015] In this manner, when the input signal _OIN alters from the low level to the high level, the transistor TR8 is shifted from the conductive state to the nonconductive state with a predetermined delay time by the charging characteristic of the capacitor between the base and the collector of the transistor TR7, thereby generating a leading pulse. When the input signal φ IN alters from the high level to the low level, the transistor TR5 is shifted from the conduotive state to the nonconductive state in a predetermined delay time by the charging characteristic of the capacitor between the base and the collector of the transistor TR4, thereby generating a trailing pulse.

[0016] _'As described above, in the circuit shown in Fig. 2, the output signal ϕOUT can be generated in response to the rise and fall of the input signal φ IN without using the capacitor of large capacitance.

[0017] Fig. 4 shows a pulse generator circuit according to another embodiment of the present invention. This pulse generator circuit is composed substantially in the same manner as the pulse generator circuit shown in Fig. 2 except-that capacitors CX and CY are respectively coupled between the bases and the collectors of the transistors TR5 and TR8. The length of time when the transistors TR5 and TR8 are shifted from the conductive state to the nonconductive state can be arbitrarily set by suitably setting the capacitances of the capacitors CX and CY. In this case, the capacitances of the capacitors CX and CY are not necessarily required to be excessively large, but the capacitors CX and CY can be formed in a small occupying area and do not adversely influence the integration of the embodiment of this pulse generator circuit.

[0018] Fig. 5 shows a pulse generator circuit according to still another embodiment of the present invention. This pulse generator circuit is composed substantially in the same manner as the pulse generator circuit shown in Fig. 2 except that MOS transistors TR10 to TR19 are respectively employed instead of the transistors TRO to TR9 in Fig. 2. Similar advantages to those in the generator circuit in Fig. 2 can be achieved even in the embodiment of this pulse generator circuit.

Claims

1. A pulse generator circuit for generating a pulse signal in response to an input signal having first and second levels, characterized by comprising inverting circuit (rl, TR1; TR11) for inverting the input signal, load means (r4), first and second switching means (TR6, TR9; TR16, TR16) connected at one terminal thereof to a first power source terminal through said load means (r4) and at the other terminal thereof to a second power source terminal, first and second capacitive means (TR4, TR7; TR14, TR17), first switch control circuit (TR2, TR8; TR12, TR18) for charging said first capacitive means (TR7; TR17) in response to the input signal of said first level, discharging said first capacitive means (TR7; TR17) in response to the input level of second level with predetermined time constant, and setting said first switching means (TR9, TR19) to conductive and nonconductive states respectively when the voltage across said first capacitive means (TR7; TR17) is higher and lower than a predetermined level, and second switch control circuit (TR3, TR5; TR13, TR15) for charging said second capacitive means (TR4; TR14) in response to the output signal of the first level from said inverting circuit (rl, TR1; TR11), discharging said second capacitive means (TR4; TR14) with a predetermined time constant in response to the output signal of second level, and setting said second switching means (TR6; TR16) to conductive and nonconductive states respectively when the voltage across said second capacitive means (TR4; TR14) is higher and lower than a predetermined level.

2. A pulse generator circuit according to claim 1, characterized in that said first switch control circuit comprises a first switch circuit (TR2) connected between said first power source terminal and first capacitive means (TR7) and respectively set to conductive and nonconductive states in response to input signals of said first and second levels, and a first transistor (TR8) connected at the base and emitter thereof respectively to both terminals of said first capacitive means (TR7) and connected at the collector thereof to said first switching means (TR9) and first power source terminal.

.3. A pulse generator circuit according to claim 1, characterized in that said first capacitive means is formed of a second transistor (TR7) connected at the collector thereof to the base of said first transistor (TR8) and connected at the base and emitter thereof to the emitter of said first transistor (TR8).

4. A pulse generator circuit according to claim 2 or 3, characterized in that said first switch circuit (TR2) is formed of a transistor connected at the emitter thereof to said first capacitive means (TR7) and connected at the collector thereof to said first power source terminal.

5. A pulse generator circuit according to claim 3, characterized in that said second switch control circuit comprises a second switch circuit (TR3) connected between said first power source terminal and second capacitive means (TR4) and respectively set to conductive and nonconductive states in response to the output signals of first and second levels from said inverter circuit (10), and a third transistor (TR5) connected at the base and emitter thereof to both terminals of said second capacitive means (TR4) and connected at the collector thereof to said second switching means (TR6) and first power source terminal.

6. A pulse generator circuit according to claim 5, characterized by further comprising a capacitor (CY) connected between the base and collector of said first transistor (TR8), and a capacitor (CX) connected between the base and collector of said third transistor (TR5).

7. A pulse generator circuit according to claim 1, characterized in that said second switch control circuit comprises a switch circuit (TR3) connected between said first power source terminal and second capacitive means (TR4) and respectively set to conductive and nonconductive states in response to the output signals of first and second levels from said inverter circuit (10), and a first transistor (TR5) - connected at the base and emitter thereof to both terminals of said second capacitive means (TR4) and connected at the collector thereof to said second switching means (TR6) and first power source terminal.

8. A pulse generator circuit according to claim 7, characterized in that said second capacitive means is formed of a second transistor (TR4) connected at the collector thereof to the base of said first transistor (TR5) and connected at the base and emitter thereof to the emitter of said first transistor (TR5).

9. A pulse generator circuit according to claim I, characterized in that said first capacitive means is formed of a MOS capacitor (TR17), and said first switch control circuit comprises a first MOS transistor (TR12) connected between said first power source terminal and first capacitive means (TR17) and respectively set to conductive and nonconductive states in response to the input signals of said first and second levels and a second MOS transistor (TR18) connected at one terminal thereof to said second power source terminal and at the other terminal thereof to said first switching means (TR19) and first power source terminal.

10. A pulse generator circuit according to claim 9, characterized in that said second capacitive means is formed of a MOS capacitor (TR14), and said second switch control circuit comprises a third MOS transistor (TR13) connected between said first power source terminal and second capacitive means (TR14) and respectively set to conductive and nonconductive states in response to the output signals of first and second levels from said inverter circuit (rl, TR11), and a fourth MOS transistor (TR15) connected at one terminal thereof to said second power source terminal and at the other terminal thereof to said second switching means (TR16) and first power source terminal.

Drawing