DWELL CIRCUITRY FOR AN INGNITION CONTROL SYSTEM

Description

[0001] The present invention relates generally to the field of digital signal processing circuitry, and more particularly to the field of digital electronic dwell circuits used in ignition control systems which control spark and dwell occurrence.

[0002] In internal combustion engines the time occurrence at which a spark is produced to ignite a fuel and air mixture in a cylinder is a primary operational consideration. Similarly, producing an appropriate excitation signal (dwell) for an ignition coil immediately prior to the coil producing spark ignition is also a major design consideration. Mechanical spark control ignition systems have been found not to be reliable over long periods of time thus necessitating frequent readjustment of the mechanical controls. Thus electronic dwell and spark control ignition systems having greater reliability have been developed.

[0003] Electronic dwell circuits for ignition control systems are known and U.S.-A-3,908,616 and 4,018,202 illustrate digital circuits for determining a dwell control signal. While the circuits shown in these patents evidently produce accurate digital dwell control signals, generally they are not economically adaptable to operate in conjunction with digital spark timing circuits in which the spark timing is to be a function of engine speed and other additional engine variables. This is because generally prior art dwell circuits utilize circuitry which is separate from the spark timing calculation circuitry. Thus the dwell calculation is accomplished without the utilization of the majority of the spark calculation circuitry, thus increasing the cost of the total ignition control system.

[0004] Generally, prior art dwell circuits such as U.S.-A-4,018,202 utilize a complex and costly cam structure having an extremely large number of individual teeth projections in order to produce a series of high resolution crankshaft position pulses, typically one pulse being produced for every one degree of crankshaft rotation. The construction of these cams is costly and their utilization would tend to inhibit utilization of the same cam to produce other crankshaft position pulses which would occur at other than one degree increments of crankshaft rotation. Of course this deficiency can be overcome by utilizing additional cams and additional crankshaft position sensors, but then the cost of the ignition control system would be increased. While the one degree pulses can be electronically realized by dividing up large angular crankshaft pulses, this would also add to the cost of an ignition control system.

[0005] The one degree crankshaft position pulses produced by the prior art dwell circuits represent speed dependent crankshaft position pulses and enable the prior art circuits to readily calculate ignition dwell as a fixed number of degrees of crankshaft rotation. However these circuits have problems in realizing a constant dwell time, rather than constant dwell angle, which is desired for some engine operative conditions. Also prior dwell circuits such as U.S.-A-4,018,202 require complex feedback circuits having marginal stability.

[0006] Some dwell circuits such as those in U.S.-A--3,908,616 utilize speed independent pulses in order to calculate ignition dwell. While these circuits have eliminated the need for a multi-tooth crankshaft cam or its electronic equivalent for producing high resolution crankshaft position pulses, the disclosed circuit designs cannot produce large dwell angles which are required at high engine speeds. In addition the dwell circuit in US-A-3,908,616 contemplates adjusting count thresholds in order to adjust the dwell occurrence and/or contemplates adjusting the rate at which pulse counting takes place. In order to implement either of these two functions, relatively complex and costly control structures are required.

[0007] Typically, digital signal processing circuits which intend to implement the function of producing a pulse occurrence a predetermined time prior to the known occurrence of periodic signal pulse transitions having a variable occurrence rate have utilized circuit configurations corresponding to those shown in U.S.-A-3,908,616 or 4,018,202. Therefore they have suffered from the same deficiencies described above.

[0008] A known digital circuitry for receiving a signal comprising periodic pulse transitions and producing indicative signals at times prior to the occurrence of the periodic pulse transitions is summarised in the precharacterizing portion of Claim 1 and is known from US-A-4052967.

[0009] In US-A-4052967 the dwell circuitry includes means to develop a running count by counting oscillator pulses between first and second time occurrences corresponding to the ignition initiating signal. The count occurring at the second time occurrence, which is the maximum running count, is stored and subsequently has subtracted therefrom a predetermined number of counts to obtain a resultant subtracted count. Thereafter, the resultant subtracted count is compared with the current running count and upon the occurrence of an equality an indicating signal is produced which initiates dwell.

[0010] It is an object of the present invention to provide an improved and simplified digital signal processing circuit which overcomes the aforementioned deficiencies of the prior art and initiates a signal at a variable rate signal transitions. It is also an object of the present invention to provide an improved digital dwell circuit for an ignition control system which overcomes the problems of the prior art.

[0011] The present invention is summarized in the characterizing portion of Claim 1. The present invention overcomes the problems of the prior art by having the first and second time occurrences directly related to the occurrence of the first and second pulse transitions of said periodic signal. In addition, the provision of a means for counting down the resultant subtracted count avoids the necessity to use comparators in adddition to which the incrementing of the count is at a rate independent of the said variable repetition rate after the said second time occurrence.

[0012] It should be noted that the dwell circuit of the present invention is contemplated as being utilized in an ignition dwell and spark control system in which the circuitry which produced the running count also is utilized to determine spark occurrences. This double utilization of the running count by both the dwell and spark timing circuits of an ignition control system reduces the cost of the ignition control system.

[0013] For a more complete understanding of the invention, reference should be made to the drawings, in which:

Figure 1 comprising drawings 1A, 1B and 1C, is a combination block and schematic diagram illustrating an engine ignition control system for an internal combustion engine;

Figure 2 is a schematic diagram illustrating a typical configuration for a pulse width modulator circuit shown in Figure 1;

Figure 3 is a schematic diagram illustrating typical circuit configurations for several of the block components shown in Figure 1;

Figure 4 is a schematic diagram illustrating a typical configuration for a select decoder illustrated in Figure 1;

Figure 5 is a schematic diagram illustrating a typical configuration for a slow speed decoder shown in Figure 1;

Figure 6 is a schematic diagram illustrating a typical configuration for a spark logic circuit shown in Figure 1;

Figure 7 is a schematic diagram of a typical embodiment of the present invention for the dwell circuit shown in Figure 1;

Figure 8 is a graph which shows the desired spark timing versus engine speed characteristic provided by the circuit in Figure 1; and

Figures 9A through 9Q are a series of graphs which illustrate electrical signals and pulse count accumulations as functions of time for the system shown in Figure 1.

[0014] Figure 1 illustrates an electronic ignition control system 10 for a two cylinder internal combustion engine (not shown). Essentially the control system 10 receives sensor input signals and develops control signals that determine the spark timing and dwell (coil excitation time) for a distributorless inductive ignition system. The term "distributorless" contemplates the fact that no rotating mechanical distributor will be utilized, and that instead sparks will be created in each of the two cylinders simultaneously but at different times with respect to the compression cycle of each cylinder. In other words, when a spark is generated by cylinder 1 at the proper time of its compression cycle, a spark will also be generated in cylinder 2 but this spark will occur during the exhaust cycle of cylinder two and therefore will not result in igniting a fuel mixture. Distributorless ignition systems are known and do not form an essential part of the present invention.

[0015] The control system 10 illustrated in Figure 1 will now be described. For a better understanding of Figure 1, drawings 1A, 18 and 1C should be arranged with drawing 1 B located between drawings 1A and 1C.

[0016] The control system 10 includes a rotating cam 11 synchronously rotatable with a crankshaft of a two cylinder engine, the crankshaft being shown schematically as an axis of rotation 12. The cam 11 has a peripheral projection 13 spaced from the axis 12 and the cam 11 is contemplated as rotating in a clockwise direction.

[0017] An advance sensor 15 is contemplated as having a sensing probe 16 positioned at a fixed location with respect to the rotating cam 11, and a reference sensor 17 is contemplated as having a sensing probe 18 similarly positioned with the probes 16 and 18 being spaced apart by 35 degrees of angular rotation of the cam 11 (which corresponds to 35 degrees of engine crankshaft rotation). The probes 16 and 18 produce crankshaft angular position pulses as the projection 13 rotates by these probes with the produced position sensing pulses initially occurring in response to the passage of a leading edge 13a of the projection passing by the sensing probes and the position pulses terminating after a trailing edge 13b has passed by the probes 16 and 18. The advance sensors 15 and 17 receive input signals from their corresponding sensing probes and produce digital pulse outputs in correspondence thereto at output terminals 19 and 20, respectively.

[0018] It should be noted that the positioning of the sensing probes 16 and 18 with respect to the rotating cam 11 and its projection 13 is not totally arbitrary and that it is contemplated that the probe 16 is positioned such that it defines the maximum possible advance (earliest possible spark ignition occurrence for a cylinder compression cycle) for the ignition system 10 while the probe 18 defines the minimum possible advance (generally corresponding to top dead center of cylinder position which is generally termed zero or reference advance). Thus the positioning of the probes 16 and 18 define the earliest and latest possible occurrences of spark ignition, respectively, for the ignition control system 10. The significance of this will be demonstrated subsequently.

[0019] The advance and reference output terminals 19 and 20 are coupled as inputs to advance and reference buffers 21 and 22, respectively, which impedance isolate the sensors from subsequent circuitry and insure the production of precise, uniform magnitude corresponding digital pulses at the output terminals 23 and 24, respectively. Figures 9A and 98 illustrate the sensing pulses produced at the terminals 23 and 24, respectively, and illustrate that these pulses occur periodically at times t_A and t_R corresponding to the passage of the leading edge 13a past the sensing probes 16 and 18. The time occurrences t_A and t_R of the pulses at the terminals 23 and 24 are utilized by the ignition control system 10 to determine spark timing and dwell, and the manner in which this is accomplished will now be discussed with reference to the circuit schematics in Figures 1 through and the graphs in Figures 8 and 9A-Q. It should be noted the horizontal axis in Figures 9A-Q is time and that Figures 9A, 9B, 9D-9J and 9P and Q are drawn having the same time axis scale, while Figures 9C and 9K through 100 are drawn with a greatly expanded time scale.

[0020] The control system 10 includes a master clock oscillator 25 which produces clock timing pulses Cp at an output terminal 26 wherein the frequency of the clock oscillator is preferably 149.25 KHz. The clock pulses Cp are illustrated schematically in Figure 9C on a greatly expanded horizontal time scale and are continuously produced by the oscillator 25 regardless of the angular position of the crankshaft of the engine. A prescaler 27 is shown as being integral with the clock oscillator 25 and producing output signals C₁ through C₄ at the output terminals 28 through 31, respectively. The prescaler essentially comprises a series of counters which receive the clock signals Cp and produce related lower frequency signals by essentially counting and thereby frequency dividing down the oscillator signal pulses Cp. Such pre- scalers are very well known and thus the construction details of the prescaler 27 will not de discussed. The C₁ signal produced at the terminal 28 has an operative frequency of 1.16 KHz, C₂ has a frequency of 9.33 KHz, the frequency for C₃ is 49.75 KHz and the frequency of C₄ is 74.6 KHz. All of the signals Cp and C₁―C₄ have repetition rates independent of the speed of crankshaft rotation. The prescaler 27 has a reset terminal 32 which causes resetting of the counters internal to the prescaler 27. The signals developed by the clock oscillator 25 and prescaler 27 at the terminals 26 and 28 through 31 essentially determine the operation of the ignition control system 10 in conjunction with the pulses sensed by the advance and reference probes 16 and 18. The signals produced at the terminals 28 through 31 are essentially used in various counters included in the ignition control system 10 and therefore the provision for resetting the internal counters in the prescaler 27 via the reset terminal 32 is required to insure that the counters receiving their inputs in accordance with the signals at the terminals 28 through 31 will be synchronized with the advace sensor signal S₁ described below.

[0021] A pulse synchronizer 33 receives an advance signal input from the terminal 23 and the clock pulse signal Cp from the terminal 26. The pulse synchronizer produces a synchronized advance pulse S₁ at an output terminal 34. Essentially, the synchronizer 33 insures that a pulse S₁ is produced at the terminal 34 at a time t₁ which corresponds to the first clock pulse Cp that occurs after the time t_A. In this manner the signal S₁ (shown in Figure 9D) represents an advance pulse which is synchronized with the occurrence of the clock pulses Cp.

[0022] The pulse synchronizer 33 also receives an input at a terminal D from an output terminal 35 of an inhibit circuit 36. Essentially the inhibit circuit 36 produces a 4 millisecond delay pulse at the terminal 35 in response to the occurrence of the spark ignition and this delay or inhibit signal at the terminal 35 prevents the pulse synchronizer from producing an output at the terminal 34 for 4 milliseconds after the occurrence of spark ignition. The reason for this is to quiet the output of the synchronizer 33 such that additional sparks will not be initiated by the synchronizer 33 until at least 4 milliseconds has elapsed since the last spark occurrence.

[0023] A pulse synchronizer 37 is similar to the synchronizer 33 and receives inputs from the reference sensor terminal 24 and the clock pulse terminal 26 and produces a synchronized reference pulse signal S₂ at an output terminal 38. The synchronizer 37 merely insures that a reference signal S₂ has an initial time occurrence which precisely corresponds to the occurrence of one of the clock pulses Cp. Since it is contemplated that the frequency of occurrence of the clock pulse Cp is very high (higher than all other timing signals C₁―C₄), this synchronization results in substantially no loss in accuracy for the present system, due to delaying advance and reference timing by one clock pulse, but does insure that the reference pulse S₂, as well as the advance pulse S₁, will occur in synchronism with the clock pulse Cp. This insures synchronized timing for the control system 10. The reference signal S₂ is illustrated in Figure 9E as comprising periodic pulses which occur at the times t₂. It should be remembered that the duration of time between the occurrence of the advance pulses S₁ at t, and the reference pulses S₂ at the times t₂ corresponds to 35 degrees of engine crankshaft rotation. Of course the actual time duration between t₁ and t₂ will vary directly as a function of engine speed.

[0024] A delay circuit 39 receives the signal S₁ along with the clock pulses Cpand produces a delayed output signal SD at an output terminal 40. Essentially, the delay circuit 39 receives the synchronized.signal S₁, delays this signal by one full period of the clock pulse signal Cp and produces this delayed signal S₁D at the terminal 40. Figure 9F illustrates this delay advance signal S₁D which has a time occurrence at t₁ D that is one clock pulse period later than the time occurrence t₁. The reason for creating the delayed advance signal S₁D is that in many cases the control system 10 will transfer accumulated counts at the times t₁ in response to the pulses S₁, and subsequently the accumulated counts are to be reset. Obviously the transference and resetting cannot occur simultaneously, thus the present system provides for delaying the resetting until after transference.

[0025] The ignition control system 10 essentially utilizes a main up-counter 41 to linearly count up C₁ pulses occurring at the terminal 28 in between the occurrence of delayed advance signal pulses S₁D. This is accomplished by having the main up-counter 41 receive its counter input from the terminal 28 while its reset terminal is directly connected to the terminal 40. The counter 41 therefore periodically linearly accumulates a speed independent running count which has a maximum value directly related to engine speed since the counting occurs during the times t,D which occur every 360 degrees of crankshaft rotation.

[0026] Figure 9H illustrates a waveform representative of the linearly incremented running count of the counter 41. It should be noted that individual counting steps have not been illustrated in Figure 9H since these steps occur at the relatively high frequency of the signal C, produced by the prescaler 27. However, Figure 9N does illustrate the count in the main counter 41 on a very expanded horizontal time scale, and this figure clearly illustrates the incremental nature of the accumulated count in the counter 41.

[0027] The accumulated count of counter 41 is produced at 6 output terminals 42 through 47 with terminal 42 corresponding to the least significant bit and terminal 47 corresponding to the most significant bit. Thus the main up-counter 41 represents a 6 bit binary counter. Such counters are well known and readily available. It should be noted that while the electronic ignition control system 10 utilizes the maximum accumulated count obtained by the counter 41 as an indication of engine speed, the ignition system 10 also utilizes each incremental count produced by the counter 41 at its output terminals 43 through 47 as control signal inputs to spark time occurrence circuitry within the system 10, and these incremental counts are utilized to produce a desired non-linear spark occurrence versus engine speed characteristic. The manner in which this is accomplished will now be discussed.

[0028] Each of the output terminals 43 through 47 of the main up-counter 41 are coupled as inputs to a read only memory (ROM) device 48 which has 4 output terminals 49 through 52 which are coupled as control signal inputs to a rate multiplier device 53. The rate multiplier 53 receives a continuous stream of input clock pulses C₂ via a direct connection to the terminal 29 and produces a corresponding output pulse stream at an output terminal 54 in accordance with the control signals received from the terminals 49 through 52. The rate multiplier device 53 is set by the pulse S, which is received via a direct connection from the terminal 34, and this reinitiates the operation of the rate multiplier 53. The rate multiplier essentially functions as a controllable frequency divider which multiplies (actual divides) the frequency of the input pulse stream by predetermined integers which are determined by the control signals received from the ROM. Rate multipliers are well known and are readily available.

[0029] Essentially, the pulse stream produced at the output terminal 54 is subsequently accumulated in an accumulator means which develops a count related to the number of pulses produced at the terminal 54. The exact structure of the accumulator means which accomplishes this will be described subsequently. This total accumulated count, which occurs between the pulses S_i, is then subsequently utilized by the ignition control system 10 to determine the occurrence of spark ignition. The above described spark timing technique of utilizing a rate multiplier which is controlled by a read only memory circuit that receives incrementally controlled inputs related to engine speed (it should be remembered that in the present case the ROM inputs are the counts of the up-counter 41 which are related to engine speed) is essentially described in prior specification DE-A-2812325.

[0030] Essentially the ROM 48 functions as a look-up table device which produces different control signals at the terminals 49 through 52 that control the frequency multiplication (division) provided by the rate multiplier 53. The end result is that the output pulse count produced at the terminal 54 is a non-linear function of engine speed such that a desired spark ignition occurrence versus engine speed characteristic can be obtained. The accumulator means effectively integrates or accumulates the pulse count at the terminal 54 and determines, between S₁ pulses, a maximum pulse count non-linearly related to engine speed. This maximum pulse count is then utilized to determine spark ignition.

[0031] Issued U.S.-A-4,104,997 illustrates an analog system in which a desired non-linear spark occurrence versus engine speed characteristic is produced by controlling the rates of charging and discharging a capacitor. In the present system the ROM 48 and rate multiplier 53 digitally implement an equivalent function for controlling the rate of pulses produced at the terminal 54, and an accumulator means integrates these pulses to produce the desired result. Figure 8 illustrates the desired advance angle (spark timing occurrence) versus engine speed characteristic which is desired by issued U.S.-A-4,104,997 and which is a typical characteristic also desired by the present system. DE-A-2812325 explains how the slope changes of the characteristics shown in Figure 8 can be digitally implemented by use of a rate multiplier and ROM without having the ROM store every individual point of the composite characteristics shown in Figure 8. It should be noted that in Figure 8, the curve NV represents the desired spark occurrence characteristic for no vacuum being sensed by an ignition control system whereas the curve V represents the desired characteristic for a predetermined amount of vacuum being sensed by an engine control system.

[0032] The present system contemplates providing the read only memory 48 with an additional input signal at an input terminal 55 wherein this additional signal represents the output of a pulse width modulator circuit 56 having its output terminal 57 directly connected to the terminal 55. The pulse width modulator 56 receives an analog signal at an input terminal 58 wherein the magnitude of this analog signal is related to a predetermined engine condition, in the present case related to the magnitude of sensed engine vacuum pressure. The pulse width modulator 56 will then produce a periodic digital two state signal which has a duty cycle (ratio of one logic state to the other during one cycle period) which is related to the magnitude of this analog signal. By coupling this digital two state signal produced at the terminal 57 as an input to the read only memory, the result is that the control signals at the output terminals 49 through 52 of the ROM are now made a function of this analog signal and effectively the ROM control outputs will be switched between two different sets of outputs, one corresponding to a low digital signal at the terminal 55 and another corresponding to a high logic digital signal at the terminal 55. Since the percentage of time (duty cycle) of the logic states of the signal at the terminal 55 is controlled in response to the magnitude of the analog signal at the terminal 58, this results in having output control signals at the terminals 49 through 52 switched back and forth between two extreme values with the average of these control signals being related to the magnitude of the analog signal at the terminal 58. Since the control signals at the terminals 49 through 52 determine the rate multiplication of the rate multiplier 53, and since the output of the rate multiplier is effectively integrated by a following accumulator means, the effect of applying a pulse width modulation signal as an input at the terminal 55 of the ready only memory 48 results in providing a continuous interpolation capability between the two extreme control output produced at the terminals 49 through 52 in response to the terminal 55 having a high or low logic state.

[0033] For any one set of speed dependent control inputs received from the terminals 43 through 47 of the main counter 41, the ROM 48 need only store a maximum and minimum output corresponding to whether the signal at the terminal 55 is either high or low. In the present case these maximum and minimum outputs correspond to the sensed vacuum pressure being above or below a predetermined vacuum pressure. The actual outputs produced at the terminals 49 through 52 are then made to represent a value more directly indicative of the magnitude of the analog voltage at the terminal 58 by first producing a digital two stage signal whose duty cycle varies in accordance with the analog signal magnitude and then by applying this signal to the input terminal 55.

[0034] The improved result obtained by the present system should be contrasted with the prior art technique of providing a different digital output signal for each analog magnitude increment for which resolution of the output signal is desired. In other words, previously if you wanted a ready only memory to produce different output signals in response to three different magnitudes (for example) of an analog input signal, then three memory storage spaces within the read only memory would be required wherein three different memory address inputs would address any one of three different desired outputs. In the present system only two input addresses and two desired outputs are required, and by pulse width modulating a digital signal so that its duty cycle is related to an analog signal magnitude, the read only memory output will be switched back and forth between these two extreme outputs such that the average output of the read only memory will represent any output value in between these two extreme outputs which are stored in the read only memory. Thus the read only memory of the present system need only store two output limits in response to any desired engine condition and an average ROM output corresponding to any magnitude between these two output limits can be obtained merely by using a duty cycle pulse width modulated input signal to the read only memory. This permits saving an enormous amount of read only memory storage space while still enabling the output of the read only memory to have a high resolution correspondence with respect to the magnitude of the input analog signal. To obtain an equivalent resolution by any of the prior art references could not be digitally accomplished unless an extremely large read only memory capacity was utilized. The present system minimizes the read only memory capacity and therefore implements this function with a substantial cost savings.

[0035] The operation of the pulse width modulator and the accumulator means which follows the rate multiplier 53 will now be described in detail.

[0036] The present system contemplates an engine vacuum pressure sensor 59 supplying an analog signal to the input terminal 58 of the pulse width modulator 56. The analog signal magnitude is representative of the state of engine vacuum pressure. Terminals 42 through 44 of the main counter 41 are also received by the pulse width modulator 56 which produces an output at terminal 57.

[0037] Figure 2 illustrates typical embodiments for the vacuum sensor 59 and the pulse width modulator 56 both shown dashed in Figure 2. The vacuum sensor 59 is contemplated as comprising a two position vacuum sensing switch 60 with a wiper arm terminal coupled to ground and the wiper varying between a first terminal 61 when sensed engine vacuum pressure is below a predetermined threshold value and a second terminal 62 when the sensed vacuum pressure is above this predetermined value. The terminal 62 is coupled to a B+ terminal through a resistor 63 and is coupled to the terminal 58 through a resistor 64. A capacitor 65 is coupled from the terminal 58 to ground. In response to sensing an engine vacuum pressure change from below to above the predetermined threshold, the switch 60 will short the terminal 62 to ground resulting in slowly changing the voltage at the terminal 58 from a high voltage to a low voltage. Preferably this voltage change occurs at a relatively slow 0.5 second time constant. Thus the signal at the terminal 58 represents an analog signal which has a magnitude related to the sensed engine vacuum pressure.

[0038] While in the present embodiment an analog signal which varies between two voltage magnitudes which directly correspond to two discrete states of vacuum pressure is illustrated, the present system certainly contemplates other embodiments which provide an analog signal at the terminal 58 which is continuously and directly related to the instantaneous value of engine vacuum pressure rather than the opening or closing of a two position engine vacuum sensor switch.

[0039] The pulse width modulator circuit 56 comprises a DC level comparator 66 having a negative input terminal coupled to the input terminal 58 through a resistor 67. Limiting diodes 68 and 69 are also connected to the negative input terminal of the comparator 66 and essentially limit the signals received by the comparator to magnitudes either one diode drop above B+ or one diode drop below ground. The terminals 42 through 44 are received as inputs to a NAND gate 70 whose output is coupled through an inverter 71 to a control terminal 76 of an FET gate 72. An output terminal of the gate 72 is coupled to a positive input terminal 75 of the comparator 66 which is also coupled to B+ through a resistor 73 and to ground through a capacitor 74. The output of the comparator 66 is directly coupled to the output terminal 57 of the pulse width modulator 56.

[0040] Essentially the signals at the terminals 42 through 44 are converted by the NAND gate 70 into a relatively slow periodically occurring pulse signal which is used as the control signal for the FET gate 72. This control signal is illustrated in Figure 9K. In response to each periodic pulse produced at the control gate of the FET 72, the positive input terminal (terminal 75) of the comparator 66 is shorted to a positive reference voltage just above ground potential by the gate 72. After setting the terminal 75 to just above ground, the FET gate 72 is open circuited until the next occurrence of a control pulse at its control terminal 76. Figure 9K illustrates the control signals at the terminal 76 and Figure 9L illustrates the signal waveforms produced in response thereto at the positive input terminal 75 of the comparator 66. Superimposed on the waveform shown in Figure 9L is a high first dashed voltage level 77 corresponding to low vacuum pressure is being sensed by the sensor 59, a low second voltage level 78 corresponding to the low voltage eventually produced at the terminal 58 upon closure of the switch 60 in response to a high vacuum pressure being sensed, and an interim voltage level 79 corresponding to the voltage at the terminal 58 which would occur at some time after the closure of the switch 60 but before the attainment of the limit level 78. It should be noted that the waveforms in Figures 9K and 9L are all commenced at the times t₁, and that the horizontal time axes in Figures 9K through 90 are shown with greatly expanded time scales as compared with the other graphs in Figures 9A-9Q. The time scales for graphs 9K-9M are identical, but the time scales for graphs 9N and 90 are even more expanded.

[0041] Figure 9M shows the output signal of the comparator 66 produced in response to the signal shown in Figure 9L being created at the positive input terminal 75 while the negative terminal of the comparator 66 receives a transitional voltage corresponding to the dashed level 79 shown in Figure 9L. Figure 9M illustrates that the output of the comparator 66 is a digital two state logic signal in which the duty cycle of this signal varies in accordance with the magnitude of the analog signal produced at the terminal 58. For a no vacuum condition corresponding to the level 77 present at the negative input terminal of the comparator 66, the output of the comparator 66 would remain at zero, and for a voltage at the negative input terminal corresponding to the level 78, the output of the comparator 66 would always be high.

[0042] Figure 9M illustrates that for interim values of vacuum (in the case of a continuous analog sensor being used instead of a two position vacuum sensing switch) or in the case of a slowly changing signal representing changing from vacuum to non-vacuum and back again (when a two position vacuum sensing switch is used), an analog signal is produced at the terminal 58 which results in a varying duty cycle signal being produced as the output of the comparator 66. As was previously discussed, applying this varying duty cycle signal to the input of the ROM 48 allows the output of the ROM to vary, in a periodic stepwise manner, between two maximum limits and this produces an output whose average value will be directly related to the magnitude of the analog signal at the terminal 58.

[0043] In the present situation, it was found that rapidly switching from a vacuum spark advance determination to a no vacuum spark determination would disrupt the operation of the ignition control system 10. Thus it was necessary to slowly implement the change between vacuum and non-vacuum spark calculations by the system 10. In order to accomplish this, the output of the ROM 48 must be able to represent interim output values between the vacuum and no vacuum conditions corresponding to the levels 78 and 77, respectively. The present system accomplishes this desired result without any increase in the storage space required by the ROM 48.

[0044] As was previously mentioned, an accumulator means essentially follows the rate multiplier 53 and effectively converts the pulse count at the terminal 54 into an integrated or accumulated maximum count. It is this accumulation step that results in effectively averaging the different control signal outputs produced at the ROM output terminals 49 and 52 by use of the pulse width modulator 56 altering the duty cycle of the input ROM control signal at the terminal 55.

[0045] Before describing the accumulator means coupled to the rate multiplier output terminal 54, a better understanding of the present invention will be obtained by referring to Figures 9N and 90. Figure 9N represents the incremental count, incrementing at twice the frequency of the clock pulse signal C_i, commenced at the times ti D by the main up-counter 41 on the control terminals 43 through 47 coupled to the ROM 48. After the main counter 41 receives two C₁ pulses the count of the main counter, as recorded on the output terminals 43 through 47, is incremented one count. In Figure 9N the horizontal axis represents an expanded time scale whereas the vertical axis represents the stepped count stored by the terminals 43 through 47. Figure 90 represents maximum and minimum rates of increase SL, and SL₂ determined by the output terminals 49 through 52 of the read only memory 48. At a subsequent time t,, the count of the main counter is incremented by counting C₁ pulses such that the terminal 43 now indicates a new count as an input signal to the read only memory 48. Thus a different input control signal is now received by the read only memory 48 and the output terminals 49 through 52 of the ROM now are able to implement different rates of increase SL₃ and SL₄. The rates of increase SL,-SL₄ represent different fixed integers used by the rate multiplier for frequency division.

[0046] For each different count increment on lines 43-47 the ROM 48 can select either of two different rates of increase for the count processed by the rate multiplier 53 because for any main count received as an input by the ROM 48 from the counter 41, either a zero or one logic state can be produced by the pulse width modulator 56 at the input terminal 55. Figure 90 illustrates the different characteristics for rates of pulse count increase at terminal 54 that can be implemented by the rate multiplier 53 in accordance with the control input signals received by the read only memory 48 which supplies control inputs to the rate multiplier. By applying a pulse width modulation signal to the input terminal 55, the present system contemplates selectively switching between maximum rates of increase such as SL₁ and SL₃ and minimum rates of increase such as SL₂ and SL₄ during the times t₁D―T₁ and after t₁, respectively, to obtain a composite (average) rate of increase which can be anywhere within the limits defined by the maximum and minimum rates of increase.

[0047] It can be seen that controlling ROM and rate multiplier in accordance with pulse counts related to engine speed can result in determining break points for the composite spark timing advance versus engine speed characteristics illustrated in Figure 8. Issued U.S.-A-4,104,997 demonstrates how controlling the rate of increase of an effective integrator means can be utilized to accurately determine desired spark timing relationships as a function of engine speed. The present system combines these two techniques along with providing for pulse width modulation of an input to a read only memory in accordance with sensed engine vacuum pressure in order to minimize the ROM storage space required by an ignition spark timing control system responsive to engine speed and engine vacuum pressure.

[0048] From Figures 9N and 90, which are drawn with identical horizontal time scales, it would appear that for optimum interpolation between the maximum and minimum slopes, such as SL₁ and SL₂, a pulse width modulation frequency for the signal shown in Figure 9M as high as possible should be selected. In the preferred embodiment, this is not the case since the period of the signal in Figure 9M is equivalent to eight main counter increments (at the frequency of C₁) while the period of the signal in Figure 9N is equivalent to two main counter increments. This relationship was decided upon in order to permit the rate multiplier to pass enough of the divided down C₃ pulses to the output terminal 54 to obtain an adequate number of pulse counts at terminal 54 which represents any of the rates SL₁―SL₄.

[0049] The structure of the effective pulse count accumulator means connected to the output terminal 54 of the rate multiplier 53 will now be described.

[0050] The output of the rate multiplier 53 at the output terminal 54 is effectively coupled to an accumulator means which accumulates a count related to the total pulse count produced at the output terminal 54. This accumulator means essentially comprises a select decoder 80, a main advance up-down counter 81 and an auxiliary advance up counter 82. The rate multiplier output terminal 54 is coupled as an input to both the select decoder 80 and a counter terminal (>) of the auxiliary advance up counter 82. The auxiliary advance up counter 82 receives a reset signal by means of a direct connection to the terminal 34 at which the S₁ pulses are produced. The up counter 82 is a four bit binary counter and produces count outputs at terminals 83 through 86 which are coupled as inputs to preset terminals P₁ through P₄ or the main advance up-down counter 81. The select decoder 80 receives three inputs in addition to the input from the rate multiplier output terminal 54 and produces a main output at a pulse terminal 87 and a latched advance output signal S_IL at a terminal 88. The select decoder 80 receives the delayed advance pulses S↑D by means of a direct connection to the terminal 40, and the decoder also receives the pulses C₃ from a direct input connection to the terminal 30. In addition, the select decoder 80 also receives an input signal termed SSp from a spark logic circuit 90. The signal SSp is a signal produced by the spark logic circuit 90 at the desired time occurrence t_x of spark ignition and this signal is very short in duration (one period of the high frequency clock pulse signal Cp). The manner in which the spark logic circuit 90 creates the signal SSp will be subsequently discussed. For the time being it is sufficient to note that this signal occurs at times tx which represents the time at which spark ignition will occur according to the ignition control system 10.

[0051] It should be noted that at the output terminal 88 of the select decoder 80 the latched output signal S,L produced at this terminal is initiated in response to the delayed advance signal S₁D and is terminated at the time t_x. The output produced by the select decoder 80 at the main output terminal 87 essentially comprises the pulse signal C₃ during the pulses S,D (occurring at the times t,D) until the time t_x at which spark ignition occurs. After the times t_x until times t₁D the decoder 80 directly couples pulses at the rate multiplier output terminal 54 to the main terminal 87.

[0052] The terminal 88 of the select decoder 80 is directly coupled as an input to an up-down control terminal (U/D) of the main up-down advance counter 81. The terminal 87 of the select decoder is directly coupled to an input clock terminal (>) of the advance counter 81. A preset enable (PE) input terminal of the advance counter 81 directly receives the signal SSp by means of a direct connection to the output terminal 89 of the spark logic circuit 90.

[0053] An input reset terminal of the advance counter 81 receives a power on reset signal POR by means of a direct connection to a terminal 91. This power on reset signal is merely utilized to initiate operation of the ignition control system 10 in response to the initial application of power to the ignition control system. This is accomplished by means of a capacitor 92 coupled between the terminal 91 and a power on reset terminal 93 that receives positive power when power is applied to the ignition system control 10. The terminal 91 is coupled to ground through a resistor 94A. Thus the components 92, 93, 94A provide for a positive impulse at terminal 91 upon the first application of power to the power on reset terminal 93, and this is utilized to initiate the resetting of the advance counter 81. The advance counter 81 produces an output at a zero detect terminal 94 and this output is produced whenever the advance counter counts down to or through a count of zero.

[0054] Essentially, the auxiliary advance counter 82 is reset at the times t₁ by the S₁ pulses. The counter 82 then proceeds to count up in accordance with the pulses passed by the rate multiplier 53 and provided at the output terminal 54. This count is registered in the four bit binary output terminals 83 through 86. At the time t_x the signal SSp produces a positive spike at the present enable terminal of the main advance counter 81. This results in instantaneously transferring the count at the output terminals 83 through 86 of the auxiliary advance counter 82 into the main advance counter 81 at the times t_x. At this same time the latch signal at the terminal 88 (S₁L) is terminated resulting in the up-down control terminal of the advance counter 81 receiving a control input which tells it to count up any subsequently received clock pulses at its clock input terminal. At the times t_x' the select decoder 80 now channels the pulses produced at the output terminal 54 of the rate multiplier through the select decoder 80 and its output terminal 87 into the input clock terminal of the advance counter 81. The result of this is that the advance counter 81, after the time t, essentially acts as if it had continuously counted all of the pulses produced at the terminal 54 since the initial time t₁. The reason that the counter 81 did not directly count all of the clock pulses at the terminal 54 from the time t₁ to the time t_x was because the counter was engaged in a down counting operation at that time which determines the occurrence of spark ignition. This will now be explained in detail.

[0055] From the time t_x until the next time t₁, the advance counter 81 continues to count up all of the pulses produced at the output terminal 54 of the rate multiplier 53. Thus at the next time t, a maximum count is obtained by the main advance counter 81 which is related to the actual time difference between the periodic occurrence of synchronized advance sensor pulses S₁ at the times t₁. This means that the maximum count obtained by the counter 81 is related to engine speed and that the ROM 48 and rate multiplier 53 control this relationship in a piecewise linear manner to obtain the correct non-linear relationship between the maximum count in the advance counter 81 and engine speed, as well as the relationship between the maximum count and the sensed engine vacuum pressure.

[0056] At the time occurrences t,D, which occur just after each of the synchronized advance pulses S_1' the select decoder 80 produces a latched signal S,L at the terminal 88 which now instructs the advance counter 81 to count down instead of up. Simultaneously, the select decoder 80 now channels the fixed frequency clock pulses C₃ to its output terminal 87. The end result is that the main advance counter 81 will now count down at a fixed rate determined by the occurrence of the pulses C₃ until a zero count is obtained and a zero detect signal is produced at the terminal 94. At this time, this zero detect signal will be received by the spark logic circuit 90 and result in producing the spark occurrence signal SSp which will terminate further down counting, load the count of the auxiliary advance counter 82 into the main counter 81 and initiate the main counter 81 up counting the pulses produced at the terminal 54.

[0057] The operation of the components 80 through 82 is probably best understood by referring to Figures 91 and 9J. Figure 91 represents the accumulated count in the auxiliary advance counter 82. This count is essentially the non-linear pulse occurrences which occur at the output terminal 54 of the rate multiplier 53. At the times t_x at which the pulses SSp occur, the count of this counter is directly transferred to the advance counter 81 by means of preset enable circuitry. Preset enable circuitry for counters is very well known and merely results in loading a counter with a preset count in response to an actuation pulse being received at a preset enable terminal.

[0058] Figure 9J illustrates the count in the main advance counter 81. This figure illustrates that at the times t₁ a maximum count is obtained by the advance counter 81. Then at times t₁D the counter 81 will count down at the fixed rate determined by the rate occurrence of the signal C₃, whereas the up counting of this counter was determined by the ROM 48 and rate multiplier 53 implementing a steepwise rate of increase of pulse counts. U.S.-A-4,104,997 clearly illustrates how such a stepwise increasing rate combined with a linear decreasing rate will result in accurately determining the spark time occurrence for internal combustion engines so that a proper advance versus engine speed relationship is developed. Since the equations demonstrating this relationship are contained in the referred to issued U.S. patent, they will not be repeated here.

[0059] From the foregoing statements it should be evident that the decoder 80 and counters 81 and 82 effectively form an accumulating means for the pulses produced at the output terminal 54 of the rate multiplier 53. At the times t₁D, this accumulated count is then linearly decreased at a fixed rate determined by the time occurrence of the pulses C₃ until a zero detect signal is produced at the terminal 94. This zero detect signal represents the desired spark timing occurrence, and the spark logic circuit 90 utilizes this signal to produce the signal SSp at the terminal 89 as well as produce a composite signal (dwell/spark) at an output terminal 100 which contains both dwell and spark timing information. This composite signal at the terminal 100 is then coupled to an input terminal 101 of an output pre-driver 99 which supplies an output at a terminal 102 to a final driver stage 103, in an ignition coil power stage 98 (shown dashed), that controls the excitation of the primary winding 104 of an ignition coil. A high voltage secondary winding 105 of the ignition coil is coupled to the spark gaps of a two cylinder engine to produce ignition pulses therein.

[0060] A primary ignition coil current sensing resistor 106 is contemplated as sensing the current through the primary coil 104 and providing a feedback signal at a terminal 107 which is coupled as an input to the output pre-driver. This is utilized to maintain constant primary ignition coil current excitation in a well known manner. The output pre-driver 99 also receives an input at the terminal 109 related to actual battery voltage magnitude and another input at a terminal 110 related to whether or not an engine stall condition has occurred. If engine stall, abrupt slow crankshaft rotation, has been detected, then the current through the primary coil 104 will be slowly decreased so as to remove energization from this coil without generating a spark until the engine stall condition has been rectified. The battery voltage magnitude signal at the terminal 109 is utilized to alter the ignition coil current driving signal to obtain constant energy spark ignition despite variations in battery voltage. The output pre-driver 99 and the ignition coil power stage 98 are contemplated as comprising standard electronic ignition system components and therefore the details of these components will not be discussed since they do not form part of the present invention.

[0061] The spark logic circuit 90 which creates the dwell/spark control signal at terminal 100 receives the master clock pulses Cp from a direct connection to the terminal 26. The circuit 90 also is directly connected to the terminals 34 and 38 for receiving the signals S₁ and S₂, respectively. The spark logic circuit 90 receives the POR signal at a reset terminal for initiating the logic components contained in the circuit 90 in response to the initial application of power to the electronic ignition control system 10. The circuit 90 also receives the zero detect signal produced at the terminal 94 of the main advance counter 81. In addition, the spark logic 90 also receives a dwell initiation signal by means of a direct connection to an output terminal 120 of a dwell circuit 121, and the circuit 90 also receives a slow speed detect signal from an output terminal 122 of a slow speed decoder 123. In response to all of these inputs the spark logic circuit 90 produces the signal SSp at the terminal 89 wherein the SSp signal is a pulse at t_x which exists for one clock pulse period of the pulses Cp. The circuit 90 will also create a combined dwell initiate and spark timing occurrence output signal at the output terminal 100.

[0062] Essentially, once the spark logic circuit 90 has been reset by the application of power to the electronic ignition control system 10 by the POR signal, the logic circuit 90 will receive dwell initiate signals from the terminal 120 and spark timing occurrence signals from the terminal 94 for each cycle of cylinder compression. If for some reason a dwell initiating signal has not been received by the spark logic circuit 90 prior to the occurrence of the pulse S₁ which is generated at the maximum possible advance point of crankshaft rotation, then the spark logic circuit 90 will initiate dwell at the times t₁ corresponding to the occurrence of the pulses S_i. Similarly, if for some reason a spark ignition has not occurred by the times t₂ at which the pulses S₂ occur, then the spark logic 90 will create a spark occurrence at these times. Actually, when the slow speed decoder 123 determines that engine rotating speed is below a predetermined minimum level, the signal at the terminal 122 insures that dwell will be initiated at the times t₁ and that spark will occur at the times t₂. This provide a dwell equal to 35 degrees of crankshaft rotation for slow speed conditions and provides for spark ignition at essentially top dead center of the cylinder compression cycle. For engine speeds above this predetermined slow speed, the signal at the terminal 122 allows dwell to be initiated by the signal at the terminal 120 and spark to be determined by the zero detect provided at the terminal 94. The signal produced at the terminal 100 is initiated in response to when dwell is desired to commence (t_Dw) and is terminated in response to when the spark logic 90 determines spark ignition should occur (t_x).

[0063] A typical embodiment for the spark logic circuit 90 is illustrated in Figure 6. The power on reset connection has not been shown in Figure 6 in order to simplify the diagram. All of the components in Figure 6 correspond to standard logic gate components and flip-flop devices.

[0064] The engine stall indicating signal produced at the terminal 110 is the output of an engine stall counter 125 which receives a reset input signal by a direct connection to the terminal 34. The counter 125 receives a counting clock input signal by means of an input direct connection to the terminal 47 of the main up counter 41. In this manner, if the stall counter 125 determines that between consecutive times t₁ at which the synchronized advance pulses S₁ occur, the main up counter 41 has registered a predetermined number of changes in the most significant bit of the counter which is connected to the terminal 47, then the counter 125 will indicate that the count being registered by the main up counter 41 is too high. This indicates that the actual time elapsed between consecutive times t₁ is too great thus indicating that the engine has stalled by virtue of the fact that the engine crankshaft is not rotating above a predetermined speed. When this is determined, a stall indicating signal at the terminal 110 will be received by the output pre-driver 99 and result in appropriately modifying the output of the pre-driver to take into account this condition. The internal construction of the stall counter 125 merely consists of a resettable pulse counter which develops an output whenever the pulse count is above a predetermined threshold. Readily available logic circuits can implement such a function.

[0065] The slow speed decoder 123 essentially works on a similar principle to the stall counter 125. The slow speed decoder 123 determines when the count in the main up counter 41 exceeds a predetermined maximum count. This is accomplished by coupling the terminals 43 through 47 as inmputs to the slow speed decoder 123. The decoder 123 is reset at times t_lD via a connection to terminal 40. The decoder also receives the pulses S₁ via a direct connection to the terminal 34 and it receives a power on reset pulse via a direct connection to the terminal 91. In response to all of these inputs the decoder 123 produces a slow speed detection at the terminal 122 at times t₁ whenever the count of the main counter indicates that the actual time between the S_ID pulses exceeds a predetermined maximum time. Whenever this occurs, this indicates that the engine speed is below a predetermined minimum speed, and the signal at the terminal 122 is received by the spark logic circuit 90 and results in initiating dwell at the times t₁ and causing spark ignition to occur at the times t₂. Of course the engine speed which actuates the stall counter 125 is an engine speed much less than the predetermined engine speed which resulted in actuating the slow speed decoder 123. Figure 5 illustrates a typical embodiment for the slow speed decoder 123 and the components in Figure 5 represent standard logic circuit components used for a typical implementation.

[0066] It should be noted that Figure 4 illustrates a typical digital circuit implementation for the select decoder 80. In Figure 4 controllable gates 126 and 127 are illustrated. These gates operate as selective open or short circuits between their throughput terminals in response to the digital logic signals present at their respective control terminals 128 and 129.

[0067] It should also be noted that Figure 3 illustrates a typical digital circuit implementation for the advance and reference buffers 21 and 22, the pulse synchronizers 33 and 37, the delay circuit 39 and the inhibit circuit 36. Again it should be noted that the logic circuit implementations shown in Figure 3 comprise standard digital logic circuits.

[0068] The inhibit circuit 36, besides producing a four millisecond delay pulse at the terminal 35 in response to receiving a spark ignition signal (SSp) and in response to the received C, pulses provided as a timing duration input, also provides a two millisecond delay signal after spark ignition at an output terminal 130. The terminal 130 is coupled to the dwell circuit 121 and the two millisecond signal serves to inhibit the operation of the dwell circuit until at least two milliseconds after the occurrence of spark ignition. This is required in order to prevent 100 percent dwell from occurring at very high engine speeds. If 100 percent dwell were to occur then no spark ignition would be permitted since current excitation for the ignition coil primary winding 104 would always be applied.

[0069] Essentially the inhibit circuit 36 merely utilizes the signal (SSp) at the times t_x to initiate two different monostable time periods which are provided at the terminals 35 and 130 to implement different delays for circuitry in the electronic spark ignition control system 10. The detailed configuration of the inhibit circuit 36 will not be specifically recited since the embodiment in Figure 4 is a typical embodiment using standard components and many other embodiments could accomplish this desired function.

[0070] A typical embodiment for the dwell circuit 121 of the present invention will now be discussed.

[0071] Referring to Figure 7 the dwell circuit 121 receives running count counter inputs from the main counter output terminals 42 through 47 at preset input terminals P, through P₆ of a dwell down counter 131. The terminal 34 at which the S, pulses are produced is directly coupled to a preset enable terminal of the dwell down counter and a counting clock pulse input terminal 132 for the dwell down counter is provided.

[0072] In Figure 7, output count terminals 42 through 47 of the main counter 41 are connected to preset inputs P, through P6 of the dwell down counter 131. A preset enable terminal of the dwell counter 131 is directly coupled to the terminal 34 such that the counter will be preset in response to the pulses S_I. In Figure 7 a dwell counter overflow terminal is directly connected to a terminal 139 which is coupled to a terminal 140 that is directly connected to the set terminal of a latch 141 having its output connected to the terminal 120 through a controllable gate 144. A reset terminal of the latch 141 is directly connected to the terminal 34 thus providing for resetting the latch 141 in response to the signal S,. The controllable gate 144 has a control terminal 143 which is directly connected to the terminal 130 such that the controllable gate 144will implement a minimum 2 millisecond delay after SSp for initiating a dwell signal at terminal 120.

[0073] The dwell down counter 131 has a clock input terminal 132 which is coupled through a controllable gate 133 and an OR gate 160 to the terminal 31 at which the pulses C₄ are present. An auxiliary dwell counter 134 has a reset terminal directly connected to the terminal 40 and a clock signal input terminal directly connected to an output terminal 159 of gate 133. The output count of the auxiliary dwell counter 134 is coupled to a maximum count logic circuit 135 which produces an output signal at a terminal 137 whenever the auxiliary dwell counter count equals or exceeds a predetermined count. The terminal 137 is directly connected as a control input terminal to the controllable gate 133, and this terminal is also coupled through an inverter stage to a control input terminal 150 of a controllable gate 151 coupled, together with OR gate 160 between the terminal 132 and the terminal 28 at which the pulses C, are present. The OR gate 160 permits pulses passed by either of the controllable gates 133 or 151 to reach the terminal 132.

[0074] The operation of the dwell circuit 121 illustrated in Figure 7 will now be described with reference to the graph shown in Figure 9Q which essentially illustrates the operation of the dwell circuit 121 by illustrating the count of the dwell down counter 131 as a function of time. At the times t₁, the dwell down counter 131 is preset with the maximum count obtained by the main up counter 41. At the subsequent times t,D, the count of the auxiliary dwell counter 134 is set to zero resulting in the controllable gate 133 passing a predetermined number of the rapidly occurring clock pulses C₄. After the auxiliary dwell counter has counted this predetermined number of C₄ pulses, the maximum count logic circuit 135 will open the controllable gate 133 and result in closing the controllable gate 151. During this time, the dwell down counter 131 has effectively, instantaneously subtracted this predetermined number of counts from the maximum count which was preset into the dwell counter 131. Subsequent to this subtraction, the dwell down counter 131 will continue down counting at a rate determined by the occurrence of the pulses C_l. It should be noted that this occurrence rate is the same occurrence rate at which the main counter 41 is being linearly incremented up to its maximum count representative of engine crankshaft speed. At a subsequent time t_DW the count in the dwell down counter 131 will reach zero and on the next count an overflow indication will be produced at the terminal 139. This will result in setting the latch 141 and providing a dwell initiation signal at the output terminal 120 assuming at least a two millisecond delay between spark occurrence and dwell initiation.

[0075] The dwell circuit in Figure 7 avoids the need for a complex count comparator by having the dwell down counter 131 continue to count down at a rate determined by the C, pulses after effectively subtracting a predetermined number of counts occurring at the rapid frequency of the signal C₄. In this manner, the output of the dwell down counter 131 will reach zero at predetermined times t_Dw ahead of the predetermined times t,. This occurs since if no counts were subtracted and engine speed remained the same, then the dwell down count would overflow exactly at times t,. Thus the dwell circuit 121 insures that dwell initiation will occur at a predetermined time prior to the occurrence of the advance pulses S₁, at the times t,. The circuit 121 in Figure 7 accomplishes this end result without the use of a complex comparator and is therefore believed to be more economical since fewer connecting lines and logic gates are required than hitherto known.

[0076] The controllable gate 144 is utilized to insurethat the dwell initiation signal at terminal 120 will not start until at least 2 milliseconds after the occurrence of spark ignition. This insures that 100 percent dwell will not be obtained, and that therefore the primary ignition coil winding 104 will not be constantly excited. This insures the occurrence of a spark for each cylinder when it is in its compression cycle, since if the primary winding always received current excitation no spark could be generated.

[0077] It should be noted that while the present invention contemplates utilizing the crankshaft position sensor signal S₁ as the periodic signal having periodicsignal pulse transitions occurring at predetermined variable (speed dependent) rate, the present invention also contemplates the use of the spark occurrence signal SSp as the periodic signal having pulse transitions which occur at a variable (speed dependent) rate. In this mannerthe present invention can implement dwell at a predetermined time prior to spark ignition occurrence rather than at a predetermined time prior to the occurrence of a specific engine crankshaft position. In order to implement such a change only minor modifications of the disclosed circuitry are necessary and these modifications are within the capability of those of average skill in the art.

[0078] In Figure 9P, the count of the dwell counter 131 is illustrated as a solid line whereas the count of the main up counter 41 is illustrated as a dashed line. Figure 9P illustrates at the times t, a maximum count is preset into the dwell down counter 131 and then a predetermined number of counts is rapidly subtracted (at times t₁D) from this number. Subsequently the dwell counter 131 maintains this subtracted count as its output. At the times t₁ D, the count in the main counter 41 is set to zero and this counterwill commence up counting in response to the pulses C, resulting in linear incrementing of the count of the counter 41. At a subsequent time t_DW the count in the main counter 41 will equal the subtracted count being maintained by the dwell counter 131. At this time t_DW the comparator 138 will produce a logic signal that will setthe latch 141 and thereby signal the initiation of the dwell by the signal produced at the latch output terminal 120. The latch 141 will be reset upon the occurrence of the pulse signal S,.

[0079] The preset invention by utilizing substantially all of the time duration between identical polarity pulse transitions of the crankshaft position sensor signal S₁ to determine the maximum running count which is related to engine speed, has provided a maximum running count which is an extremely accurate indication of engine speed. Since this running count is updated for each engine crankshaft rotation of 360 degrees, the engine speed information is similarly updated for each crankshaft revolution thus providing an up-to-date indication of engine speed. By providing a maximum running count related to engine speed during one full cycle (between identical polarity transitions) of crankshaft revolution and utilizing this maximum running count to determine dwell initiation during the subsequent cycle of crankshaft revolution, the present invention is capable of producing large dwell angles which is something that has not been obtained by similar prior art circuits (U.S.-A-3 908 616) which illustrate utilizing a first portion of the crankshaft revolution cycle to calculate engine speed and a second portion of the same crankshaft revolution cycle to calculate dwell occurrence. Thus the prior art circuits limit dwell occurrence to this second portion of the crankshaft revolution cycle.

[0080] In addition to permitting the dwell circuit to implement large angles of dwell excitation, the present invention implements dwell without adjusting count threshold levels of count comparators and without adjusting the various rates of count accumulating. While adjusting the rate of count accumulating was found to be necessary for the spark control circuitry disclosed herein, it is obvious that the rate adjustment circuitry is much more complex and costly than the dwell control circuitry. Thus the present invention is believed to be superior to prior dwell control circuits which require adjusting pulse accumulation rates or pulse count switching threshold levels in order to implement a desired dwell excitation mode over a range of different engine speeds.

Claims

1. Digital circuitry for receiving a signal comprising periodic pulse transitions and producing indicative signals commencing at times prior to the occurrence of the periodic pulse transitions, said circuitry comprising:

means (11-16, 21, 33) for producing a periodic sign (S_i) comprising periodic pulse transitions (t,) occurring at a variable repetition rate; counting means (39, 41) counting independent timing pulses (C,) between first (t_1D) and second (t,) time occurrences and providing at said second time occurrence a maximum running count related to the time duration between said first and second time occurrences, said first (t_1D) and second (t,) time occurrence directly corresponding to the occurrence of sequential first and second pulse transitions of said periodic signal (S,);

means (131-137) for periodically receiving said maximum count and effectively subtracting a predetermined number of counts therefrom to obtain a resultant subtracted count, said subtraction being completed at substantially said second time occurrence (t_l);

characterised in that there is provided means (131, 151, 160) for counting down said resultant subtracted count at a rate which is independent of said variable repetition rate; and

means (131, 141) for periodically initiating an indicative signal when the down count from said resultant subtracted count equals a predetermined threshold count (zero) subsequent to said second time occurrence (t₁) and at a predetermined time prior to the next of said periodic signal pulse transitions (t₁).

2. Circuitry as claimed in Claim 1 wherein said threshold count is fixed.

3. Circuitry as claimed in Claim 1 wherein said rate for counting down from said resultant subtracted count is fixed.

4. Circuitry as claimed in any preceding claim wherein said threshold count is zero.

5. Dwell circuitry for an ignition control system of an internal combustion engine comprising the circuitry of any preceding Claim wherein said pulse transitions (t₁) have occurrences related to predetermined angular positions of rotation of an engine crankshaft so that said maximum running counts are related to the rotational speed of the engine crankshaft; and ignition dwell means (90, 99, 103) wherein dwell is initiated in response to said incremented resultant count being at least equal to a threshold count (zero), whereby dwell is substantially initiated at a fixed predetermined time prior to the next occurrence of a maximum running count at said second time occurrence.

6. Dwell circuitry as claimed in Claim 5 wherein said counting means includes a pulse counter (41) for developing a running count, and wherein at least one of said running counts and said maximum running counts is utilized by spark timing means (48, 53, 56, 80, 81, 82, 90) for determining spark occurrences subsequent to dwell initiation.

Revendications

1. Circuit numérique pour recevoir un signal comprenant des transitions d'impulsions périodiques et produire des signaux indicatifs commençant à des instants antérieurs à l'apparition des transitions d'impulsions périodiques, ce circuit comprenant:

un moyen (11-16, 21, 33) pour produire un signal périodique (Si) comprenant des transistions d'impulsions périodiques (t_i) survenant à une vitesse de répétition variable;

un moyen de comptage (39, 41) comptant des impulsions de temporisation indépendantes (C₁) entre des premiers (t_1D) et seconds (t_i) instants et fournissant aux seconds instants un comptage dynamique maximal lié à la durée entre les premiers et seconds instants, les premiers (t_1D) et seconds (t,) instants correspondant directement à l'apparition de premières et secondes transitions d'impulsions séquentielles du signal périodique (S,);

un moyen (131-137) pour recevoir périodiquement le comptage maximal et soustraire effectivement un nombre prédéterminé de comptages de celui-ci pour fournir un comptage soustrait résultant, cette soustraction étant achevée sensiblement aux seconds instants (t,);

caractérisé en ce qu'il est prévu des moyens (131, 151, 160) pour décompter le comptage soustrait résultant à une vitesse indépendante du taux de répétition variable; et

un moyen (131, 141) pour initialiser périodiquement un signal indicatif du moment où le décomptage du comptage soustrait résultant est égal à un comptage de seuil prédéterminé (zéro) après le second instant (t,) et à un instant prédéterminé avant la suivante des transitions d'impulsions de signal périodique (t,).

2. Circuit selon la revendication 1, dans lequel le comptage de seuil est fixe.

3. Circuit selon la revendication 1, dans lequel la vitesse de décomptage à partir du comptage soustrait résultant est fixe.

4. Circuit selon l'une quelconque des revendications précédentes, caractérisé en ce que le comptage de seuil est égal à zéro.

5. Circuit de déclenchement pour système de commande d'allumage d'un moteur à combustion interne comprenant le circuit selon l'une quelconque des revendications précédentes dans lequel les transistions d'impulsions (t,) présente des instants d'apparition liés aux positions de rotation angulaire prédéterminées d'un vilebrequin de moteur de sorte que les comptages dynamiques maximum sont liés à la vitesse de rotation du vilebrequin du moteur; et un moyen de déclenchement d'allumage (90, 99, 103) dans lequel le déclenchement est initialisé en réponse au fait que le comptage résultant incrémenté est au moins égal à un comptage de seuil (zéro), d'où il résulte que le déclenchement est sensiblement initialisé à un instant fixe prédéterminé avant l'apparition suivante d'un comptage maximal audit second instant.

6. Circuit de déclenchement selon la revendication 5, dans lequel le moyen de comptage comprend un compteur d'impulsions (41) pour fournir un comptage dynamique et dans lequel au moins un des comptages dynamiques et desdits comptages dynamiques maximum est utilisé par un moyen de temporisation d'étincelles (48, 53, 56, 80, 81, 82, 90) pour déterminer des apparitions d'étincelles suivant l'initialisation de déclenchement.

Ansprüche

1. Digitale Schaltung zum Empfangen eines Signals mit periodischen Pulsübergängen und zum Erzeugen von anzeigenden Signalen, die zu Zeitpunkten vor dem Auftreten der periodischen Pulsübergänge beginnen, wobei die Schaltung folgende Merkmale aufweist:

eine Einrichtung (11-16, 21, 33) zum Erzeugen eines periodischen Signals (S₁) mit periodischen Pulsübergängen (t_i), die mit einer veränderlichen Wiederholungsrate auftreten;

eine Zähleinrichtung (39, 41) zum Zählen von unabhängigen Taktpulsen (C₁) zwischen ersten (t_1D) und zweiten (t₁) zeitlichen Auftritten und zum Erzeugen eines maximal laufenden Zählwertes bezüglich der Zeitdauer zwischen den ersten und zweiten zeitlichen Auftritten zum Zeitpunkt des zweiten zeitlichen Auftretens, wobei die ersten (t_1D) und zweiten (t₁) zeitlichen Auftritte direkt dem jeweiligen Auftreten der aufeinanderfolgenden ersten und zweiten Pulsübergänge des periodischen Signals (S₁) entsprechen;

eine Einrichtung (131-137) zum periodischen Empfangen des maximalen Zählwertes und zum wirksamen Subtrahieren einer vorbestimmten Anzahl von Zähleinheiten von diesem Wert, um einen resultierenden, subtrahierten Zählwert zu erhalten, wobei diese Subtraktion im wesentlichen bei dem zweiten zeitlichen Auftreten (t₁) beendet ist;

dadurch gekennzeichnet, daß eine Einrichtung (131, 151, 160) zum Abwärtszählen des sich ergebenden subtrahierten Zählwertes mit einer Geschwindigkeit vorgesehen ist, die unabhängig von der veränderlichen Wiederholungsrate ist; und

daß eine Einrichtung (131, 141) zum periodischen Veranlassen eines anzeigenden Signales vorgesehen ist, wenn der untere Zählwert von dem sich ergebenden subtrahierten Zählwert einem vorbestimmten Schwellenwert (Null) nach dem zweiten zeitlichen Auftreten (t₁) und eine vorbestimmte Zeitdauer vor dem nächsten periodischen Signalpulsübergang (t₁) entspricht.

2. Schaltung nach Anspruch 1, bei der der Schwellenzählwert festliegt.

3. Schaltung nach Anspruch 1, bei der die Rate zum Abwärtszählen von dem sich ergebenden subtrahierten Zählwert festliegt.

4. Schaltung nach einem der vorhergehenden Ansprüche, bei der der Schwellenzählwert Null ist.

5. Haltezeitschaltung für ein Zündsystem eines Motors mit innerer Verbrennung mit der Schaltung nach einem der vorhergehenden Ansprüche, bei der die Pulsübergänge (t₁) ein Auftreten haben, das in Beziehung steht zu vorbestimmten Winkellagen der Drehung einer Motorkurbelwelle, so daß die maximal laufenden Zählwerte in einer Beziehung stehen zu der Drehgeschwindigkeit der Motorkurbelwelle; und eine Zündhaltezeiteinrichtung (90, 99, 103) aufweist, bei der die Haltezeit begonnen wird in Reaktion auf den erhöhten, sich ergebenden Zählwert, der wenigstens gleich einem Schwellenwert (Null) ist, wodurch die Haltezeit im wesentlichen eine feste vorbestimmte Zeit vor dem nächsten Auftreten eines maximal laufenden Zählwerts bei dem zweiten zeitlichen Auftreten veranlaßt wird.

6. Schwellenwertschaltung nach Anspruch 5, . bei der die Zähleinrichtung einen Pulszähler (41) zum Erzeugen eines laufenden Zählwertes aufweist, und bei der wenigstens einer der laufenden Zählwerte und der maximal laufende Zählwert durch eine Zündfunkentaktgebereinrichtung (48, 53, 56, 80, 81, 82, 90) zum Bestimmen des Auftretens eines Zündfunkens nach dem Beginn der Haltezeit verwendet wird.

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