(19)
(11) EP 0 105 105 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
05.11.1986 Bulletin 1986/45

(43) Date of publication A2:
11.04.1984 Bulletin 1984/15

(21) Application number: 83106973

(22) Date of filing: 15.07.1983
(84) Designated Contracting States:
DE FR GB IT

(30) Priority: 31.08.1982 JP 15090282

(71) Applicant: KABUSHIKI KAISHA TOSHIBA
 ()

(72) Inventors:
  • Suzuki, Hiroaki
     ()
  • Sasaki, Itsuo
     ()

   


(54) Data readout circuit for a MOS transistor array


(57) A data readout circuit for an MOS transistor array (1) includes a plurality of data output lines (B1 to B4). To each of the data output lines are connected N-channel MOS transistors (Trn) of a corresponding row group. Each of P-channel data output line selection MOS transistors (Tp1 to Tp4) is connected between each of the data output lines (B1 to B4) and a data output node (W1). An access time is shortened by controlling the data output line selection MOS transistors (Tp1 to TP4) to be conductive while the data output lines (B1 to B4) and the data output node (W1) are both in a precharged state.






Search report