[0001] The present invention relates to lamp flashers and more particularly to apparatus
for flashing lamps in particular code sequences and for synchronising a number of
lamp flashing systems.
[0002] Marine buoys and beacons commonly use incandescent lamps which are periodically flashed
in various sequences of short and long flashes separated by short and long eclipses
for identification of channels, obstructions and other navigational features. Many
such devices are battery operated and conservation of primary power is important.
In recent years, older flashing systems using motors and relays have been supplanted
by transistor timing and control circuits. For example, see the following of the Applicants
U.S. Patents: US-A-3 244 892; US-A-3 310 708; and US-A-3 596 113. To obtain reliability
and accurately timed signals, voltages must be regulated. To eliminate relays, transistor
switches have been used. Prior art regulating and switching transistors have generally
been germanium types to minimize voltage drops; however, these types have high leakage,
especially at high temperatures. Lower leakage at high temperatures can be obtained
with the use of silicon transistors but at the expense of higher voltage drops.
[0003] In many applications, a number of beacons or buoys are required to operate in synchronism,
and generally, a master flasher controls a set of slave units. When the master fails,
improper operation of the slaves is common. A need exists for a flexible easily programmable
flasher control circuit that will minimize primary power drain, that will permit any
unit to synchronize the remaining units, that will not fail when other units fail,
and which will permit almost any coded signals to be generated.
[0004] US Patent No. US-A-3 855 587 discloses a flashing light timer for a navigational
light in which the timing is controlled by a plurality of different time constant
circuits and a counter having a plurality of sequentially operated outputs, with the
time constants selected through a code board. Additionally a burned-out lamp is sensed
and a turret is controlled to change that lamp with accurate alignment.
[0005] According to one aspect of this invention, there is provided apparatus for producing
a preselected sequence of flashes and eclipses from a lamp comprising:
lamp control means connected to said lamp for energizing said lamp during a flash
period;
timing generator means connected to said lamp control means for producing a start
timing pulse for starting a flash period and a stop timing pulse for terminating a
flash period;
flash period control means connected to said timing generator means for controlling
the time between said start timing pulse and said stop timing pulse, said flash period
control means having a short flash control input and a long flash control input;
eclipse period control means connected to said timing generator means for controlling
the time between said stop timing pulse and said start timing pulse, said eclipse
period control means having a short eclipse control input and a long eclipse control
input; and
counter means having a set of sequential count outputs, the number of said count outputs
selected to be equal to the number of flashes in said preselected sequence, each of
said count outputs connected to selected ones of said flash and eclipse control inputs
for controlling said flash period and said eclipse period to produce the durations
of the flash and the eclipse preselected for each position in said preselected sequence,
said counter means having its clocking input connected to said timing generator means
for receiving each of said start timing pulses to cause each count output to have
a duration equal to the time between its clocking start timing pulse and the next
clocking start timing pulse.
[0006] The voltage regulator and switching circuits may utilize silicon transistors having
low leakage in a novel connection that produces low voltage drops. In one embodiment
the current to the lamp is monitored during flashes and a lamp change switch is closed
when a lamp failure is detected energizing an automatic lamp changer.
[0007] In a preferred embodiment a solid-state flash sequence generation circuit is provided
using, for the most part, integrated logic circuits. Almost any code sequence or sequence
of short and long flashes and eclipses can be generated. The sequence generator utilizes
an electronic counter which produces a count for each sequential flash and eclipse
pair. A set of electronically switched RC time constants are controlled form the counter
to produce the desired flash and eclipse durations of each successive set of a flash
and eclipse. The selected time constants for a given flash-eclipse period controls
a timing generator which clocks the counter at the beginning of each such flash-eclipse
period.
[0008] Preferably the apparatus further comprises synchronization pulse generation means
connected to said lamp control means and having a synchronization output/input terminal,
said synchronization pulse generation means controlled to produce at said output terminal
a short first synchronization pulse at the beginning of each flash period in said
sequence.
[0009] When a number of flashers are to be operated together, this feature permits synchronization
of the flashes and eclipses. The sync pulses produced at the beginning of each flash
may be fed to a cable or other link to the other flasher units in the system. If all
units are not in synchronization, the sync pulses will cause all of the other units
to reset and synchronize. Advantageously, any unit can serve as the master and the
remainder as slaves. Therefore, failure of a master will not affect the other units.
[0010] The apparatus may also include a daylight control to disable the flashes during the
day, thereby conserving primary power. When darkness falls, the daylight control will
cause at least one flasher to begin operation. The sync pulses from the first enabled
unit will automatically cause the remainder to operate, regardless of whether their
daylight controls have been triggered. In the morning, all units will remain operating
until the least sensitive daylight control is operated at which time all units will
cease flashing. Therefore, if a very sensitive daylight control on a flasher attempted
to prematurely disable that unit, the sync pulses from the other units would maintain
operation thereof, providing a fail-safe system.
[0011] According to another aspect of this invention there is provided a system of flashing
beacons for buoys and the like having a plurality of spaced apart flash units interconnected
by communication links, said beacons producing a preselected sequence of flashes and
eclipses representative of an identification code or the like and in which all beacons
flash in synchronism, comprising:
lamp means at each of said flasher units;
flash and eclipse period generation means in each of said flasher units for producing
a set of lamp control pulses, said set of lamp control pulses defining the preselected
sequence, said pulses energizing said lamp means during the flash period of said set;
synchronization pulse generation means for producing a synchronization pulse at each
of said flasher units at the beginning of each flash period;
output means connected to said sync pulse generation means for transmitting said synchronization
pulses from each of said flasher units to all other of said flasher units; and
synchronizing means in each of said flasher units for resetting said flash and eclipse
period generation means to the beginning of a set when a synchronizing pulse is received
from another flasher unit by a unit which is out of synchronization.
[0012] In a further aspect of this invention there is provided a flasher unit for use in
a system of synchronized flasher units which can be programmed to produce a desired
sequence of short and long flashes separated by short and long eclipses and which
produces synchronization pulses for synchronizing other externally-connected flasher
units therewith.
[0013] In a further aspect of this invention there is provided a flasher unit having a daylight
control for use in a system of multiple units interconnected by communication links,
all units having a daylight control circuit and arranged such that all units will
continue flashing until the least sensitive daylight control unit inhibits its flasher
unit; and in which the first flasher unit to be enabled with a drop in ambient light
will cause all other units to begin flashing.
[0014] Preferred embodiments of the invention have a flasher unit having a silicon transistor
switch and regulator having a low voltage drop across the regulator when the supply
voltage falls below the regulated value.
[0015] Preferably, the invention provies a switch and voltage regulator using silicon transistors
connected to produce a darlington circuit for a first current level and to change
to a single regulator circuit at a second current level.
[0016] In another preferred embodiment of the invention a switch and regulator uses a darlington
circuit modified to permit driving the switching transistor to a preselected low voltage
drop.
[0017] Preferably the invention provides a lamp current sensing circuit to determine when
a lamp has failed and to thereafter energize an automatic lamp changing mechanism.
[0018] Advantageously the invention provides a novel lamp flash sequence generating circuit
using integrated logic circuits which minimize power drain on the power source and
which have long life and low cost.
[0019] Advantageously the invention provides a sequence generating circuit permitting selection
of a very large variety of short and long flash sequences without the use of mechanical
devices, relays, or motors.
[0020] In a preferred embodiment of the invention there is provided a sequence generating
circuit utilizing a steppable counter controlled by timing pulses in which a first
timing pulse steps the counter to the next count, in which the time to the next timing
pulse is controlled in accordance with the length of the required flash and eclipse
for that count, and in which the next timing pulse is generated causing the counter
to step to the next count.
[0021] These and other aspects and advantages of my flasher system will be apparent from
the following detailed description which is by way of example only, reference being
made to the accompanying drawings, in which:
Figure 1 is a waveform diagram of a simple code sequence for the flasher unit illustrated
in Figure 2;
Figure 2 is a simplified functional block diagram of a flasher unit of the invention;
Figure 3 is a simplified functional diagram of a system of flasher units interconnected
by communication links;
Figure 4 is a schematic diagram of the voltage regulator and switch portions of a
flasher unit;
Figure 5 is a schematic diagram of the logic circuits for producing a sequence of
flashes of a flasher unit; and
Figure 6 is a waveform diagram of two cycles of the sequence of flashes produced by
the unit shown in Figures 4 and 5.
[0022] Referring first to Figure 2 which provides a greatly simplified functional block
diagram of the lamp control and synchronizing system of the invention and to Figure
1 which illustrates certain waveforms occuring during the operation of the system,
the basic mode of operation will be explained. Lamp 24, shown in Figure 2, may be
an incandescant lamp installed in a buoy or on obstructions in a waterway such as
an oil drilling platform or the like. It is required to flash lamp 24 in a particular
sequence to produce a code for identifying to vessels the significance of the particular
buoy or structure. In Figure 1, a specific light flashing cycle is shown for exemplary
purposes only and it is to be understood that a large number of different coded signals
may be produced by my invention. Line B shows a sequence of flashes FL in which a
code is generated consisting of three code elements; in this case, two short flashes
and a long flash, indicative of the Morse code letter U. The first short flash 10
may be, for example, on the order of three tenths of a second. The lamp is then OFF
for a short period as indicated at 12. The OFF period, EC, is termed as "eclipse".
This eclipse is followed again by a short flash and a short eclipse. The long flash
shown at 16 is much longer than the short flash and is indicated as being about three
times the short flash length in this example, or about one second. A long eclipse
18 follows the completion of the Morse letter U at which time the coded letter is
again repeated. It is to be understood that the flash and eclipse ratios may be varied
as desired. An example of one timing is as follows: short flash, ON for 0.3 seconds,
OFF for 0.7 seconds; and long flash, ON for 1 second, OFF for 3 seconds.
[0023] Referring to Figure 2, lamp 24 is flashed or turned ON by means of lamp control circuits
22 which close a circuit to one side of lamp 24. Power is supplied from power supply
32 which may commonly be primary or secondary batteries or other types of power supplies.
To maintain a long lamp life, the flash output voltage is controlled by regulator
28 which effectively controls the maximum voltage that can be applied to lamp 24.
The current which flows through lamp 24 is monitored by lamp current sensor 26. As
will be explained in more detail below, a series resistor in the circuit of lamp 24
is not required for current monitoring in accordance with the described embodiment.
An indication from lamp control 22 appearing on lead 27 indicates to lamp sensor 26
that lamp 24 is in the ON condition. If, at that time, the lamp current noted is not
within the normal limits for lamp 24, a control signal is sent to an automatic lamp
changer 30 described in U.S. Patent No. 3,308,338, which replaces lamp 24 with a new
unit. Regulator 28 also includes means for regulating the operating voltage to the
electronic flash control circuits of my invention.
[0024] Next, the manner in which this embodiment produces the required control of lamp 24
will be described. A counter 40 is utilized to define the time period for each set
of flashes and eclipses such as 10 and 12, and 16 and 18 of Figure 1. As may be noted,
the time period 10 and 12 is much shorter than time period 16 and 18; therefore, counter
40 is controlled to provide different length count periods through its cycle. In the
present example, ony three count periods are required for producing flashes representative
of the Morse code U as shown on line B of Figure 1. Therefore, in one cycle, counter
40 will step from ZERO count to the ONE count, to the TWO count, and will then automatically
reset by virtue of connection of the count THREE output to the reset termination of
counter 40. Therefore,-the counter cycles, as shown on lines C, D, and E, produce
a short pulse 14 at the ZERO output, a short pulse 15 at the ONE output and a long
pulse 20 at the TWO output.
[0025] The control to produce the long and short periods is provided by a set of switches
44, 48, 52 and 58 with associated resistors 60, 62, 64 and 66. At a particular count,
the desired resistors are switched so as to charge capacitor 68 (C,) wherein the time
constants control the lengths of the flash and eclipse during that output pulse of
counter 40. In the present example, resistor 60 (R,) is selected to produce a time
constant proportional to the length of the counter output pulses 14 and 15 as will
be explained in more detail hereinafter. Switch 44 is controlled by gating circuits
42 to produce a short flash 10 with the necessary gate control signals provided by
lamp control circuit 22. Similarly, switch 48 which controls resistor 62 (R
2) is controlled by short eclipse gates 46, which are also controlled by lamp control
circuits 22. Thus, the value of resistor R
2 determines the OFF period 12 of the lamp and, in this application, R, and R
2 may have equal values if equal flash and eclipse durations are required. In some
instances the flash and eclipse periods are unequal; for example, a ratio of 3 to
7 is commonly used. In a similar fashion, switches 52 and 58 control resistors 64
(R
3) and 66 (R
4) in which the time constants of the selected resistors in conjunction with capacitor
68 (C
i) produces either long flash duration 16 or long eclipse duration 18. To provide the
long flash and long eclipse, a set of gates 50 and 54 is used, each having four inputs
for this purpose. Therefore, in one cycle, it is possible to have four long flashes
and four long eclipses. However, my invention is not limited to this number and it
is obvious that additional gating inputs could be provided for this purpose. The selection
of the point in a cycle of flashes at which a long flash and a long eclipse is required
is selected by connecting an input of gate 50 and of gate 54 to the counter output
occurring at the desired point in the cycle. In the present example, the long flash
16 and long eclipse 18 is desired at the third count which is count TWO on line E
and therefore inputs from gates 50 and 54 are connected to the count TWO output of
counter 40. Since this is the only count in the cycle requiring the long flash and
eclipse, the remainder of the gate inputs are grounded.
[0026] The control which causes the long and short outputs from the counter 40 is provided
by use of clock and timing generator 34. As will be described in more detail hereinafter,
clock and timing generator 34 produces a sequence of timing pulses on lead 35 to lamp
control circuits 22 as shown on line A of Figure 1. The time between these pulses
is controlled by the selection of resistors R, through R
4. The timing pulses may be short pulses in the range of one millisecond to ten milliseconds
at the start of each required flash or eclipse and in the center of each flash or
eclipse. These timing pulses are directed by lamp control circuits 22 via lead 23
to the clock input of counter 40 causing it to step one count shortly after the beginning
of each flash. If the time between the first pulse 11, referred to as a START pulse,
and the third pulse 13, referred to as a STOP pulse, is short, flash lamp control
circuits 22 enable gate 42 on the START pulse and gate 46 on the STOP pulse, both
of which occur during count ZERO from counter 40. Thus, resistors 60 and 62 are switched
in sequentially. As may be understood, when the START pulse 11 enables gate 42, the
short time constant of R1 C1 will cuase clock and timing generator 34 to produce the
STOP pulse 13 of the pair which causes lamp control circuit 22 to enable short eclipse
gate 46. Similarly, when the START pulse 17 of the long flash period occurs as counter
40 steps to produce output pulse 20 on its TWO output, pulse 20 enables one input
of gates 50 and 54. A flash pulse will then appear on lead 41 from lamp control circuits
22 to long flash gates 50 which then operate switch 52 to connect resistor R
3 to capacitor C
1 producing a long time constant for long flash 16. When the STOP timing pulse 19 appears
on lead 35 to flash lamp control circuits 22, an eclipse pulse on lead 43 enables
long eclipse gates 54, switching resistors R
4 on resulting in eclipse period 18.
[0027] The desired arrangement also includes a daylight control subsystem comprising daylight
control circuit 70 and photocell 72. The purpose of this control is to disable the
flashing system during daylight hours and to turn on the system at night. As will
be explained in more detail below, during daylight or when sufficient incident light
falls on photocell 72, clock and timing generator 34 is prevented from producing timing
pulses. It is desirable that, when the system is turned on, all units in the system
will begin at the beginning of the cycle shown on line B in Figure 1. To this end,
lamp control circuits 22 produce a short synchronizing pulse at the start of each
flash and during the first flash of each cycle. In the present example, a sync pulse
would occur at the same time as pulse 11 and as the second timing pulse on line A.
The sync pulses will apear on lead 29 from lamp control circuits 22 to sync output
amplifier 36. The sync pulses are then externally available on output line 37 for
purposes described below. The sync pulses also reset clock and timing generator 34
and via control circuits 22, counter 40, to ensure that the first sequence of flashes
begins at the start of a cycle.
[0028] Turning now to Figure 3, an array of N flasher systems is shown, each being of the
type illustrated in Figure 2. As is to be understood, when each of the photocells
72 is exposed to sufficient light, the flasher systems will all be inhibited as previously
described. The objective of this arrangement is to cause all of the systems in the
array to come on at the same time and to be synchronized. It is generally not feasible
to have the sensitivity of all the photocells identical and, even if this were true,
the light incident on each cell would not normally be of the same intensity since
each of the systems would be at a different location. For purposes of illustration,
assume all of the systems are off and that system 2 experiences a sufficient reduction
in light on its photocell 72 to start the operation of the flasher as described above.
When this occurs, the sync signals appearing on lead 29 from lamp control 22 of Figure
2 will be sent out on lead 37 via sync output 36. In this instance, the sync pulses
will be transmitted via links 39 to system 1, system 3 and the remainder of the systems
in the array. Thus, as each of the other systems receive the sync pulses, it resets
its clock and timing generator 34 and counter 40, causing each of the systems to override
its daylight control 70 which is inhibited by a control signal on lead 71 from flash
lamp control circuits 22. It is to be now noted that each system is producing its
own sync signals with all sync signals occurring simultaneously and appearing on each
output lead 37. When the light conditions change such as to energize photocells 72,
it is also an object of this arrangement to require that all units remain flashing
until the least sensitive or last unit to be turned off by daylight control 70 occurs.
Assume now that the system 3, photocell 72 is the last unit to receive sufficient
light to disable the flashing system. At this time, all of the other untis will have
been controlled by their photocell to cause daylight control 70 to attempt to stop
the unit from flashing. However, the synchronizing pulse from system 3 appearing at
the sync input on lead 37 at each of the other systems will again perform the function
of keeping each of the units operating. However, when system 3 eventually turns off
due to sufficient illumination of its photocell 72, its sync pulse disappears from
lead 37 and all systems will therefore turn off at the same time. Although Figure
3 shows a conductive line 39 between leads 37 of each unit it is to be understood
that any type of interconnection can be used as determined by the environment of the
systems. For example, a cable connection may be used on large structures such as oil
drilling platforms and a radio link may be used for buoys. I do not consider the interconnection
means to be a part of my invention.
[0029] Having now described the basic operation of the illustrated embodiment the specificl
novel circuits will now be explained in more detail. Figure 4 presents a schematic
diagram of the power supply regulators and lamp circuit sensor portions of the arrangement.
This circuit consists of three basic elements: a voltage regulator for the electronic
circuits 80, a voltage regulator 90 to control the voltage applied to incandescent
lamp 24, and a lamp current sensor 26 which operates a switch composed of transistors
205, 202, and 109.
[0030] It is contemplated that the arrangement will be utilized primarily with flashers
operated from a battery-type power supply. The battery supply will vary in output
voltage over a battery life or a charging cycle. To maximize the life of an incandescant
bulb 24, it is necessary to regulate the voltage across the bulb. With battery operation
it is also necessary to minimize the losses in the regulator circuits to maintain
proper operation as the battery voltage drops to a value lower than normal. This has
been accomplished in the past by using germanium power transistors for switching and
regulating the current through the incandescent lamp. Although the drop across the
main switching transistor could be held to about 0.5 to 0.6 volts with germanium transistors,
these devices have a high leakage current which increases at higher temperatures.
In my regulator 90, however, I have used a silicon power transistor 92 as the main
switching and regulating element. Advantageously, for low battery voltage, I am able
to maintain the voltage drop across transistor 92 much lower than previously possible
with a silicon transistor switch and regulator. Transistor 92 is driven by transistor
94 which in turn is driven by transistor 96. When main transistor 92 is cut off, the
collectors of transistors 94 and 96 are connected to the collector of transistor 92
by diode 93 to form a darlington circuit. The collectors of transistors 94 and 96
are connected via bypass resistor 95 to the negative side of the power source which
is considered ground in the circuit of Figure 4. A differential amplifier 98 and 99
is connected in a regulator circuit with voltage reference zener 97 and is used to
regulate the collector voltage of transistor 92. When lamp 24 is first turned on,
drive current will pass through the emitter-base junction of transistor 92, through
transistors 94 and 96, through diode 93 and also through the load. However, as the
collector voltage of transistor 92 rises, diode 93 will become reverse biased and
the drive current will therefore pass through bypass resistor 95 to the ground. Thus,
the circuit automatically switches from a darlington circuit to a single transistor
circuit driven by another transistor where the drive current is now not part of the
load current. With transistor 92 conduction, incandescent lamp filament 24 will draw
a heavy current when first energized and will increase in resistance as the filament
heats up reducing the drive and load current required. The resulting collector voltage
and consequently the voltage across lamp 24 will be determined by zener 97 and the
setting of resistor 201 in the regulator circuit formed by transistors 98, 99. When
the currents through transistors 94 and 96 flow through bypass resistor 95, the minimum
voltage drop between the emitter and collector of transistor 92 is not limited by
the collector-to emitter voltages of transistors 94 and 96. When the input voltage
drops below the desired regulated output voltage in the usual darlington regulator
circuit, the minimum voltage drop across the transistor 92 would approach a value
determined by the voltage drops across transistors 94 and 96 when the input voltage
drops below the desired regulated outputvoltage. When the supply voltage is greater
than the desired regulated output voltage, the voltage divider formed by resistors
205 and 103 will produce a voltage across zener 97 greater than its zener voltage
causing it to conduct. Thus, the base of differential amplifier transistor 98 will
be held constant at the reference voltage provided by zener 97. The voltage at the
base of transistor 99 will be determined by the voltage divider formed by resistors
197 and 201 from the regulated lamp voltage. The ratio of resistors 197, 201 is adjusted
to provide only that current through transistors 94 and 96 which will provide the
desired maximum output voltage at the collector of transistor 92.
[0031] When the supply voltage to the emitter of switch transistor 92 approaches or drops
below the desired value of the regulated output voltage, the voltage at the base of
transistor 98 will drop below the breakdown voltage of zener 97 to a value determined
by the ratio of voltage divider 205, 103. The base voltage of transistor 99 is determined
by the ratio of voltage divider 197, 201. The ratio of resistors 205, 103 is adjusted
so as to produce a low predetermined emitter to collector voltage drop across switch
transistor 92. This voltage, however, is higher than the drop would be if transistors
98,96 and 94 were fully on. The addition of resistor 103 to form divider 205, 103
when zener 97 is non-conducting therefore permits limitation of transistor 92 drive
current to that current required to maintain the desired minimum voltage drop across
transistor 92 at any given load current.
[0032] In an alternative arrangement of the circuit of Figure 4 in which it is only required
that transistor 92 switch the load off and on without regulation of the load voltage,
zener diode 97 may be omitted and the voltage across switch transistor 92 maintained
at a very low value over a wide range of supply voltages. In this case, resistor 103
prevents saturation of transistors 98, 96 and 94. Without resistor 103, the drive
current for transistor 92 would be limited only by the value of resistors 95 and 211.
In such case, selecting resistor 95 to supply sufficient drive current for a high
amperage load would result in excessively high drive current for a low amperage load,
representing a waste of energy. With resistor 103, the drive current is dynamically
adjusted to only the amount required to maintain the selected voltage drop across
transistor 92 for any instantaneous or steady-state value of load current and the
drive current can be maintained as a small percentage of the load current for maximum
efficiency.
[0033] As may now be recognized, the novel voltage dividers associated with differential
amplifier 98, 99 and drivers 94, 96 permit the voltage drop across switch transistor
92 to approach saturation but without excessive drive current at any given lamp load
current.
[0034] As an example of a specific operation of my novel regulator 90, assume that the input
voltage may vary between 13 and 18 volts and that an output of 12 volts is desired.
With the input voltage in the range of 13 to 18 volts and resistor 103 omitted, the
first step is to adjust resistor 201 to give an output voltage of 12 volts. Next,
the input voltage is reduced below 12 volts to, for example, 11 volts. Resistor 103
is then inserted and adjusted to give the desired voltage drop from the emitterto
the collector of transistor 92 at the highest lamp load for which the unit is designed.
[0035] As may be recognized, the voltage drop across bypass resistor 95 will decrease if
the lamp filament fails and this voltage can thus be used for sensing such failures.
A sensing resistor in series with lamp 24 is therefore not necessary and the power
loss such a resistor would cause is eliminated. Accordingly, the voltage across bypass
resistor 95 produced by the drive current is sensed by comparator 195. If lamp 24
fails, comaprator 195 controls transistor switch 202 which in turn causes switching
transistors 204 and 109 to conduct to energize an automatic lamp changer which operates
to remove failed lamp 24 and to insert a new lamp.
[0036] Regulator 80, which supplies regulated power to the timing circuits of my invention
and also to comparator 195, is a simple voltage regulator utilizing transistor 206,
zener 208 and resistor 108.
[0037] The preferred embodiment of the electronic flash control circuits and timing circuits
for my invention is shown in schematic form in Figure 5, although it will be understood
that other circuits to provide the desired functions will be obvious to those of skill
in the art. The operation of the circuits illustrated will be explained with reference
also to the diagrams in Figure 6 of waveforms at various points in the circuits. As
previously discussed in reference to Figure 2, my invention can provide up to 10 flash
periods with the counter shown to permit a variety of coded signals to be flashed,
and, by selection of the values of capacitor 68 and resistors 60, 62, 64 and 66, the
durations of the flashes and eclipses can be controlled. It is to be understood that
larger counters may be used to provide greater than 10 flash period. For the circuits
of Figure 5, six periods (N=6) have been selected for illustrative purposes with counter
50 connected to produce the coded flash sequence indicated on line T of Figure 6.
The sequence of two dashes, two dots and two dashes is also, of course, an arbitrary
code for illustration. A short eclipse space is provided between successive code elements
with a long eclipse at the end of the code. As will be recognized, Figure 6 shows
two complete cycles of the code. It may be noted in Figure 5, that counter 40 has
it counter outputs ZERO and ONE connected to two inputs of quad NOR gate 146 to produce
the two long flashes at the beginning of the code and counter outputs FOUR and FIVE
are connected to the other two inputs to produce the two long flashes at the end of
the code. Quad NOR gate 148 has one input connected to count output FIVE to provide
the long eclipse at the end of the code. The remainder of its inputs are grounded
as previously discussed.
[0038] Flip-flops 101 and 102 are keytiming elements in the circuit. As shown on lines G
& H of Figure 6, flip-flops 101 and 102 are interconnected to cause flip-flop 101
to produce equal length HIGH and LOW pulses at its 0 output for each HIGH or LOW output
pulse from the 0 output of flip-flop 102. For example, when flip-flop 102 produces
a long duration HIGH 170, flip-flop 101 produces HIGH 171 followed by LOW 172 with
each being half the duration of HIGH 170. Thus, flip-flop 102 changes state once for
each two changes of state offlip-flop 101. The clock and timing generator shown generally
at 34 places the sequence of timing pulses as indicated on line F, on lead 35 which
clocks flip-flop 101 and inputs to several gates. The output levels on Q
1, Q
1, Q
2, Q
2 are utilized to control various gates in the lamp control circuits.
[0039] A starting sequence for the flash control system may be illustrated by assuming that
the circuits are in the condition indicated by the "start" arrow on line F of Figure
6, with the timing pulse lead 35 HIGH, Q
1 and Q
2 LOW, and lamp OFF. Counter 40 will begin its sixth count. As counter 40 completes
its sixth count which appears at output 5, the counter 40, as will be shown, will
step to its N + 1 or seventh count which appears at output 6 and is connected via
OR gate 132 to the reset input of counter 40. The reset pulse to counter 40 also resets
both flip-flop 101 and 102. At this point, Q
1 and G
2 are both LOW. When a negative-going timing pulse appears on lead 35 from timing generator
34, all inputs to NOR gate 110 will be LOW producing a HIGH at its output. OR gate
126 output will then be HIGH, producing a HIGH signal at one input of NOR gate 112
and of NOR gate 114. NOR gate 114 will produce a LOW at one input of OR gate 125 which
has a LOW on its other input from NOR gate 112. Thus, the LOW produced atthe output
of OR gate 124 turns off transistor 141.
[0040] The collector of transistor 141 connects the input X of Figure 4 which controls lamp
switching transistor 92 via transistors 98 and 99. When transistor 141 is conducting,
point X is LOW cutting off the current to lamp 24. Thus, when OR gate 124turns off
transistor 141, the lamp switch is enabled and turns the lamp 24 on. The action of
START timing pulse 174 in going LOW also places a HIGH from the output of NOR gate
110 on one input of NOR gate 120. Both Q
1 and Q
2 are then HIGH producing a HIGH at the input of NOR gate 118 which has a LOW input
from lead 35. Thus, NOR gate 120 produces a LOW output, turning transistor 125 on,
causing its collector and sync output lead 37 to go HIGH. This produces the leading
edge of sync pulse 178 on line S of Figure 6. It may be noted that sync pulse 178
occurs at essentially the same time as START timing pulse 174. When START timing pulse
174 goes positive (trailing edge), flip-flops 101 and 102 are clocked producing pulses
171 and 170 at Q
1 and Q
2 shown on lines G and H. The output of NOR gate 110 then goes LOW causing the output
of NOR gate 102 to be HIGH. Transistor 125 is thus turned off and lead 37 goes LOW.
The action just described therefore produces sync pulse 178 on lead 37. When transistor
125 turns on, transistor 121 also turns on and transistor 123 turns off.
[0041] Prior to START timing pulse 174, transistor 123 was on, charging capacitor 145. When
the first sync pulse 178 occurs, one input of AND gate 136 goes HIGH with the other
input being HIGH from the charge on capacitor 145. Therefore a HIGH appears at the
output of AND gate 136. Resistor 143 is selected to discharge capacitor 145 to inhibit
AND gate 136 before the end of the sync pulse 178. This action results in sync pulses
178 and 180 being duplicated on lead 161 but of shorter duration to prevent lead 161
from remaining HIGH which would cause a lock-on condition at the reset input of transistor
139. Flip-flip 101 and 102 are set by the short set pulses 182 (line J of Figure 6)
and are reset by short pulses 183 through gate 132 which also resets counter 40. The
short pulse 183 on lead 161 to AND gate 138 is also conducted to the base of transistor
139 of clock and timing generator 34, resetting the generator. AND gate 106 has both
inputs HIGH; therefore, the reset pulse is propagated to reset counter 40.
[0042] It may be noted that the output of NOR gate 118 goes HIGH during the timing pulse
176 which occurs at the middle of each flash in the flash sequence. When the ZERO
counter output shown on line M is present, timing pulse 176 produces second sync pulse
180 on line S of Figure 6. This pulse is therefore propagated through NOR gate 120
to cause the signal on sync output line 37 to go HIGH. Inverter 130 whose output is
connected to one input of AND gate 128 serves to inhibit a reset pulse which might
occur from a distant unit during the last count of counter 40 if the last flash were
a long one. Second sync pulse 180, which appears on sync output 37, will be trnasmitted
to all other flasher systems in the network, and will reset each of the counters in
the other flasher systems connected to sync line 37 through their corresponding gates
136,138,106,128 and 132. If all of the flasher systems in a group were not synchronized,
the first flasher system to reach the ZERO count will cause generation of the sync
pulse 180 and will reset all of the others except any which happen to be on the last
count. However, when such a unit goes to its ZERO count, the sync pulse generated
will in turn reset and therefore resynchronize all of the other units to that unit.
[0043] From the description above of the turn on sequence of the lamp, it will be seen that
turn off of the lamp is controlled by a LOW input to NOR gate 114 which places a HIGH
input on OR gate 124 turning on transistor 141. Transistor 141, when conducting, places
a LOW on the X input to the lamp switching circuits of Figure 4 causing the lamp to
be turned off. NOR gate 112 acts as a latch to hold transistor 141 on until the next
turn on signal occurs. During a turn on pulse, a HIGH signal from the output of AND
gate 104 sets flip-flops 101 and 102 causing 0
1 and Q
2 to go LOW. - During an eclipse, transistor 105 is conducting and charges capacitor
107 permitting a sync signal on AND gate 104 to produce a HIGH at the output for setting
of flip-flops 101 and 102. Transistor 105 turns OFF, permitting discharge of capacitor
107 which inhibits AND gate 104. The set pulse is thus shortened and cannot appear
again during a flash period since the capacitor will remain discharged. It may be
noted that during synchronization, both the sync pulse and the counter reset pulse
from the output of AND gate 138 will also appear at transistor 139 in the clock and
timing generator causing it to reset as will be discussed below.
[0044] The next timing pulse 176 will occur while 0:1 and Q
2 are both HIGH as shown by pulse 171 and 170 in Figure 6. Lead 35 to one input of
NOR gate 118 will go LOW. The ZERO output of counter 40, as seen on line M of Figure
6, will be HIGH and inverter 122 will cause a second input to NOR gate 118 to go LOW.
Q
1 and Q
2 outputs are LOW, causing a LOW from the output of OR gate 116 to the third input
of NOR gate 118. Thus, its output is HIGH to one input of NOR gate 120 whose other
input is held LOW by NOR gate 110. The output of NOR gate 120 then goes LOW turning
on transistor 125 to produce the HIGH sync pulse on output lead 37 as previously described.
At the end of timing pulse 176, the input to NOR gate 118 goes HIGH causing sync output
line 37 to go LOW. It is to be noted that the enabling of the sync pulse by means
of NOR gate 118 requires that the input from counter 40 via inverter 122 produce a
LOW on that input to NOR gate 118. This can only happen during the ZERO count and
therefore no sync pulses appear during the rest of the cycle. The reset pulse produced
on lead 161 during the second sync pulse 180 during the ZERO count will again reset
clock and timing generator 34 and will also be passed through AND gate 106, AND gate
128, and OR gate 132 to the reset terminals of flip-flops 101 and 102. As may now
be recognized, sync pulses 178 and 180 on sync output 37 will appear at all of the
other interconnected flash lamp systems. An incoming sync pulse will be conducted
via the unit's own gates 136 and 138 to its clock and timing generator, resetting
the same and, via gates 106, 128 and 132, resetting the counter. This will start that
unit in synchronism with the transmitting unit to provide the desired simultaneous
flashing among all units in the system. On line L in Figure 6, a series of inhibit
pulses are shown. These negative going pulses are produced by gate 140 during the
last half of each flash period to inhibit gate 138 which prevents the unit from resetting
on an incoming sync pulse arriving during such time.
[0045] Turning now to the circuits of the clock and timing generator shown generally at
34 in Figure 5 and with reference to line F on Figure 6, its operation will be described.
Timing generator 34 utilizes transistor 137 and transistor 139. The base of transistor
137 is held at a fixed bias voltage by the voltage divider formed by resistor 43 and
variable resistor 47. Variable resistor 47 may be adjusted to provide the desired
bias. Transistor 139 is non-conducting during the period between timing pulses such
as START pulse 174 and pulse 176 of Figure 6 thereby producing a HIGH output . on
lead 35. When transistor 139 conducts, its collector voltage drops producing a LOW
on lead 35 during a timing pulse. Immediately after a timing pulse, one of the bilateral
switches 52, 58, 44 or 46 is closed by the selected gating circuits causing capacitor
68 (C
1) to begin to charge through the selected resistor. Using timing pulse 176 of Figure
6 as an example, switch 52 is closed connecting resistor 64 to the +V regulated power
supply, charging capacitor 68. When the voltage on capacitor 68 rises sufficiently
to overcome the bias on the base of transistor 137, that transistor will conduct placing
a HIGH on the base of transistor 139 whose collector then goes LOW as described above.
The charge on capacitor 68 will be dumped by diode 149 with diode 147 serving to hold
the output of resistor 64 LOW to prevent recharge of capacitor 68 during the timing
pulse period. When the charge is quickly removed from capacitor 68, the LOW at the
collector of transistor 139, in a regenerative fashion, cuts off transistor 137 permitting
capaciutor 68 to recharge through resistor 64 connected to capacitor 68 by switch
52. It is to be noted that switch 52 has been held ON by the ZERO count output from
counter 40 as shown on line M of Figure 6 and is therefore still conducting. Diode
147, as noted, prevents recharging of capacitor 68 during the timing pulse 176 which
occurs at the center of a flash or an eclipse. As may also now be seen, a reset pulse
from AND gate 138 to the base of transistor 139 will cause transistor 139 to conduct
producing a timing pulse and starting a new timing cycle.
[0046] Bilateral switches 52, 58, 44, and 48, which may be elements of a quad switch 160,
are closed by their respective AND gates 152, 154, 156 and 158. When a short flash
is required, such as 184 on line T of Figure 6, during count TWO of counter 40, START
timing pulse 185 -clocks flip-flops 101 and 102 causing HIGH 186 at Q
2. This HIGH appears at one input of AND gate 156 which has a HIGH on its other input
from OR gate 146 whose inputs are all LOW. Thus, a HIGH at the output of 156 turns
on gate 44 for the period that Q
2 remains HIGH. When STOP timing pulse 187 occurs, flip-flop 102 is clocked by flip-flop
101 producing the LOW at d
2 shown at 189 in Figure 6. Short eclipse 188 on line T is next required and is accomplished
by the HIGH from Q
2 appearing at one input of AND gate 158 with the other input being HIGH from the output
of NOR gate 148. Switch 48 is therefore closed connecting resistor 62 to charge capacitor
68. Since resistors 60 and 62 in this instance have equal values, the charging times
will be the same as for the short flash and therefore transistor 141 will be controlled
to maintain the lamp off during eclipse 188 for the same time period as flash 184.
It is to be emphasized that it is not necessary that the short flash and short eclipse
have the same duration. For example, resistor 60 may be selected to produce a short
flash of 0.3 seconds and resistor 62 selected to produce a short eclipse of 0.7 seconds.
[0047] The long flashes and long eclipses are controlled by switches 52 and 58, respectively,
with gates 152 and 154 maintained inhibited during short flashes and eclipses by the
inverting action of inverter 144 and NOR gate 150. When a long flash is required,
such as at count ONE, the count pulse 190 on line N of Figure 6 is applied to one
input of NOR gate 146 producing a LOW at its output which via inverter 144, places
a HIGH on one input of AND gate 152. The other input receives a HIGH from Q
2 turning on switch 52. Similarly, a long eclipse is obtained by a HIGH on NOR gate
148 which in this case would occur at count FIVE, 191 on line R of Figure 6. The basic
pulse generating and timing circuit described above as applied to the present invention
has been disclosed in my United States Patent No. 3,596,113 and is incorporated herein
by reference.
[0048] NOR gate 150 between NOR gate 148 and AND gate 154 is advantageously utilized in
the daylight control circuit shown generally at 70 to disable the flashing system
during daylight hours and to start the system during night time or heavily overcast
conditions. During the day when sufficient light falls on photocell 72 to make the
minus input of comparator 162 lower than the plus input, its output will become HIGH,
causing the output of NOR gate 150 to be LOW, inhibiting AND gate 154. However, the
above action will take place only when AND gate 164 is enabled by Q, and Q
2 being high simultaneously. As evident from Figure 6, this condition occurs only during
the last half of each eclipse. Thus, when the sequence reaches the second half of
the next long eclipse, AND gate 154 is disabled, capacitor 68 will discharge, turning
transistor 137 on. Capacitor 68 cannot recharge since switch 58 remains open until
comparator 162 changes state again. Therefore, the clock and timing lead 35 will remain
HIGH and the flashing sequence will stop. When the light on photocell 72 drops low
enough to cause the voltages at the input of comparator 162 to change so as to put
a LOW at its output when AND gate 164 is enabled by HIGHS on Q, and Q
2, this action will enable OR gate 150 to permit capacitor 68 to recharge. AND gate
164 is disabled by a LOW on Q, of flip-flop 101 during the first half of each eclipse,
disabling comparator 162. This action prevents the flow from the filament of lamp
24 during nigressence from causing shut down of the flash system.
[0049] It will be understood that many modifications may be made to the system as described;
for example, it is contemplated that the circuits shown herein may be implemented
in LSI thereby reducing the size and cost.
1. Apparatus for producing a preselected sequence of flashes and eclipses from a lamp
(24) comprising:
lamp control means (22) connected to said lamp (24) for energizing said lamp during
a flash period;
timing generator means (34) connected to said lamp control means for producing a start
timing pulse for starting a flash period and a stop timing pulse for terminating a
flash period;
flash period control means (42, 44, 50, 52) connected to said timing generator means
(34) for controlling the time between said start timing pulse and said stop timing
pulse, said flash period control (42, 44, 50, 52) means having a short flash control
input and a long flash control input;
eclipse period control means (46, 48, 54, 58) connected to said timing generator means
(34) for controlling the time between said stop timing pulse and said start timing
pulse, said eclipse period control means having a short eclipse control input (46)
and a long eclipse control input (54); and
counter means (40) having a set of sequential count outputs, the number of said count
outputs selected to be equal to the number of flashes in said preselected sequence,
each of said count outputs connected to selected ones of said flash and eclipse control
inputs (42, 46, 50, 54) for controlling said flash period and said eclipse period
to produce the durations of the flash and the eclipse preselected for each position
in said preselected sequence, said counter means (40) having its clocking input connected
to said timing generator means (34) for receiving each of said start timing pulses
to cause each count output to have a duration equal to the time between its clocking
start timing pulse and the next clocking start timing pulse.
2. Apparatus according to claim 1 which further comprises synchronization pulse generation
means (36) connected to said lamp control means (22) and having a synchronization
output/input terminal (37), said synchronization pulse generation means (36) controlled
to produce at said output terminal a short first synchronization pulse at the beginning
of each flash period in said sequence.
3. Apparatus according to claim 2 in which said synchronization pulse generation means
(36) produces a short second synchronization pulse at said synchronization output
only during the zero count of said counter (40).
4. Apparatus according to claim 2 in which said lamp control means (22), is adapted
to energize said lamp (24) responsive to an external first synchronization pulse received
at said syn-- chronization output-input terminal.
5. Apparatus according to claim 4 in which said counter means (40) is adapted to reset
to its zero count responsive to an external second synchronization pulse received
at said synchronization output/input terminal during a flash.
6. Apparatus according to claim 1 in which said flash period control means and said
eclipse period control means include:
a set of short flash gates (42) connected to said lamp control means (22) and enabled
by said lamp control means when a short flash is required;
a set of short eclipse gates (46) connected to said lamp control means, and enabled
by said lamp control means when a short eclipse is required;
a set of long flash gates (50) connected to said lamp control means and to said counter
means, and enabled by said lamp control means and said counter means when a long flash
is required;
a set of long eclipse gates (54) connected to said lamp control means and said counter
means, and enabled by said lamp control means and said counter means when a long eclipse
is required;
a set of electronic switch means (44, 48, 52, 58) having switches connected respectively
to said short flash gates, said short eclipse gates, said long flash gates, and said
long eclipse gates; and
a series resistance (60, 62, 64, 66) capacitance timing circuit having the capacitance
(68) thereof connected to all of said electronic switch means (44, 48, 52, 58) and
in which said resistance is a separate resistor (60, 62, 64) connected to each of
said electronic switch means whereby enabling of one of said gates causes the associated
one of said electronic switches to close to thereby connect the one of said resistors
associated with said closed gate in series with said capacitance to establish a selected
long or short duration.
7. Apparatus according to claim 6 which further comprises:
daylight control means (70, 72) responsive to incident ambient light for disabling
said timing generator means (34) when said incident light is greater than a preselected
level, said daylight control means (70, 72) responsive to incident ambient light for
enabling said counter means (40) when said incident light falls below such preselected
level.
8. Apparatus according to claim 7 in which said daylight control means includes:
photocell means (72) adapted to receive incident ambient light; and
comparator means (162) connected to said photocell means (72) for comparing the output
from said photocell means to a preestablished threshold.
9. Apparatus according to claim 7 in which said daylight control means further includes
gating means (164) connected to said timing generator means (34) for inhibiting the
operation of said comparator means (162) during nigressence of said lamp.
10. A system of flashing beacons for buoys and the like having a plurality of spaced
apart flasher units interconnected by communication links (39), said beacons producing
a preselected sequence of flashes and eclipses representative of an identification
code or the like and in which all beacons flash in synchronism, comprising:
lamp means (24) at each of said flasher units;
flash and eclipse period generation means (22) in each of said flasher units for producing
a set of lamp control pulses, said set of lamp control pulses defining the preselected
sequence, said pulses energizing said lamp means (24) during the flash period of said
set;
synchronization pulse generation means (36) for producing a synchronization pulse
at each of said flasher units at the beginning of each flash period;
output means (37) connected to said sync pulse generation means (36) for transmitting
said synchronization pulses from each of said flasher units to all other of said flasher
units; and
synchronizing means (40) in each of said flasher units for resetting said flash and
eclipse period generation means to the beginning of a set when a synchronizing pulse
is received from another flasher unit by a unit which is out of synchronization.
11. A system according to claim 10, in which said sync pulse generation means (36)
produces a first synchronizing pulse at the beginning of each flash and a second synchronizing
pulse following said first synchronizing pulse only during the first flash in said
set and in which said synchronizing means is responsive only to said second synchronizing
pulse.
12. A system according to claim 11, which further comprises:
photo sensitive means (72) for producing a sequence inhibiting control signal in response
to daylight incident thereon;
and wherein said flash and eclipse period generation means (22) is responsive to said
control signal to cease producing said lamp control pulses.
13. A system according to claim 12, in which said flash and eclipse period generation
means (22) is responsive to said control signal only when said synchronization pulses
are not being received from other flasher units in said system.
14. A system according to claim 12 in which said photo sensitive means includes control
means (150) for producing said lamp control pulses in the absence of daylight incident
thereon, said control means including inhibit means (164) for preventing production
of said sequence inhibiting control signal during the nigressence of said lamp.
15. A system according to claim 11 in which each of said flasher units is operable
independently of the other flasher units in said system whereby said units are unaffected
by failure of said communication links.
16. Apparatus according to claim 1 in which said flash period control means includes
a set of short flash gates (42) connected to said lamp control means and enabled by
said lamp control means when a short flash is required, said short flash gates having
a short flash control input and a set of long flash gates (50) connected to said lamp
control means and enabled by said lamp control means when a long flash is required,
said long flash gates having a long flash control input; said eclipse period control
means includes a set of short eclipse gates (46) connected to said lamp control means,
and enabled by said lamp control means when a short eclipse is required, said short
eclipse gates having a short eclipse control input and a set of long eclipse gates
(54) connected to said lamp control means and enabled by said lamp control means when
a long eclipse is required, said long eclipse gates having a long eclipse control
input; said counter means includes its clocking input connected to said timing generator
means for receiving each of said start timing pulses to cause each count output to
have a duration equal to the time between its clocking start timing pulse and the
next clocking start timing pulse; and further comprising:
a set of electronic switch means (44, 48, 52, 58) having switches connected respectively
to the outputs of said short flash gates, said short eclipse gates, said long flash
gates, and said long eclipse gates; and
a series resistance-capacitance timing circuit having the capacitance (68) thereof
connected to all of said electronic switch means, and in which the resistance thereof
is a separate resistor (60, 62, 64, 66) connected to each of said electronic switch
means whereby enabling of one of said gates causes the associated one of said electronic
switches to close to thereby connect the one of said resistors associated with said
closed gate in series with said capacitance to establish a selected long or short
duration.
17. A system of flashing beacons for buoys and the like according to claim 10 in which:
said synchronization pulse generation means (37) for producing a first synchronizing
pulse at the beginning of each flash includes means for generating a pulse following
said first synchronizing pulse occurring only during the first pulse in said set,
and
said synchronizing means (40) in each of said flasher units for resetting its said
flash and eclipse period generation means to the beginning of a set when synchronizing
pulses are received from another flasher unit by a unit which is out of synchronization
is responsive only to said second synchronizing pulse.
1. Vorrichtung zum Erzeugen einer vorgewählten Folge von Blitzen und Dunkelzeiten
von einer Lampe (24) mit:
Lampensteuermitteln (22), welche mit der Lampe (24) für die Energiezufuhr der Lampe
während einer Blitzperiode verbunden sind;
Zeitgebermitteln (34), welche mit dem Lampensteuermittel zum Erzeugen eines Startzeitpulses
für den Beginn einer Blitzperiode und eines Stoppzeitpulses für das Beenden einer
Blitzperiode verbunden sind;
Blitzdauersteuermitteln (42, 44, 50, 52), welche mit den Zeitgebermitteln (34) zum
Steuern der Zeit zwischen dem Startzeitpuls und dem Stoppzeitpuls verbunden sind,
wobei die Blitzdauer-Steuermittel (42, 44, 50, 52) einen Kurzblitzsteuereingang und
einen Langblitzsteuereingang haben;
Dunkelzeitdauer-Steuermitteln (46, 48, 54, 58), welche mit dem Zeitgebermittel (34)
verbunden sind zur Steuerung der Zeit zwischen einem Stoppzeitpuls und einem Startzeitpuls,
wobei die Dunkelzeitdauer-Steuermittel einen Kurzdunkelzeit-Steuereingang (46) und
einen Langdunkelzeit-Steuereingang (54) haben; und
Zählermitteln (40), welche einen Satz von aufeinanderfolgenden Zählerausgängen haben,
wobei die Anzahl der Zählerausgänge gleich der Anzahl von Blitzen in der vorgewählten
Folge ausgewählt werden, jeder der Zählerausgänge mit einem der ausgewählten Blitz-
und Dunkelzeit-Steuereingänge (42, 46, 50, 54) verbunden sind zur Steuerung der Blitzdauer
und der Dunkelzeitdauer, um die Zeitdauer des Blitzes und der Dunkelzeit herzustellen,
welche für jede Position in der ausgewählten Folge vorgewählt ist, wobei das Zählermittel
(40) mit seinem Zeitgebereingang mit dem Zeitgeneratormittel (34) verbunden ist zur
Aufnahme jedes der Startzeitpulse, um jeden Zählerausgang(swert) zu veranlassen, daß
er eine Dauer hat, welche gleich der Zeit zwischen seinem Taktstartzeitpuls und dem
nächsten Taktstartzeitpuls ist.
-2. Vorrichtung nach Anspruch 1, welche weiterhin ein Synchronisierungspuls-Erzeugungsmittel
(36) aufweist, welches mit dem Lampensteuermittel (22) verbunden ist und einen Synchronisierungsausgangsleingangs-Anschluß
(37) hat, wobei das Synchronisierungspuls-Erzeugermittel (36) so gesteuert ist, daß
an dem Ausgangsanschluß ein kurzer erster Synchronisierungspuls zu Beginn jeder Blitzperiode
in der Folge erzeugt wird.
3. Vorrichtung nach Anspruch 2, wobei das Synchronisationspuls-Erzeugungsmittel (36)
einen kurzen zweiten Synchronisierungspuls an dem Synchronisierungsausgang nur während
der Nullzählung des Zählers (40) erzeugt.
4. Vorrichtung nach Anspruch 2, bei welcher das Lampensteuermittel (22) so ausgelegt
ist, daß es die Lampe (24) mit Energie versorgt unter Ansprechen auf einen externen
ersten Synchronisierungspuls, welcher an dem Synchronisationsausgangs/eingangs-Anschluß
empfangen wird.
5. Vorrichtung nach Anspruch 4, bei welcher das Zählermittel (40) so ausgelegt ist,
daß es auf die Zahl Null zurückgebtellt wird unter Ansprechen auf einen externen zweiten
Synchronisierungspuls, welcher an dem Synchronisationsausgangs/eingangs-Anschluß während
eines Blitzes empfangen wird.
6. Vorrichtung nach Anspruch 1, bei welcher das Blitzdauer-Steuermittel und das Dunkelzeitdauer-Steuermittel
aufweisen:
Einen Satz von Kurzblitztoren (42), welche mit dem Lampensteuermittel (22) verbunden
sind und durch das Lampensteuermittel freigegeben werden, wenn ein kurzer Blitz gefordert
ist;
einen Satz von Kurzdunkelzeittoren (46), welche mit dem Lampensteuermittel verbunden
sind und durch das Lampensteuermittel freigegeben werden, wenn eine Kurzdunkelzeit
gefordert ist;
einen Satz von Langblitztoren (50), welche mit dem Lampensteuermittel und dem Zählermittel
verbunden sind und von dem Lampensteuermittel und dem Zählermittel freigegeben werden,
wenn ein langer Blitz gefordert ist;
einen Satz von Langdunkelzeittoren (54), welche mit dem Lampensteuermittel und dem
Zählermittel verbunden sind und durch das Lampensteuermittel und das Zählermittel
freigegeben werden, wenn eine Langdunkelzeit gefordert ist;
einen Satz von elektronischen Schaltermitteln (44, 48, 52, 58), welcher Schalter hat,
die mit den Kurzblitztoren, den Kurzdunkelzeittoren, den Langblitztoren bzw. den Langdunkelzeittoren
verbunden sind; und
einen Reihenwiderstands- (60, 62, 64, 66) Kapazitäts-Zeitschaltkreis, dessen Kapazität
bzw. Kondensator (68) mit allen elektronischen Schaltermitteln (44, 48, 52, 58) verbunden
ist, und in welchem der Widerstand ein getrennter Widerstand (60, 62, 64) ist, welcher
mit jedem der elektronischen Schaltermittel verbunden ist, wodurch die Freigabe eines
der Tore verursacht, daß der zugehörige elektronische Schalter geschlossen wird, um
dadurch den einen der Widerstände, welcher mit dem geschlossenen Tor verknüpft ist,
in Reihe mit dem Kondensator verbindet, um eine ausgewählte lange oder kurze Zeitdauer
festzulegen.
7. Vorrichtung nach Anspruch 6, welche weiterhin aufweist:
Tageslichtüberwachungsmittel (70, 72), welche auf den Einfall von Umgebungslicht ansprechen,
um das Zeitgebermittel (34) unwirksam zu machen, wenn das einfallende Licht über eine
vorgewählte Stärke hinausgeht, wobei das Tageslichtsteuermittel (70, 72) auf aus der
Umgebung einfallendes Licht anspricht, um das Zählermittel (40) unwirksam zu machen,
wenn das einfallende Licht unterhalb einer solchen vorgewählten Stärke liegt.
8. Vorrichtung nach Anspruch 7, bei welcher das Tageslichtsteuermittel aufweist:
Fotozellenmittel (72), welche ausgelegt sind um einfallendes Licht aus der Umgebung
zu empfangen; und
Vergleichs- bzw. Komparatormittel (162), welche an die Fotozellenmittel (72) angeschlossen
sind für den Vergleich des Ausgangs der Fotozellenmittel mit einem vorher festgelegten
Schwellwert.
9. Vorrichtung nach Anspruch 7, wobei das Tageslichtsteuermittel weiterhin ein Tormittel
(164) aufweist, welches mit dem Zeitgebermittel (34) verbunden ist zum Verhindern
des Betriebs des Komparatormittels während der Dunkelheit der Lampe.
10. Anordnung von Blitzleichtfeuern für Bojen und dergleichen, welche eine Vielzahl
von im Abstand angebrachten Blitzeinheiten hat, welche miteinander durch Übermittlungsanschlüsse
(39) verbunden sind, wobei die Leuchtfeuer eine vorgewählte Folge von Blitzen und
Dunkelzeiten produzieren, welche einem Identifizierungscode oder dergleichen entsprechen
und in welchem alle Leuchtfeuer synchron aufblitzen, mit:
Lampenmitteln (24) auf jeder der Blitzeinheiten;
Blitz- und Dunkelzeitdauer-Erzeugungsmitteln (22) in jeder der Blitzeinheiten zum
Erzeugen eines Satzes von Lampensteuerpulsen, wobei der Satz von Lampensteuerpulsen
die vorgewählte Folge bestimmt, und die Pulse die Lampenmittel (24) während der Blitzdauer
des genannten Satzes einschalten;
Synchronisationspuls-Erzeugungsmitteln (36) zum Erzeugen eines Synchronisierungspulses
an jeder der Blitzeinheiten zu Beginn jeder Blitzdauer;
Ausgangsmitteln (37), welche mit dem Synchronisationspuls-Erzeugungsmittel (36) zum
Übertragen der Synchronisierungspulse von jeder der Blitzeinheiten auf alle anderen
Blitzeinheiten verbunden ist; und
Synchronisationsmittel (40) in jeder der Blitzeinheiten zum Zurückstellen der Blitz-
und Dunkelzeitdauer-Erzeugungsmittel zu Beginn eines Satzes, wenn ein Synchronisierungspuls
von einer anderen Blitzeinheit durch eine Einheit empfangen wird, welche nicht synchronisiert
ist.
11. Anordnung nach Anspruch 10, wobei das Synchronisationspuls-Erzeugungsmittel (36)
einen ersten Synchronisierungspuls zu Beginn jedes Blitzes und einen zweiten Synchronisierungspuls,
welcher dem ersten Synchronisierungspuls folgt nur während des ersten Blitzes in dem
Satz erzeugt und wobei das Synchronisationsmittel nur auf den zweiten Synchronisierungspuls
anspricht.
12. Anordnung nach Anspruch 11, welche weiterhin aufweist:
fotoempfindliche Mittel (72) zum Erzeugen einer Folge von Verhinderungssteuersignalen
unter Ansprechen auf darauf einfallendes Licht;
und wobei das Blitz- und Dunkelzeitdauer-Erzeugungsmittel (22) auf das Steuersignal
anspricht, um mit der Erzeugung der Lampensteuerpulse aufzuhören.
13. Anordnung nach Anspruch 12, bei welcher das Blitz- und Dunkelzeitdauer-Erzeugungsmittel
(22) auf das Steuersignal nur ansprucht, wenn die Synchronisierungspulse von der anderen
Blitzeinheiten in dem System nicht empfangen werden.
14. Anordnung nach Anspruch 12, wobei die fotoempfindlichen Mittel ein Steuermittel
(150) aufweisen zum Erzeugen von Lampensteuerpulsen falls kein Tageslicht darauf fällt,
wobei die Steuermittel ein Verhinderungsmittel (164) aufweisen zum Verhindern der
Erzeugung des die Folge verhindernden Steuersignales während der Dunkelzeit der Lampe.
15. Anordnung nach Anspruch 11, bei welcher jede der Blitzeinheiten unabhängig von
anderen Blitzeinheiten in der Anordnung betreibbar ist, wodurch die Einheiten durch
einen Fehler der Anschlußverbindungen nicht beeinflußt werden.
16. Vorrichtung nach Anspruch 1, bei welcher das Blitzdauer-Steuermittel aufweist:
einen Satz von Kurzblitztoren (42), welche mit dem Lampensteuermittel verbunden sind
und durch das Lampensteuermittel freigegeben werden, wenn ein Kurzblitz gefordert
ist, wobei die Kurzblitztore einen Kurzblitz-Steuereingang haben, und einen Satz von
Langblitztoren (50), welche mit dem Lampensteuermittel verbunden sind und durch das
Lampensteuermittel freigegeben werden, wenn ein Langblitz gefordert ist, wobei die
Langblitztore einen Langblitz-Steuereingang haben; weiterhin das Doppelzeitdauer-Steuermittel
einschließt: einen Satz von Kurzdunkelzeittoren (46), welche mit dem Lampensteuermittel
verbunden sind und durch das Lampensteuermittel freigegeben werden, wenn eine Kurzdunkelzeit
gefordert ist, wobei die Kurzdunkelzeittore einen Kurzdunkelzeit-Steuereingang haben,
und einen Satz von Langdunkelzeittoren (54), welche mit dem Lampensteuermittel verbunden
sind und durch das Lampensteuermittel freigegeben werden, wenn eine lange Dunkelzeit
gefordert ist, wobei die Langdunkelzeittore einen Langdunkelzeit-Steuereingang haben;
weiterhin das Zählermittel seinen Takteingang aufweist, welcher mit dem Zeitgebermittel
zum Empfang jedes der Startzeitpulse verbunden ist, um zu bewirken, daß jeder Zählerausgang
eine Zeitdauer hat,
welche gleich der Zeit zwischen seinem Taktstartzeitpuls und dem nächsten Taktstartzeitpuls
liegt; und weiterhin aufweist:
einen Satz von elektronischen Schaltermitteln (44,48,52,58), mit Schaltern, die mit
den Ausgängen der Kurzblitztore, der Kurzdunkelzeittore, der Langblitztore bzw. der
Langdunkelzeittore verbunden sind; und
einen Reihenwiderstands- Kapazitäts-Zeitschaltkreis, dessen Kondensator (68) mit allen
der genannten elektronischen Schaltermittel verbunden ist, und dessen Widerstand ein
getrennter Widerstand (60, 62, 64, 66) ist, welcher mit jedem der elektronischen Schaltermittel
verbunden ist, wodurch die Freigabe von einem der Tore bewirkt, daß der damit verknüpfte
elektronische Schalter geschlossen wird, um dadurch den einen der Widerstände, welcher
mit dem geschlossenen Tor in Reihe mit dem Kondensator verknüpft ist, anzuschließen,
um eine ausgewählte lange oder kurze Zeitdauer festzusetzen.
17. Anordnung von Blitzleuchtfeuern für Bojen und dergleichen gemäß Anspruch 10, bei
welchem:
das Synchronisationspuls-Erzeugungsmittel (37) zum Erzeugen eines ersten Synchronisierungspulses
zu Beginn jedes Blitzes Mittel zum Erzeugen eines Pulses einschließt, welcher dem
ersten Synchronisierungspuls folgt, der nur während des ersten Pulses in dem Satz
auftritt, und wobei
das Synchronisationsmittel (40), welches in jedem der Blitzeinheiten zum Zurückstellen
seines Blitz- und Dunkelzeitdauer-Erzeugungsmittels zu Beginn eines Satzes, wenn Synchronisierungspulse
von einer anderen Blitzeinheit durch eine Einheit empfangen werden, welche nicht synchronisiert
ist, nur auf den zweiten Synchronisierungspuls anspricht.
1. Appareil pour la production d'une séquence présélectée d'éclats et d'éclipses à
partir d'une lampe (24) comprenant:
un moyen de commande de lampe (22) relié à ladite lampe (24) pour l'exciter en période
d'éclat;
un moyen générateur de minutage (34) relié audit moyen de commande de lampe pourfournir
une impulsion de minutage de début afin de faire débuter une période d'éclat et une
impulsion de minutage d'arrêt afin de mettre fin à une période d'éclat;
un moyen de commande de durée d'éclat (42, 44, 50, 52) relié audit moyen générateur
de minutage (34) pour déterminer le temps écoulé entre ladite impulsion de minutage
de début et ladite impulsion de minutage d'arrêt, ledit moyen de commande de durée
d'éclat (42, 44, 50, 52) présentant une entrée de commande 'd'éclat bref et une entrée
de commande d'éclat long;
un moyen de commande de durée d'éclipse (46, 48, 54, 48) relié audit moyen générateur
de minutage (34) pour déterminer le temps écoulé entre ladite impulsion de minutage
d'arrêt et ladite impulsion de minutage de début, ledit moyen de commande de durée
d'éclipse présentant une entrée de commande d'éclipse brève (46) et une entrée de
commande d'éclipse longue (54); et
un moyen compteur (40) présentant un ensemble de sorties de compte séquentielles,
le nombre de ces sorties de compte étant choisi égal au nombre d'éclats de ladite
séquence présélectée, chacune des dites sorties de compte étant reliée à certaines,
sélectionnées, desdites entrées de commande d'éclat et d'éclipse (42, 46, 50, 54)
pour commander ladite durée d'éclat et ladite durée d'éclipse afin de faire apparaître
les durées d'éclat et d'éclipse préselectées pour chaque position dans ladite séquence
présélectée, ledit moyen compteur (40) ayant sont entrée de chronométrage reliée audit
moyen générateur de minutage (34) pour recevoir chacune desdites impulsions de minutage
du début afin de faire que chaque signal de sortie de compte ait une durée égale au
temps écoulé entre son impulsion de minutage de début de chronométrage et l'impulsion
de minutage de début de chronométrage suivante.
2. Appareil selon la revendication 1 qui comprend encore un moyen générateur d'impulsions
de synchronisation (36) relié audit moyen de commande de lampe (22) et comportant
une borne à sortie/entrée de synchronisation (37), ledit moyen générateur d'impulsions
de synchronisation (36) étant commandé pour faire apparaître à ladite borne de sortie
une première impulsion de synchronisation brève au début de chaque période d'éclat
de ladite séquence.
3. Appareil selon la revendication 2 dans lequel ledit moyen générateur d'impulsion
de synchronisation (36) engendre une seconde impulsion de synchronisation brève sur
ladite sortie de synchronisation au cours seulement du compte zéro dudit compteur
(40).
4. Appareil selon la revendication 2 dans lequel ledit moyen de commande de lampe
(22) est propre à exciter ladite lampe (24) en réponse à une première impulsion de
synchronisation externe reçue sur ladite borne de sortie-entrée de synchronisation.
5. Appareil selon la revendication 4 dans lequel ledit moyen compteur (40) est propre
à revenir à son compte zéro en réponse à une seconde impulsion de synchronisation
externe reçue sur ladite borne de sortie/entrée de synchronisation pendant un éclat.
6. Appareil selon la revendication 1 dans lequel ledit moyen de commande de durée
d'éclat et ledit moyen de commande de durée d'éclipse comportent:
un ensemble de portes à éclat bref (42) reliées audit moyen de commande de lampe (22)
et validées par ledit moyen de commande de lampe lorsqu'un éclat bref est requis;
un ensemble de portes à éclipse brève (46) reliées audit moyen de commande de lampe
et validées par ledit moyen de commande de lampe lorsqu'une éclipse brève est requise;
un ensemble de portes à éclat long (50) reliées audit moyen de commande de lampe et
audit moyen compteur, et validées par ledit moyen de commande de lampe et par ledit
moyen compteur lorsqu'un éclat long est requis;
un ensemble de portes à éclipse longue (54) reliées audit moyen de commande de lampe
et audit moyen compteur, et validées par ledit moyen de commande de lampe et par ledit
moyen compteur lorsqu'une éclipse longue est requise;
un ensemble de moyens interrupteurs électroniques (44, 48, 52, 58) comportant des
interrupteurs respectivement reliés aux dites portes à éclat bref, auxdites portes
à éclipse brève, auxdites portes à éclat long et auxdites portes à éclipse longue;
et
un circuit de temporisation à résistances (60, 62, 64, 66) capacité série dont la
capacité (68) est reliée à tous lesdits moyens interrupteurs électroniques (44, 48,
52, 58) et dans lequel ladite résistance est une résistance distincte (60, 62, 64)
reliée à chacun desdits moyens interrupteurs électroniques de sorte que la validation
d'une desdites portes fait que l'interrupteur électronique associée se ferme pour
monter par là celle- desdites résistances qui est associée avec ladite porte fermée
en série avec ladite capacité afin d'établir une durée longue ou brève sélectée.
7. Appareil selon la revendication 6 qui comprend encore:
un moyen de commande de lumière du jour (70, 72) sensible à la lumière ambiante incidente
pour invalider ledit moyen générateur de minutage (34) quand ladite lumière incidente
dépasse un niveau présélecté, ledit moyen de commande de lumière du jour (70, 72)
étant sensible à la lumière ambiante incidente pour valider ledit moyen compteur (40)
quand ladite lumière incidente tombe au-dessous de ce niveau présélecté.
8. Appareil selon la revendication 7 dans lequel ledit moyen de commande de lumière
du jour comporte:
un moyen photoélectrique (72) propre à recevoir la lumière ambiante incidente; et
un moyen comparateur (162) relié audit moyen photoélectrique (72) pour comparer le
signal de sortie dudit moyen photoélectrique à un seuil préétabli.
9. Appareil selon la revendication 7 dans lequel ledit moyen de commande de lumière
du jour comporte encore un moyen formant porte (164) relié audit moyen générateur
de minutage (34) pour empêcher le fonctionnement dudit moyen comparateur (162) pendant
le noircissement de ladite lampe.
10. Système de balises à éclats pour bouées et analogues comportant une série d'éléments
clignotants reliés entre eux par des liaisons de communication (39), lesdites balises
donnant lieu à une série présélectée d'éclats et d'éclipses représentative d'un code
d'identification ou analogue et dans lequel toutes les balises émettent un éclat en
synchronisme, comprenant:
un éiément-lampe (24) à chacun desdits éléments clignotants;
un moyen générateur de durée d'éclat et d'éclipse (22) prévu dans chacun desdits éléments
clignotants pour émettre un ensemble d'impulsions de commande de lampe, ledit ensemble
d'impulsions de commande de lampe définissant la séquence présélectée, lesdites impulsions
excitant ledit élément-lampe (24) pendant la période d'éclat dudit ensemble;
un moyen générateur d'impulsions de synchronisation (36) pour la fourniture d'une
impulsion de synchronisation à chacun desdits éléments clignotants au début de chaque
période d'éclat;
un moyen de sortie (37) relié audit moyen générateur d'impulsions de synchronisation
(36) pour transmettre lesdites impulsions de synchronisation de chacun desdits éléments
clignotants à tous les autres éléments clignotants; et
un moyen de synchronisation (40) prévu dans chacun des dits éléments clignotants pour
ramener ledit moyen générateur de durée d'éclat et d'éclipse au début d'un ensemble
lorsqu'une impulsion de synchronisation est reçue d'un autre élément clignotant par
un élément clignotant qui est désynchronisé.
11. Système selon la revendication 10, dans lequel ledit moyen générateur d'impulsions
de synchronisation (36) engendre une première impulsion de synchronisation au début
de chaque éclat et une seconde impulsion de synchronisation succédant à ladite première
impulsion de synchronisation au cours seulement du premier éclat dudit ensemble et
dans lequel le dit moyen de synchronisation est sensible seulement à ladite seconde
impulsion de synchronisation.
12. Système selon la revendication .11, qui comprend encore:
un moyen photosensible (72) destiné à engendrer un signal de commande d'introduction
de séquence en réponse à la lumière du jour tombant sur lui;
et dans lequel ledit moyen générateur de durée d'éclat et d'éclipse (22) est sensible
audit signal de commande our cesser d'émettre lesdites impulsions de commande de lampe.
13. Système selon la revendication 12, dans lequel ledit moyen générateur de durée
d'éclat et d'éclipse (22) est sensible audit signal de commande seulement quand lesdites
impulsions de synchronisation ne sont pas en cours de réception à partir d'autres
éléments clignotants dudit système.
14. Système selon la revendication 12 dans lequel ledit moyen photosensible comporte
un moyen de commande (150) pour engendrer lesdites impulsions de commande de lampe
en l'absence de lumière du jour tombant sur lui, ledit moyen de commande comportant
un moyen d'interdiction (164) destiné à empêcher la génération dudit signal de commande
d'interdiction de séquence pendant le noircissement de ladite lampe.
15. Système selon la revendication 11 dans lequel chacun desdits éléments clignotants
peut fonctionner indépendamment des autres éléments clignotants dudit système de sorte
que lesdits éléments ne sont pas affectés par une défaillance des dites liaisons de
communication.
16. Appareil selon la revendication 1 dans lequel ledit moyen de commande de durée
d'éclat comporte un ensemble de portes à éclat bref (42) reliées audit moyen de commande
de lampe et validées par lui lorsqu'un éclat bref est requis, lesdites portes à éclat
bref comportant une entrée de commande d'éclat bref et un ensemble de portes à éclat
long (50) reliées audit moyen de commande de lampe et validées par lui lorsqu'un éclat
long est nécessaire, lesdites portes à éclat long comportant une entrée de commande
d'éclat long; ledit moyen de commande de durée d'éclipse comporte un ensemble de portes
à éclipse brève (46) reliées audit moyen de commande de lampe et validées par lui
lorsqu'une éclipse longue est requise, lesdites portes à éclipse courte ayant une
entrée de commande d'éclipse courte et un jeu de portes (54) à éclipse longue reliées
audit moyen de commande de lampe et validées par lui lorsqu'une éclipse longue est
requise, lesdites portes à éclipse longue ayant une entrée de commande d'éclipse longue;
ledit moyen compteur a son entrée de chronométrage reliée audit moyerr générateur
de minutage pour recevoir chacune desdites impulsions de minutage de début afin de
faire que chaque signal de sortie de compte ait une durée égale au temps écoulé entre
son impulsion de minutage de début de chronométrage et l'impulsion de minutage de
début de chronométrage suivante; et comprenant encore:
un ensemble de moyens interrupteurs électroniques (44, 48, 52, 58) comportant des
interrupteurs respectivement reliés aux sorties desdites portes à éclat bref, desdites
portes à éclipse brève, desdites portes à éclat long et desdites portes à éclipse
longue; et
un circuit de minutage à résistance capacité en série dont la capacité (68) est reliée
à tous lesdits moyens interrupteurs électroniques, et dont la résistance est une résistance
distincte (60, 62, 64, 66) reliée à chacun desdits moyens interrupteurs électroniques
de sorte que la validation d'une desdites portes fait que celui qui lui est associé
parmi les interrupteurs électroniques se ferme pour monter par là celle desdites résistances
qui est associée à ladite porte fermée en série avec ladite capacité afin d'établir
une durée longue ou brève sélectée.
17. Système de balises à éclatas pour bouées et analogues selon la revendication 10
dans lequel:
ledit moyen générateur d'impulsions de synchronisation (37) pour la génération d'une
première impulsion de synchronisation au début de chaque éclat comporte un moyen pour
générer une impulsion succédant à ladite première impulsion de synchronisation apparaissant
seulement pendant la première impulsion dudit ensemble, et
ledit moyen de synchronisation (40) de chacun desdits éléments clignotants est sensible
seulement, pour ramener son moyen générateur de durée d'éclat et d'éclipse au début
d'un ensemble lorsque des impulsions de synchronisation sont reçues d'un autre élément
clignotant par un élément désynchronisé, à ladite seconde impulsion de synchronisation.