Ion etching process for deep trench etching multi-layer semiconductor substrates

Description

[0001] This invention relates to ion etching process for deep trench etching multi-layer semiconductor substrates.

[0002] Reactive Ion Etching (RIE) is now a relatively well-known technique which finds wide utility in the fabrication of integrated circuits.

[0003] In the fabrication of semiconductor devices such as bipolar transistors, isolation of individual devices is provided for by an insulator such as silicon dioxide disposed in deep trenches which surround the individual devices. These trenches are usually formed in the semiconductor substrate by reactive ion etching after masking portions of the substrate surface with a material or materials which have etch rates sufficient to permit the trench to be etched to a desired depth. These considerations are well-known and materials such as silicon dioxide and silicon nitride are routinely used as masks. When the substrates being etched are made up of a single semiconductor material which is uniformly doped with the same dopant, the unmasked portions of the substrate may be subjected to reactive ion etching and trenches with uniform sidewalls are easily obtained. However, when the substrate to be etched is characterized by variations in doping which are required to produce a useful transistor device, reactively ion etching such as substrate can result in undercutting or "blooming" in a portion of the substrate which has a different doping level, for example, than that in the regions surrounding the above mentioned substrate portion. This is particularly so when trenches are to be etched in a substrate which contains a heavily doped region of semiconductor material sandwiched between regions of lightly doped semiconductor material and when the width of the trenches is 1.25 microns or less.

[0004] The lateral chemical attack or "blooming" of the heavily doped semiconductor region has been noted in the IBM Technical Disclosure Bulletin, vol. 21, No. 7, December 1978, p. 2814, in an article by P . M. Scharble et al entitled "Reactive Ion etching of Silicn". The lateral attack of the N^+° subcollector layer in the structure of the article was eliminated by cooling the wafers during etching and simultaneously increasing the C1₂ concentration to 20 percent in a Cl₂+argon gas mixture.

[0005] The use of Freon@ mixed with argon, helium or oxygen is well-known in the reactive ion etching art. Indeed, the sequential use of argon and oxygen in combination with CCI₄ has been shown in the IBM Technical Disclosure Bulletin, Vol. 27, No. 10, March 1980 in an article entitled "Chromium as an RIE Etch Barrier" by J. E. Hitchner et al. However, in the article, Ar+CC1₄ is used to attack an aluminum/copper layer while 0₂+CC1₄ is used to etch chromium. Thus, the article doesn't deal with the problem of "blooming" or lateral attack in heavily doped semiconductor layers which ar sandwiched by adjacent layers of lightly doped semiconductor material.

[0006] It is a principal object of this invention to provide a process for reactively ion etching deep trenches in semiconductor materials which have uniform sidewalls.

[0007] It is another object of this invention to provide a reactive ion etching process for semiconductor materials which eliminates lateral etching or "blooming" in semiconductor portions which have different doping levels than other portions.

[0008] Yet another object is to provide a reactive ion etching process in which the use of corrosive atmospheres is eliminated.

[0009] Still another object is to provide a reactive ion etching process which is applicable over a wide range of trench widths including widths of 1.25 microns and below.

[0010] The present invention provides a Reactive Ion Etching (RIE) process which is utilized to etch trenches having uniform sidewalls in semiconductor materials. The process utilizes conventional RIE apparatus and departs from the prior art in that it utilizes two different, noncorrosive gases to eliminate lateral etching or "blooming" in a heavily doped region of semiconductor material which is sandwiched between upper and lower lightly doped regions of semiconductor material. The gases are CC1₂F₂+argon and CC1₂F₂+oxygen. The former is used initially to etch an exposed portion of the upper lightly doped semiconductor substrate to at least a portion of the thickness of the lightly doped region. The latter is used, after evacuating the former, to etch through any remaining thickness of the upper region, through the heavily doped region and into at least a portion of another lightly doped region which lies below the heavily doped region. The process is not limited to any trench width but is particularly applicable to etching trenches having widths of approximately 1.25 microns and less.

[0011] Accordingly the invention provides a method of forming deep trenches with uniform sidewalls in a semiconductor structure wherein said structure includes a heavily doped region sandwiched between upper and lower lightly doped regions comprising the steps of: reactively ion etching said upper lightly doped region in an atmosphere of CCl₂F₂ and argon to at least a portion of the thickness of said upper region, and, subsequently reactively ion etching any remaining thickness of said upper region and said heavily doped region and at least a portion of said lower lightly doped region in an atmosphere CC1₂F₂ and oxygen.

[0012] The invention will now be more particularly described with reference to the accompanying drawings, in which:- FIG. 1 is a partially schematic, cross-sectional drawing or reactive ion etching apparatus which may be utilized in the practice of the process to be described herein.

[0013] FIG. 2 is a cross-sectional view of a masked semiconductor substrate in which a trench has been formed by reactive ion etching.The substrate contains a heavily doped region sandwiched between two less heavily doped regions. Using prior art gas mixtures, such s CCl₂F₂+O₂ or SF₆+CC1₂, lateral etching or "blooming" occurs in the heavily doped region producing a trench with nonuniform sidewalls.

[0014] FIG. 3 is a cross-sectional view of a substrate like that shown in FIG. 2 in which a trench has been formed by reactive ion etching using gas mixtures of CC1₂F₂+argon and CC1₂F₂+oxygen in succession to first etch into an upper lightly doped region to a depth no greater than its thickness and then etch through any remaining thickness of the upper region and through a heavily doped region into at least a portion of a lower lightly doped region. The resulting trench has uniform sidewalls.

[0015] The process to be described in detail herein utilizes standard or conventional Reactive Ion Etching (RIE) apparatus. FIG. 1 shows such apparatus and comprises a vacuum housing 1 which includes a base plate 2 and a bell jar 3 which may be made of glass or metal and is hermetically sealed to base plate 2. A cathode plate 4 is shown disposed within bell jar 3 which is electrically and mechanically connected to a cathode 5.

[0016] In FIG. 1, cathode 5 is preferably a radio frequency electrode which is supported by an electrode support element 6 which passes through base plate 2 via a feedthrough insulator 7. Electrode support element 6 and feedthrough insulator 7 hold cathode 5 in substantially parallel relationship with base plate 2. A shield 8 extending from base plate 2 is spaced from and conformal with cathode plate 4, cathode 5 and electrode support element 6. A plurality of recesses 9 is shown disposed in the surface of cathode plate 4 into which substrates which are to be etched are receivable.

[0017] A perforated anode or catcher plate 10 is shown in FIG. 1 disposed opposite cathode plate 4 and supported at its periphery by a portion of shield 8.

[0018] Perforated anode 10 partially confines the plasma developed during operation to the volume between perforated anode 10 and cathode 5. A diffuse glow, however, still fills the remaining volume of bell jar 3.

[0019] Cathode 5 which is usual made of copper is provided with a fluid conduit 12 for cooling cathode plate 4, if desired. A radio frequency power source 12 which provides power to the RIE system is shown connected between electrode support elements 6 and ground.

[0020] Performated anode or catcher plate 10 in addition to being mechanically connected to shield 8 is electrically at the same potential as shield 8 and is grounded. Anode plate 10 is preferably positioned about one inch away from cathode plate 4. To the extent that there is a tendency for the material of cathode plate 4 to sputter somewhat, anode plate 10 is used to intercept the sputtered material and prevent it from diffusing back onto the surface of the substrate being etched. Such sputtering can occur when cathode plate 4 is made of a metal such as aluminum, stainless steel or copper.

[0021] In FIG. 1, an exhaust pipe 14, which is used for evacuating the space enclosed by bell jar 3, is shown piercing base plate. 2. Exhaust pipe 14 is connected to a vacuum pump (not shown). Bell jar 3 is evacuated prior to subjecting the substrate to be etched to the reactive ion etching process. Base plate 2 is also pierced by a conduit 15 which splits into conduits 16 and 17. Conduits 16, 17 are provided with variable leak valves 18, 19, respectively, and mass flow meters 20, 21, respectively. Each combination of leak valve and flow meter can be replaced by equipment which carries out the functions such as a flow controller. Mass flow meters and controllers are available commercially from Matheson under the trade designation Series 8240 and 8260 Mass Flow Controllers and from Tylan Corporation under the trade designation Model FM-300 and FM-302 Mass Flow Meter and Model FC-200 and FC-202 Mass Flow Controller. Mass flow meters and controllers actually measure molecular flow by volume by unit time such as standard cubic centimeters per minute. Conduit 16 is connected to a gas storage vessel 22 for one of the gases utilized in reactive ion etching while conduit 17 connects to gas storage vessel 23 for the other of the gases utilized.

[0022] In FIG. 1, substrates are normall disposed in recesses 9 in cathode plate 4 such that the surfaces of the substrates are flush with the surface of cathode plate 4.

[0023] Referring now to FIG. 2, there is shown a partial cross-sectional schematic view of a semiconductor wafer or substrate 30 of silicon, for example, in which a heavily doped region or layer 31 of n⁺ conductivity type is sandwiched between lightly doped regions or layers 32, 33 of n-conductivity type. The surface of substrate 30 is covered with a masking layer 34 which may be a single layer of silicon dioxide deposited on the surface of substrate 30 or may be a composite layer of silicon dioxide overlying a layer of silicon nitride. Masking layer 34 may be made of any suitable material provided that it has an etch rate and thickness sufficient to permit etching a trench of desired depth in substrate 30 without removing all of masking layer 34.

[0024] A trench 35 is shown in FIG. 2 which extends through layers 31, 32 and partially into region 33. Using etchant gases like CC1₂F₂+oxygen or SF₆+CCI_Z in the RIE apparatus of FIG. 1, produces lateral etching or "blooming" at region 36 in heavily doped n⁺ layer 31 such that trench 35 has nonuniform sidewalls resulting in an undesirable lower density of devices permitted on a wafer and/or the existence of voids at region 36 when trench 35 is filled with insulating material. Using the prior art gases mentioned above provides relatively uniform sidewalls until the width, w, of the opening in masking layer 34 is required to be approximately 1.25 microns or less. At this point, severe lateral etching occurs in the heavily doped n⁺ layer 31 leading to the undesired density and void problems just mentioned.

[0025] Referring now to FIG. 3, there is shown a partial, cross-sectional schematic view of a semiconductor wafer 30 which is identical in every way with wafer 30 of FIG. 2 except that trench 35 therein has uniform sidewalls and the lateral etching or "blooming" in n⁺ layer 31 has been eliminated.

[0026] Wafer of substrate 30 of FIG. 3 is initially prepared by ion implanting or diffusing an n-conductivity type dopant such as phorous or arsenic into an n-conductivity silicon wafer to form region or layer 31. The doping level (1 x 10¹⁹cm^-3) in layer 31 is such that it is heavily doped characterized as n⁺ conductivity type. Subsequently, layer 32 of lightly doped n-conductivity type (1 x 10¹⁵cm^-3) is epitaxially deposited using well-known techniques over region or layer 31. A masking layer of silicon dioxide 34 is formed on the surface of layer 32 by chemical vapor deposition or regrowth in a well-known way. Using well-known photolithographic masking and etching techniques, a portion of masking layer 34 is removed exposing a surface portion of layer 32 where a trench 35 is to be formed by reactive ion etching.

[0027] Wafer or substrates 30 are then disposed in recesses 9 in cathode plate 4 of the RIE apparatus shown in FIG. 1 and the apparatus is hermetically sealed by pumping down bell jar 3 with a pump (not shown) via exhaust pipe 14. Gas storage vessels 22, 23 which are filled with CC1₂F₂+argon and CC1₂F₂+oxygen, respectively, can now be connected to the interior of vacuum housing 1 under control of valves 18,19 and flow meters 20, 21.

[0028] Assuming that it is desired to reactively ion etch a trench 5 micron deep; that layer 32 is 3 micron thick; that layer 31 is 1 micron thick, that w is approximately 1.25 microns wide and that masking layer 34 is 5 microns thick, the following process steps are carried out:

[0029] In a first step, CC1₂F₂+argon is introduced into vacuum housing 1 and reactive ion etching is carried out under conditions closely approximating the following conditions:

(sccm cubic centimeters per minute of gas flow at specified standard conditions of temperature and pressure)

[0030] Under these conditions, layer 32 is etched approximately 0.5 microns deep.

[0031] In the above step, the gas flow may be in a range of 20-25 sccm) the gas pressure may be in a range of 2.40-3.06 Pa (18-23 microns) and the RIE power may be 100 watts ± 10% and similar results will be obtained.

[0032] In a second step, RIE is discontinued and the CCl₂F₂+argon is evacuated via exhaust pipe 14.

[0033] In a third step, CC1₂F2+oxygen is introduced and RIE is carried out under conditions closely approximating the following conditions:

[0034] Under the above conditions, layer 31 is etched through and a portion of layer 33 is etched. The sidewalls in trench 35 are uniform. In the last step, the gas flow may be in a range of 20-25 sccm. The gas pressure may be in a range of 2.40-3.06 Pa (18-23 microns) and RIE power may be 100 watts ± 10% and similar results will be obtained.

[0035] In connection with the depth of etch of epitaxial layer 32, it should be appreciated that this layer can be etched all the way through, and the lateral etching will be eliminated. However, this is not normally done inasmuch as it is not necessary to achieve the desired result. Preferably, at least a portion of layer 32 is etched. Typically for a 1 micrometer layer, the thickness etched can be 0.4 mm-0.6 mm. Of course, the thicker epitaxial layer 31 is, the greater will be the portion etched but normally is approximately less than half the thickness of layer 32.

[0036] Using the above steps, trenches with uniform sidewalls may be etched in semiconductor wafers. In a usual application, layer 31 is a region known as a subcollector layer and layer 32 is an epitaxial layer in which emitter, base and collector regions of a bipolar device are formed. The teaching of the present application however, is not limited to forming trenches for such specific applications but may be used in any layered structure which contains variations in the doping of the layers or regions.

[0037] While n-conductivity type dopants have been shown in the structure of FIG. 3, it should be appreciated that the process disclosed herein works equally well with p-conductivity type dopants. In addition, layer 33 of FIG. 3 may be p-conductivity type while the other layers or regions are n-conductivity type. Conversely, layer 33 may be n-conductivity type while the other layers are p-conductivity type.

Claims

1. A method of forming deep trenches with uniform sidewalls in a semiconductor structure wherein said structure includes a heavily doped region sandwiched between upper and lower lightly doped regions comprising the steps of:

reactively ion etching said upper lightly doped region in an atmosphere of CC1₂F₂ and argon to at least a portion of the thickness of said upper region, and,

subsequently reactively ion etching any remaining thickness of said upper region and said heavily doped region and at least a portion of said lower lightly doped region in an atmosphere CC1₂F₂ and oxygen.

2. A method according to Claim 1, further including the step of masking the surface of said upper region to provide at least an exposed surface portion prior to reactive ion etching.

3. A method according to Claim 1 or 2 wherein the step of reactive ion etching in an atmosphere of CC1₂F₂ and argon includes the steps of: introducing said atmosphere of CC1₂F₂ and argon into an evacuated reactive ion etching reactor at a pressure in the range of 2.40-3.06 Pa (18-23 microns), at a flow in the range of 20-25 standard cubic centimeters per minute and at a gas ratio (by volume) of CCl₂F₂ to argon of 1, and, applying power in a range of 90-110 watts to said reactor.

4. A method according to Claim 1, 2 or 3, wherein the step of reactively ion etching in an atmosphere of CC1₂F₂ and oxygen includes the step of:

introducing said atmosphere of CCl₂F₂ and oxygen into said evacuated reactive ion etching reactor at a pressure in the range of (2.40-3.06 Pa (18-23 microns), at a flow in the range of 20-25 standard cubic centimeters per minute and at a gas ratio (by volume) of CC1₂F₂ to oxygen of 1, and,

applying power in a range of 90­110 watts to said reactor.

5. A method according to any one of claim 1 to 4, wherein said semiconductor is silicon, said heavily doped region and said upper region are doped with an n- or p-conductivity type dopant and said lower region is doped with a p- or n-conductivity type dopant.

6. A method according to any one of claims 1 to 4, wherein said semiconductor is silicon, said heavily doped region and said upper and lower regions are doped with an n-conductivity type dopant.

7. A method according to Claim 2 wherein the step of masking includes the steps of forming at least a layer of masking material on said surface of said upper region,

forming a layer of photoresist on said at least a layer of masking material and exposing at least a portion of said resist to radiation, and,

developing said photoresist to remove said at least a portion of said layer of photoresist to provide said at least an exposed surface portion.

8. A method according to Claim 7 wherein the step of forming at least a layer of masking material includes the step of depositing a layer of silicon nitride or silicon oxide on said surface of said upper region.

9. A method according to Claim 8 further including the step of depositing a layer of silicon oxide on a layer of silicon nitride.

10. A method of forming deep trenches with uniform sidewalls in a semiconductor structure wherein said structure includes a heavily doped region sandwiched between upper and lower lightly doped regions comprising the steps of: placing at least one of said structures in a reactive ion etching reactor, introducing an atmosphere of CC1₂F₂ and argon into said reactor at a pressure of 2.66 Pa (20 microns), at a flow of 20 standard cubic centimeters per minute and at a gas ratio (by volume) of CC1₂F₂ to argon of 1,

applying power of 100 watts to said reactor, reactively ion etching said upper lightly doped region to a depth up to the thickness of said upper region,

evacuating said reactor,

introducing an atmosphere of CC1₂ and oxygen into said reactor at a pressure of 2.66 Pa (20 microns), at a flow of 20 standard cubic centimeters per minute and at a gas ratio (by volume) of CC1₂F₂ to oxygen of 1, applying power of 100 watts to said reactor, and,

reactively ion etching said heavily doped region and at least a portion of said lower region.

11. A method according to Claim 10 wherein said semiconductor is silicon, said upper region is a layer of epitaxially deposited, n- or p-conductivity type silicon, said lower region is a region of p- or n-conductivity type silicon and said heavily doped region is a region of n- or p-conductivity type silicon.

12. A method according to Claim 10 wherein said semiconductor is silicon, said heavily doped region and said upper and lower regions are all regions of n- or p-conductivity type silicon.

13. A method according to any one of claims 1 to 12, wherein the trench has a width up to 1.25 microns.

Ansprüche

1. Verfahren zur Bildung von tiefen Gräben mit gleichmäßigen Seitenwänden in einer Halbleiterstruktur, wobei die Halbleiterstruktur eingeschichtet einen stark dotierten Bereich zwischen einem oberen und einem unteren schwach dotierten Bereich enthält, gekennzeichnet durch folgende Verfahrensschritte:

reaktives lonenätzen des oberen schwach dotierten Bereichs in einer Atmosphäre von CCl₂F₂ und Argon bis zumindest einem Teil der Dicke des oberen Bereiche, und

anschließendes reaktives lonenätzen der verbleibenden Dicke des oberen Bereichs und des schwach dotierten Bereichs und zumindest eines Teiles des unteren schwach dotierten Bereichs in einer Atmosphäre von CC1₂F₂ und Sauerstoff.

2. Verfahren nach Anspuch 1, dadurch gekennzeichnet, daß als weiterer Verfahrensschritt die Oberfläche des oberen Bereichs mit einer Maske versehen ist, um zumindest einen erhabenen Oberflächenteil vorausgehend einem rekativen lonenätzen auszusetzen.

3. Verfahen nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß der Verfahrensschritt des reaktiven lonenätzens in einer Atmosphäre von CCI₂F₂ und Argon folgende Schritte aufweist:

Einführen der Atmosphäre von CCI₂F₂ und Argon in einen evakuierten lonenätzreaktor bei einem Druck in einem Bereich von 2,40-3,06 Pa (18-23 Mikron), einem Gasfluß im Bereich von 20-25 Standardkubikzentimeter pro Minute und einemGasverhältnis (volumenmäßig) von CCl₂F₂ und Argon von 1, und

Anlegen von Strom in einem Bereich von 90-110 Watt an den Reaktor.

4. Verfahren nach Anspruch 1, 2 oder 3, dadurch gekennzeichnet, daß der Verfahrensschritt des reaktiven lonenätzens in einer Atmosphäre von CCI_ZF₂ und Sauerstoff folgende Schritte aufweist:

Einführen der Atmosphäre von CC1₂F₂ und Sauerstoff in den evakuierten reaktiven lonenätzreaktor bei einem Druck in dem Bereich von 2,40-3,06 Pa (18-23 Mikron), einem Gasfluß in dem Bereich von 20-25 Standardkubikzentimeter pro Minute und einem Gasverhältnis (volumenmäßig) von CCl₂F₂ und Sauerstoff von 1, und

Anlegen von Strom in einem Bereich von 90-110 Watt an den Reaktor.

5. Verfahren nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, daß der Halbleiter Silizium ist, wobei der stark dotierte Bereich und der obere Bereich n- oder p- leitend und der untere Bereich p- oder n-leitend dotiert sind.

6. Verfahren nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, daß der halbleiter Silizium ist und der stark dotierte Bereich und der obere und der untere Bereich n-leitend dotiert sind.

7. Verfahren nach Anspruch 2, dadurch gekennzeichnet, daß zum Maskenabdecken einer Schicht Abdeckmaterial auf der Oberfläche des oberen Bereichs dann eine Schicht von fotoresistentem Material auf dem Schichtabdeckungsmaterial jgebildet wird und daß zumindest ein Teil der fotorresistenten Schicht einer Strahlung ausgesetzt, und die fotoresistente Schicht zur Beseitigung von zumindest einem Teil der fotoresistenten Schicht zur Erlangung von zumindest eines erhabenen Oberflächenteiles entwickelt wird.

8. Verfahren nach Anspruch 7, dadurch gekennzeichnet, daß zur Bildung von zumindest einer Schicht von Abdeckmaterial eine Schicht von Siliziumnitrid oder Siliziumoxid auf die Oberfläche des oberen Bereichs aufgebracht wird.

9. Verfahren nach Anspruch 8, dadurch gekennzeichnet, daß einer Schicht von Siliziumoxid auf eine Schicht von Siliziumnitrid aufgebracht wird.

10. Verfahren zur Bildung von tiefen Gräber mit gleichförmigen Seitenwänden in einer Halbleiterstruktur, wobei die Halbleiterstruktur eingeschichtet einen stark dotierten Bereich zwischen einem oberen und einem unteren schwach dotierten Bereich enthält, gekennzeichnet durch folgende Verfahrensschritte:

Anordnen von zumindest einer der Halbleiterstrukturen in einem reaktiven lonenätzreaktor, Einführen einer Atmosphäre von CC1₂F₂ und Argon in den Reaktor bei einem Druck von 2,66 Pa (20 Mikron), bei einem Gasfluß von 20 Standardcubikzentimeter pro Minute und einem Gasverhältnis (volumenmäßig) von CC1₂F₂ zu Argon von 1,

Anlegen von Strom von 100 Watt an den Reaktor, reaktives lonenätzen des oberen schwach dotierten Bereichs bis zu einer Tiefe entsprechend der Dicke des oberen Bereichs,

Evakuieren des Reaktors,

Einführen einer Atmosphäre von CCI₂F₂ und Sauerstoff in den Reaktor bei einem Druck von 2,66 Pa (20 Mikron) bei einem Gasfluß von 20 Standardcubikzentimeter pro Minute und einem Gasverhältnis (volumenmäßig) von CCl₂F₂ zu Sauerstoff von 1, Anlegen von Strom von 100 Watt an den Reaktor, und

reaktives lonenätzen des Stark dotierten Bereichs und zumindest einem Teil des unteren Bereichs.

11. Verfahren nach Anspruch 10, dadurch gekennzeichnet, daß der Halbleiter Silizium ist, der obere Bereich eine Schicht von epitaxisch aufgebrachtem Silizium vom Typ n- oder p-leitend, der untere Bereich silizium vom Typ p- oder n-leitend und der hochdotierte Bereich silizium vom Typ n- oder p-leitend ist.

12. Verfahren nach Anspruch 10, dadurch gekennzeichnet, daß der Halbleiter Silizium ist, der hochdotierte Bereich und die unteren und oberen Bereiche Silizium vom Typ n- oder p-leitend sind.

13. Verfahren nach einem der Ansprüche 1 bis 12, dadurch gekennzeichnet, daß der Graben eine breite bis zu 1,25 Mikron aufweist.

Revendications

1. Procédé de formation de rainures profondes à parois latérales uniformes dans une structure semiconductrice dans lequel la structure comprend une région fortement dopée prise en sandwich entre des régions supérieure et inférieure faiblement dopées, comprenant les étapes suivantes:

attaquer par gravure ionique réactive la région supérieure légèrement dopée dans une atmosphère de CC1₂F₂ et d'argon sur au moins une partie de l'épaisseur de cette région supérieure, et

attaquer ensuite par gravure ionique réactive toute l'épaisseur restante de la région supérieure et de la région fortement dopée et au moins une partie de la région inférieure faiblement dopée dans une atmosphère de CC1₂F₂ et l'oxygène.

2. Procédé selon la revendication 1, comprenant en outre l'étape consistant à masquer la surface de la région supérieure pour fournir au moins une partie de surface exposée avant la gravure ionique réactive.

3. Procédé selon l'une des revendications 1 ou 2 dans lequel l'étape de gravure ionique réactive dans une atmosphère de CCl₂F₂ et d'argon comprend les étapes suivantes:

introduire ladite atmosphère de CC1₂F₂ et d'argon dans un réacteur de gravure ionique réactive sousvide à une pression dans la gamme de 2,40 à 3,06 Pa (18 à 23 microns), à un débit dans la gamme de 20 à 25 centimètres cube par minute et avec un rapport volumique gazeux entre CC1₂F₂ et l'argon de 1, et
appliquer une puissance dans une gamme de 90 à 110 watts à ce réacteur.

4. Procédé selon l'une des revendications 1, 2 ou 3, dans lequel l'étape de gravure ionique réactive dans une atmosphère de CCI₂F₂ et d'oxygène comprend les étapes suivantes:

introduire l'atmosphère de CCcI₂F₂ et d'oxygène dans le réacteur sousvide de gravure ionique réactive à une pression dans la gamme de 2,40 à 3,06 Pa (18 à 23 microns) avec un débit dans la gamme de 20 à 25 centimètres cube par minute et un rapport volumique de gaz entre CC1₂F₂ et l'oxygène de 1, et

appliquer une puissance dans la gamme de 90 à 110 watts au réacteur.

5. Procédé selon l'une quelconque des revendications 1 à 4, dans lequel le semiconducteur est du silicium, la région fortement dopée et la région supérieure sont dopées avec un dopant de type de conductivité n ou p et la région inférieure est dopée avec un dopant de type de conductivité p ou n.

6. Procédé selon l'une quelconque des revendications 1 à 4, dans lequel le semiconducteur est du silicium, la région fortement dopée et les régions supérieure et inférieure sont dopées par un dopant de type de conductivité n.

7. Procédé selon la revendication 2, dans lequel l'étape de masquage comprend les étapes consistant à:

former au moins une couche de matériau de masquage sur ladite surface de la région supérieure,

former une couche de produit photosensible sur ladite au moins une couche de matériau de masquage et exposer au moins une partie de ce produit photosensible à un rayonnement, et

développer le produit photosensible pour enlever ladite au moins une partie de la couche de produit photosensible pour produire ladite au moins une partie de surface exposée.

8. Procédé selon la revendication 7, dans lequel l'étape de formation d'au moins une couche de matériau de masquage comprend l'étape consistant à déposer une couche de nitrure de silicium ou d'oxyde de silicium sur la surface de la région supérieure.

9. Procédé selon la revendication 8, comprenant en outre l'étape consistant à déposer une couche d'oxyde de silicium sur une couche de nitrure de silicium.

10. Procédé de formation de rainures profondes à parois latérales uniformes dans une structure semiconductrice dans lequel ladite structure comprend une région fortement dopée prise en sandwich entre des régions supérieure et inférieure légérement dopées, comprenant les étapes suivantes:

placer au moins l'une desdites structures dans un réacteur de gravure ionique réactive, introduire une atmosphère de CCI_ZF_Z et d'argon dans le réacteur à une pression de 2,66 Pa (20 microns) selon un débit de 20 centimètres cube par minute et un rapport volumique gazeux de CC1₂F₂ à argon de 1,

appliquer une puissance de 100 watts au réacteur, graver par gravure ionique réactive la région supérieure légèrement dopée jusqu'à une profondeur correspondant à l'épaisseur de la région supérieure,

mettre sousvide le réacteur,

introduire une atmosphère de CC1₂F₂ et d'oxygène dans le réacteur à une pression de 2,66 Pa (20 microns), à un débit de 20 centimètres cube par minute et avec un rapport gazeux volumique de CC1₂F₂ à l'oxygène de 1, appliquer une puissance 100 watts au réacteur, et

graver par gravure ionique réactive la région fortement dopée et au moins une partie de la région inférieure.

11. Procédé selon la revendication 10, dans lequel le semiconducteur est du silicium, la région supérieure est une couche épitaxiale de silicium de type de conductivité n ou p, la région inférieure est un région de silicium de type p ou n et la région fortement dopée est un région de silicium de type n ou p.

12. Procédé selon la revendication 10, dans lequel le semiconducteur est du silicium, la région fortement dopée et les régions supérieure et inférieure sont toutes des régions de silicium de type n ou p.

13. Procédé selon l'une quelconque des revendications 1 à 12, dans lequel la rainure a une profondeur allant jusqu'à 1,25 micromètres.

Drawing