(19)
(11) EP 0 186 518 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
07.01.1988 Bulletin 1988/01

(43) Date of publication A2:
02.07.1986 Bulletin 1986/27

(21) Application number: 85309507

(22) Date of filing: 24.12.1985
(84) Designated Contracting States:
DE FR GB IT

(30) Priority: 28.12.1984 JP 27993784

(71) Applicant: KABUSHIKI KAISHA TOSHIBA
 ()

(72) Inventors:
  • Imamura, Kaoru c/o Patent Division
     ()
  • Muramoto, Kenichi c/o Patent Division
     ()

   


(54) A breakdown protected transistor device


(57) A protection circuit is provided- for a bipolar planar transistor device (2). The protection circuit comprises a variable resistor device (6) formed of a junction type field effect transistor (7). The resistor device (6) is connected in series with the base of the planar transistor (2). The drain electrode (11) of the J-FET (7) is connected to the base of the planar transistor (2) while the collector of the planar transistor is connected to the gate of the J-FET. Due to this interconnected scheme, the base input resistance of the planar transistor (2) is increased to reduce its base current when a high voltage is applied accidentally to the collector. The base current is not eliminated, however, and the device (2) is protected but can still operate.






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