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(11) | EP 0 317 567 B1 |
| (12) | EUROPEAN PATENT SPECIFICATION |
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PERIPHERAL CONTROL CIRCUITRY FOR PERSONAL COMPUTER PERIPHERIESTEUERUNGSSCHALTUNGSANORDNUNG FÜR PERSONALRECHNER CIRCUITS DE COMMANDE PERIPHERIQUES POUR ORDINATEURS PERSONNELS |
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| Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention). |
BACKGROUND OF THE INVENTION
[0001] This invention relates to the field of micro-circuits for video games and personal computers, especially those implemented in MOS (metal oxide seimconductor) technology where circuit implementation is provided with LSI chip size as a consideration. It further relates to the circuits used to control and interface peripheral devices in such a computer system where bus time is allocated and priority for bus accessing is a factor.
[0002] Dash, USPN 4,034,983, shows a video game computer circuit with audio and pot interfacing. Dash's circuitry includes an analog mapping circuit for receiving input signals for a pair of paddle controls, an interface circuit, and a sound signal generator circuit for driving an audio speaker.
[0003] Best, USPN 4,445,187, shows a video game circuit with an audio-dialog. A tape cartridge as opposed to a disk is interfaced to the circuit. Audio output circuits are implemented.
[0004] Sukonick, USPN 4,070,710, shows a peripheral device (here a video display) control and interface circuit utilizing data bus and address bus architecture.
[0005] Other circuits have followed which have improved upon these circuits to one degree or another.
SUMMARY OF THE INVENTION
[0006] An object of the present invention is to provide a peripheral control circuit which can be incorporated into a personal computer system and is compatible with address bus and data bus architecture, as well as direct memory access (DMA) where priority is established for bus access.
[0007] A second object of the invention is to provide a peripheral control circuit whose operating parameters are resettable by and from a system microprocessor and from memory via the bus architecture.
[0008] A further object of the invention is to package the various peripheral port control and interface circuit components by size and power consumption.
[0009] The objects of this invention are realized in a custom NMOS 48 pin chip capable of interfacing with the data bus architecture and address bus architecture of a host computer system which extensively uses direct memory access (DMA).
[0010] United States Patent US-A-4,296,476 discloses a system in which the contents of one data register are used to select. the particular type of audio that will be produced by the audio generator. A counter section includes counters which are used as noise generator.
[0012] Independent control and interface circuits are provided for each of right and left audio channels, an information storage medium such as floppy disk, a communication port (UART), and up to four joy stick or paddle (pot) ports.
[0013] Each independent control and interface circuit is loaded with data from a data bus connection according to instructions placed at that data's destination.
[0014] A separate interrupt priority control and status circuit is dedicated to communication with a microprocessor in the host computer system. This microprocessor communication circuit is connected with each of the right and left audio channel circuits, the disk circuit, and the UART circuit.
[0015] A separate logic circuit communicates DMA requests from the audio and disk circuits to the host system.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The invention will be better understood from a reading of the following detailed description of the preferred embodiment in conjunction with the accompanying drawings, in which:
Figure 1 is a block diagram of the peripheral device circuit chip;
Figure 2 is a block diagram of the UART port controller circuit;
Figure 3 is a block diagram of the disk port controller circuit;
Figure 4 is a detailed block diagram of the audio ports controller circuit;
Figure 5 is a detailed block diagram of the pot port controller circuit.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0017] The present invention provides an improved peripheral control circuit for use in a microprocessor driven personal computer system utilizing direct memory access (DMA) and incorporating address and data bus architecture. The invention provides audio, disk, UART (Universal Asynchronous Receiver/ Transmitter) and controller port interfacing and control signal generation using less chip "real estate" and faster processing than found in other peripheral controllers. Queue and priority access enhance the duty cycle of the bus architecture. The architecture reduces inter-chip and intra-chip wiring, thereby reducing noise interference.
[0018] Figure 1 shows the circuitry for the present peripheral controller implemented on a single chip. An 8-bit wide register address (RGA) bus 11 provides an input to the chip through a first buffer 13. The buffer 13 loads addresses onto a continuation of the address bus 15. This continuation address bus 15 inputs 8-bit addresses into a register address decoder 17. The register address decoder 17 could be implemented on another circuit chip, but it is desirable to implement the register address decoder 17 on the same chip to cut down on wiring and on line noise pick-up. Data is received into the chip through a 16-bit wide data bus 19. A buffer register 21 in the chip transmits/receives the data and connects the bus 19 with a continuation data bus 23.
[0019] The invention is designed to operate with a plurality of 16-bit/32-bit microprocessor systems, including a personal computer system utilizing a Motorola 68000 microprocessor as its CPU. The system disclosed in "Video Game and Personal Computer", US-A-4 777 621, and "Display Generator Circuitry for Personal Computer System," WO 88/00490, is such a system.
[0020] The chip includes interrupt status registers 25 connected to receive external interrupt input lines 25a, as would be provided by other peripheral devices in the system. The plurality of interrupt status registers 25 is connected to receive and send data to the data bus 23. The status registers 25 feed interrupt control and priority logic 27, which outputs interrupt code signals which are carried off the chip to the 68000 microprocessor.
[0021] A plurality of data registers 29, 31 are connected to receive data from the data bus 23. The data registers 29 are connected to control circuitry for the left audio channel, while the data registers 31 are connected to control circuitry for the right audio channel. Each of the data registers 29, 31 transfers its data into a plurality of audio control counters and registers 33 and 35, which in turn each drive an individual one of the digital to analog (D/A) converters 37, 39, of which there are four in all. The D/A converters 37 are connected to the output port 41 for the left audio channel, while D/A converters 39 are connected to the output port 43 for the right audio channel. Each of the audio control counter and register circuits 33 and 35 generate interrupt signals on lines 24, which are connected into the interrupt status registers 25. D/A converter circuits 37 and 39 are constructed according to known techniques. Each of the audio control counter and register circuits 33, 35 also provides a direct memory access request via the respective lines 45, 47 to a DMA request logic multiplexer (serializer) circuit 49. This DMA request logic circuit 49 provides an external DMA request signal on line 51 for direct memory access to system memory for additional data or instruction words. The lines 45, 47 carry timing strobe decode signals which act as DMA access requests to the DMA request logic circuit 49. While the left and right channel audio circuits are each represented as a single channel in Figure 1, they actually include two channels each of which are mixed at the port, as will be described further below.
[0022] The disk controller includes data registers 53 connected to receive data and also load data onto the data bus 23. The data registers 53 transfer data with a disk control logic circuit 55. Disk control logic 55 is connected to a pre-compensator circuit 57 for sending signals to a disk port 61 via a connection line 59. Information received into the disk port 61 is transmitted via line 63 into a data separator circuit 65, which in turn is connected to the disk control logic 55. DMA access request lines 67 connect the disk control logic circuit 55 to the DMA request logic circuit 49. The disk control logic 55 also has interrupt signal lines 24 connected to the interrupt status registers 25.
[0023] UART port 69 is sent data via a line 71 from a transmit buffer circuit 73. UART port 69 provides data to a receive buffer circuit 77 via line 75. The transmit buffer 73 and receive buffer 77 are connected to a UART control logic circuit 79. UART control logic circuit 79 has interrupt signal connections 24 to the interrupt status registers 25. UART control logic circuit 79 likewise receives data from and transmits data to data registers 81. Data registrars 81 provide two way access with data bus 23.
[0024] Four controller (pot) ports 83 a, b, c, d are connected via lines 86, 87, 89 and 91 to a bi-directional buffer and latch circuit 93. The buffer and latch circuit 93 is operated under the control of pot control and counters circuit 95, which communicates with the data bus 23 through data registers 97. The data registers 97 transfer data with the data bus 23.
[0025] The register address decoder 17 receives addresses via the address bus 15 generated by the microprocessor or by a register address encoder on an address generator chip. As a function of the address received, the decoder 17 provides an exclusive load enable signal on one of lines 99 to one of the registers 25, 29, 31, 53, 81 or 97 to cause the register to receive (load) or transmit (unload) data from or to the data bus 23, thereby controlling which register communicates with the data bus 23 at any given point in time.
[0026] The UART control circuitry, Figurre 2, operating in connection with port 69, transfers serial data via line 71 from the transfer buffer 73 to the port 69, and transfers data in serial form received at port 69 to the receive buffer 77 via line 75. Each buffer 73, 77 is driven to load and unload information under the control of clock pulses. The control register 81 and data transmit buffer register 73 receive parallel data from the data bus 23, while receive buffer register 77 sends parallel data to the bus 23.
[0027] The control logic 79 includes a first down courter 101 which develops first clock timing pulses on line 103 which are used to control information transfer into and out of the receive buffer register 77. A second down counter 105 is loaded from the control logic 79, which operates the transmit buffer register 73 at a second and different time from the receive buffer register 77. The control circuit 79 can be implemented as a general logic arithmetic unit, and is driven by an input on line 109 from the system clock of the host computer system. The control logic circuitry 79 also outputs interrupt signals on line 24.
[0028] The UART port 69 is a universal receive and transmit port of the type commonly known in the industry as an "RS232" port. A system control signal places the circuitry in either the "read mode," i.e., receiving, or write mode, i.e., transmitting. The UART port 69 circuitry typically does not timeshare receive and transmit functions. The circuit alternatively controls the receive function or the transmit function, which are intermittent as the data rate is considerably slower than the system processing rate.
[0029] The disk port 61 outputs serial data transferred from the precompensator circuit 57 (Figure 3) via line 59. Serial data is input from the disk port 61 via line 63 to the data separator circuit 65. The system clock on line 109 is input into the disk control logic circuit 55 to control its operation, as well as to precompensator circuit 57 and data separator circuit 65. The data separator circuit 65 creates a carry pulse on line 111 to an input data shift register 113 to control the transfer of data through the data shift register 113. Data is fed serially via line 115 from the data separator 65 to the data register 113. Data register 113 then transfers data to the data bus 23 in parallel format through a first-in, first-out buffer 120 which is three 16-bit registers deep. The FIFO buffer 120 is controlled by an enable signal line 99. A location register 116 is loaded from the data bus 23 under control of an enable line 99. This register 116 is 16-bits wide and holds a comparison value which is input to comparator 114 to be compared with the value in the data register 113. The output from the comparator 114 is a synch signal on line 112 to control logic 55 to provide the word count control signal output on line 121.
[0030] Another data shift register 117 receives data from the data bus 23 in 16-bit parallel transfers through a three 16-bit register deep FIFO buffer 122 which is controlled by an enable signal 99. A down counter 119 loaded from control register 53 provides a control instruction to the disk control logic circuit 55 which in turn provides a control function via line 121 to the data shift registers 117 to control the word count transfer of information through the data shift register 113, the shift register 117 and the FIFO buffers 120, 122. Shift register 117 outputs serial data on the line 123 to the precompensator circuit 57. A precompensator circuit decodes the differences between successive bits of data as "zeros" and "ones" and introduces a phase shift to compensate for bit migration on the magnetic medium caused by the differences between magnetic attraction and repulsion of "zeros" and "ones." The pre-compensator circuit 57 provides a delay or acceleration of 0, 140 ns, 280 ns or 560 ns to individual pulses delivered to the disk port 61 to compensate for location migration on the disk medium. Register 117 receives carry pulses on line 111 from separator 65 which control the transfer rate of the register 117.
[0031] The control register 53 receives data from the data bus 23 in 16-bit parallel transferes and likewise transfers the information to the disk control logic circuit 55 under the control of an enable signal on line 90 from the register address decoder 17. The disk control logic circuit 55 provides two interrupt status signals on lines 24 to the interrupt status registers 25 and three DMA request signals on lines 67 to the DMA, request logic circuit 49 as previously discussed.
[0032] The pre-compensator 57, shift register 117, and buffer 122 are utilized when writing information onto a disk through the port 61. The data separator 65, data shift register 113, and buffer 120 are used when reading information from a disk. Carry pulses on lines 111, generated by the separator 65, are used during both read and write operations.
[0033] The data separator circuit 65 operates in a complementary manner to the pre-compensator circuit 57 discussed above. This data separator sets up electronic inspection times for the data received as a function of the ideal data frequency rate. An inspection time period is called a "window" because it is the time during which the circuit "looks" for a data bit expected to be input. Due to irregularities in disk drives and data transmission and magnetic migration, i.e., "bit migration," on floppy disks, the data separator circuit is needed to track input data by shifting the window to compensate for frequency and phase errors in the arrival time of the data. A data input (separator) circuit is shown in US-A-4 780 844, entitled "Data Input Circuit With Digital Phase Locked Loop".
[0034] The audio control circuitry, Figure 4, is duplicated to generate the left side audio signals to port 41 and the right side audio signals to port 43. Each side audio circuit is made up of two channels, an A channel and a B channel, which contain identical circuitry.
[0035] The A channel for the left audio port 41 includes three sound control registers, register 126a for signal period, register 126b for duration, and register 126c for volume. The "period" data register 126a, "length" data register 126b, and "volume" data register 126c each receive data from the data bus 23 under the control of individual enable lines 99 and transfer data into "period," "length" and "volume" control counters 127a, 127b, and 127c. Period data contained in register 126a is tone frequency data, i.e., the frequency of the sound "note" generated. Length data contained in register 126b is the time duration of the tone. Volume data is the amplitude of the "note". This data is fed to control counters 127a, b, c which provide signals via lines 130a, b, c, to the control logic 129. The load signal lines 132a, b, c control the loading of data into one of the control counters 127a, b, c. The count signal lines 134a, b, c control the serial readout of the data held in each control counter 127a, b, c.
[0036] The control circuit 129 has an output control line 140 to the audio data register 125. This audio data register stores the data which defines the character of the music. As an example, perhaps the system is programmed to produce a middle "c" note. The data defining this note is held in the register 125. This register is then controlled by circuit 129 to modify the period, length, and volume for the note.
[0037] Control logic circuit 129 receives the output 130a from "period" control counter 127a, the output 130b from "length" control counter 127b, and the output 130c from "volume" control counter 127c, and provides the load control signals on lines 132a, 132b, 132c and count control signals on lines 134a, 134b, 134c to the respective counters 127a, 127b, 127c. Control circuit 129 provides an interrupt output on line 24 to status registers 25, and a DMA access request output on line 45 to DMA request logic parallel-to-serial multiplexer 49. The operation of the control circuit 129 is clocked with system clock signals on line 109. The control logic circuit 129 can be implemented as a general logic arithmetic unit or by an instruction decoder logic circuit. The control logic circuit 129 can also be implemented by a logic array network implemented in NAND gates.
[0038] Buffer register 29 is loaded with data from data bus 23 under control of an enable line 99. Buffer register 29 outputs to an audio data register 125 under control of line 140 from control logic circuit 129. The information in the audio data register 125 is then output to a digital-to-analog converter 139. The control logic provides a control line 135 to this D-to-A converter 139. The analog output from the D-to-A converter 139 is the left audio channel A signal and is connected to the left audio port 41. This circuitry is duplicated to form the left audio channel circuit 141. The output of the B channel circuit 141 is similarly connected to port 41 so that the two audio signals are mixed.
[0039] Duplicate circuitry 143, 145 is used for the right audio A and B channels, respectively. The output lines from these circuits 143, 145 are likewise mixed by a common connection to the right audio port 43. Each of the circuits 141, 143, 145 have DMA request output lines 45 and interrupt signal lines 24 as outputs.
[0040] The controller (pot) port control circuitry 93, 95, and 97 of Figure 1, with its connections 85, 87, 89 and 91 to the pot ports 83a, 83b, 83c, and 83d, can be implemented as shown in Figure 5. Each of the four pot ports 83a, 83b, 83c, and 83d are identified in broken lines. The bi-directional lines 85, 87, 89, and 91 comprise the pairs 85a-85b, 87a-87b, 89a-89b, and 91a-91b, as shown in Figure 5. The lines 85a, 87a, 89a and 91a are signal level lines tied to tri-state drivers 149a, b, c, d. The lines 85b, 87b, 89b, and 91b are tied to a + 5V DC voltage reference. A joystick circuit is shown within the pot port blocks 83a, 83b, 83c, and 83d. Each joystick circuit includes a variable 470K ohm resistor 147a, 147b, 147c and 147d and 47 microfarad capacitors 151a, 151b, 151c, and 151d connected to ground. The resistor and capacitor establish an RC time constant that is adjustable with the adjustment of the variable resistor.
[0041] A control register 154 is loaded from the data bus 23 under control of an enable signal on line 99. This control register feeds two different control bits on lines 161 to each individual one of four dedicated tri-state drivers for pot ports 83a, 83b, 83c and 83d. Bits nos. 15 and 14 of the control register 154 are output via lines 161a to a first tri-state driver circuit 149a. Bit nos. 13 and 12 of register 154 are output via lines 161b to a second tri-state driver circuit 149b, bit nos. 11 and 10 of register 154 are output via lines 161c to a third tri-state driver 149c, and bit nos. 9 and 8 of register 154 are output via lines 161d to a fourth tri-state driver circuit 149d. Each tri-state driver is a differential line driver with tri-state outputs. Such circuits have been supplied by many manufacturers, including Texas Instruments, Inc., for many years. These drivers can provide a + 5V DC, OV DC, and intermediate level voltage output.
[0042] A control counter circuit 157 is clocked by the system video horizontal synch pulse on line 156, which provides the line scan sample rate of the video display to the control counter 157. Bit no. 0 of the control register 154 is output as the reset control 163 of the counter 157. The control register 154 instructs each of the tri-state drivers 149a, 149b, 149c, and 149d when to switch its state to OV to drive down the signal on its respective pot port 83a, 83b, 83c and 83d and when to switch its state to allow the signal level to begin to rise. The RC time constant of the particular joystick will determine the rise time.
[0043] Individual control switches 158a, 158b, 159c, and 158d monitor respective ones of the lines 85a, 87a, 89a, and 91a. When a preset level is sensed, each control switch outputs a control signal 150a, 150b, 150c, and 150d to latch registers 153a, b, c, d. The output of the control counter 157 is simultaneously fed as data into latch registers 153a, 153b, 153c, and 153d, which are assigned one each to the pot ports 83a, 83b, 83c, and 83d. When a control signal 150 is received by a latch register 153, the respective register is loaded with the instantaneous value in control counter 157. In this manner, the analog position of each joystick variable resistor 147a, 147b, 147c, and 147d can be determined and is digitized into a (digital) value stored in the registers 153a, 153b, 153c, and 153d. The position of a joystick is translated into a signal value which operated the control switch 158. A control switch 158 then sets a latch register 153 to enable the value resident in the free running control counter 157 to be transfered into the latch register. In this manner the analog position of each joy stick is translated into a digital value which can be loaded onto the data bus 23.
storing audio period data in a period register (126a) coupled to the data bus (23) in response to a first enable signal;
storing the audio period data as a period count in a period counter (127a) coupled to the period register (126a) in response to a period load signal from a control circuit (129) coupled to the period counter (127a);
controlling the readout of the period data from the period counter (127a) in response to a period count control signal from the control circuit (129);
providing a sound data control signal from the control circuit (129) to an audio data register (125) at a frequency determined by the period count;
storing audio length data in a length register (126b) coupled to the data bus (23) in response to a second enable signal;
storing the audio length data as a length count in a length counter (127b) coupled to the length register (126b) and to the control circuit (129) in response to a length load signal from the control circuit (129);
controlling the readout of the length data from the length counter (126b) in response to a length count control signal from the control circuit (129);
storing audio volume data in a volume register (126c) coupled to the data bus (23) in response to a third enable signal;
storing the audio volume data in a volume counter (127c) coupled to the volume register (126b) and to the control circuit (129) in response to a volume load signal from the control circuit (129);
controlling the readout of the audio volume data from the volume counter (127c) in response to a volume count control signal from the control circuit (129);
providing a DMA access request (45) from the control circuit (129) to cause sound data stored in the system memory to be placed on the data bus (23), wherein the sound data corresponds to the sound waveform;
storing the sound data corresponding to the sound waveform in the audio data register (125) in response to the sound data control signal;
converting the sound data corresponding to the sound waveform to an analog signal in a D-to-A converter (139) coupled to the audio data register (125);
providing a converter control signal from the control circuit (129) to the D-to-A converter (139) in response to the audio volume data read out from the volume counter (127c) to control the amplitude of the analog signal; and
outputting the analog signal corresponding to the sound waveform from the D-to-A converter (139) to an audio port (41).
outputting a plurality of analog signals corresponding to a plurality of sound waveforms from a plurality of D-to-A converters (139, 141, 143, 145) to the audio port (41, 43).
outputting a first analog signal corresponding to a first sound waveform from the first audio channel to a first audio port (41); and
outputting a second analog signal corresponding to a second sound waveform from the second audio channel to a second audio port (43).
mixing together the plurality of analog signals for output to the audio port (41, 43).
period data register (126a) coupled to the data bus (23) for storing audio period data in response to a first enable signal;
period counter means (127a) coupled to the period data storing means (126a) for storing a period count;
control circuit (129) coupled to the period counter means (127a) and responsive to a clock signal and the period count for controlling the loading and readout of period data by providing a period load signal and a period count control signal to the period counter means (127a);
control circuit (129) coupled to the period counter means (127a) for providing a sound data control signal at a frequency determined by the period count to an audio data register means (125);
length data register (126b) coupled to the data bus (23) for storing audio length data in response to a second enable signal;
length counter means (127b) coupled to the length data register (126b) for storing a length count;
control circuit (129) coupled to the length counter means (127b) and responsive to a clock signal and the length count for controlling the loading and readout of length data by providing a length load signal and length count control signal to the length counter means (127b);
volume data register (126c) coupled to the data bus (23) for storing audio volume data in response to a third enable signal;
volume counter means (127c) coupled to the volume data register (126c) for receiving the audio volume data;
control circuit (129) coupled to the volume counter means (127a) and responsive to a clock signal and the volume count for controlling the loading and readout of audio volume data by providing a volume load signal and a volume count control signal to the volume counter means (127c);
DMA access request means (45) coupled to the control circuit (129) for providing a DMA access request to cause sound data stored in the system memory to be placed on the data bus (23), wherein the sound data corresponds to the sound waveform;
audio data register means (125) coupled to the control circuit (129) for storing the sound data corresponding to the sound waveform in response to the sound data control signal;
D-to-A converter means (139) coupled to the audio data register means (125) for converting the sound data corresponding to the sound waveform to an analog signal;
control circuit (129) coupled to and responsive to audio volume data read out from the volume counter means (127c) for providing a converter control signal to the D-to-A converter means (139) to control the amplitude of the analog signal; and
means for outputting the analog signal corresponding to the sound waveform from the D-to-A converter means to an audio port (41).
signals corresponding to a plurality of sound waveforms to the audio port (41,43).
a first audio channel for outputting a first analog signal corresponding to a first sound waveform to a first audio port (41); and
a second audio channel for outputting a second analog signal corresponding to a second sound waveform to a second audio port (43).
means for mixing together the plurality of analog signals for output to the audio port (41,43).
a data bus;
an address bus;
a register address decoder connected to said address bus, said decoder output providing a plurality of individual enable timing pulse signals;
a DMA access serializer circuit for taking a plurality of DMA access requests and outputting them in serial order of receipt;
a plurality of interrupt status registers connected to said data bus and connected to receive said system interrupt signals;
an interrupt control circuit connected to said plurality of interrupt status registers, said interrupt circuit providing a microprocessor type interrupt code output;
an audio left channel port;
an audio right channel port;
a disk port;
a UART port;
at least one of a plurality of identical pot ports;
a UART control and interface circuit connected to receive data from said data bus and to send data to said data bus, and connected to send an receive information with said UART port, said UART control and interface circuit having a connection to receive certain of said enable signals from said register address decoder;
at least one pot control and interface circuit connected to receive data from said data bus and to send data to said data bus, and connected to power and monitor the signal level at said one pot port, said pot control and interface circuit having a connection to receive certain of said enable signals from said register address decoder whereby said data transfer with said data bus is controlled
a left audio channel control and interface circuit connected to receive data from said data bus and to send audio signals to said audio left channel port, said left audio channel control and interface circuit having a connection to receive certain of said enable signals from said register address decoder whereby said data transfer from said data bus is controlled, and having connection to said DMA access serializer circuit to request left audio channel data onto said data bus;
a right audio channel control and interface circuit connected to receive data from said data bus and to send audio signals to said audio right channel port, said right audio channel control and interface circuit having a connection to receive certain of said enable signals from said register address decoder whereby said data transfer from said data bus is controlled, and having a connection to said DMA access serializer circuit to request right audio channel data onto said data bus; and
a disk control and interface circuit connected to send and receive data with said data bus, said disk control and interface circuit having a connection to receive certain of said enable signals from said register address decoder whereby said data transfer with said data bus is controlled, said disk control and interface circuit being connected to send and receive information with said disk port and having a connection to receive certain of said enable signals from said register address decoder whereby said data transfer with said data bus is controlled, said disk control and interface circuit being connected to send and receive information with said disk port and having a connection to said DMA access serializer circuit to request disk data into said data bus.
Speichern von Audio-Periodendaten in einem Periodenregister (126a), welches unter Ansprechen auf ein erstes Freigabesignal mit dem Datenbus (23) verbunden ist,
Speichern der Audioperiodendaten als eine Periodenzählung in einem Periodenzähler (127a), der mit dem Periodenregister (126a) verbunden ist, und zwar unter Ansprechen auf ein Periodenladesignal aus einem Steuerschaltkreis (129), der mit dem Periodenzähler (127a) verbunden ist,
Steuern der Auslesung der Periodendaten von dem Periodenzähler (127a) unter Ansprechen auf ein Periodenzählsignal von dem Steuerschaltkreis (129),
Bereitstellen eines Klangdatensteuersignals aus dem Steuerschaltkreis (129) an ein Audiodatenregister (125) mit einer Frequenz, die durch die Periodenzählung bestimmt wird,
Speichern von Audiolängendaten in einem Längenregister (126b), welches unter Ansprechen auf ein zweites Freigabesignal mit dem Datenbus (23) verbunden wird,
Speichern der Audiolängendaten als eine Längenzählung in einem Längenzähler (127b), der mit dem Längenregister (126b) und mit dem Steuerschaltkreis (129) verbunden ist, und zwar unter Ansprechen auf ein Längenladesignal von dem Steuerschaltkreis (129),
Steuern des Auslesens der Längendaten aus dem Längenzähler (126b) unter Ansprechen auf ein Längenzählungssteuersignal aus dem Steuerschaltkreis (129),
Speichern von Audiolautstärkedaten in einem Lautstärkeregister (126c), welches mit dem Datenbus (23) verbunden ist, und zwar unter Ansprechen auf ein drittes Freigabesignal,
Speichern der Audiolautstärkedaten in einem Lautstärkezähler (127c), welcher mit dem Lautstärkeregister (126c) und mit dem Steuerschaltkreis (129) verbunden ist, und zwar unter Ansprechen auf ein Lautstärkeladesignal aus dem Steuerschaltkreis (129),
Steuern des Auslesens der Audiolautstärkedaten aus dem Lautstärkezähler (127c) unter Ansprechen auf ein Lautstärkezählungssteuersignal aus dem Steuerschaltkreis (129),
Bereitstellen einer DMA-Zugriffsanfrage (45) aus dem Steuerschaltkreis (129), um zu bewirken, daß in dem Systemspeicher gespeicherte Klangdaten auf den Datenbus (23) gebracht werden, wobei die Klangdaten der Klangwellenform entsprechen,
Speichern der Klangdaten, welche der Klangwellenform entsprechen, in dem Audiodatenregister (125), und zwar unter Ansprechen auf das Klangdatensteuersignal,
Umwandeln der Klangdaten, welche der Klangwellenform entsprechen, in ein Analogsignal in einem D/A-Wandler (139), der mit dem Audiodatenregister (125) verbunden ist,
Bereitstellen eines Wandlersteuersignals aus dem Steuerschaltkreis (129) an den D/A-Wandler (139), und zwar unter Ansprechen auf die Audiolautstärkedaten, die aus dem Lautstärkezähler (127c) ausgelesen wurden, um die Amplitude des Analogsignals zu steuern, und
Ausgeben des Analogsignals entsprechend der Klangwellenform aus dem D/A-Wandler (139) an einen Audioanschluß (41).
Ausgeben einer Mehrzahl von Analogsignalen, welche einer Mehrzahl von Klangwellenformen entsprechen, aus einer Mehrzahl von D/A-Wandlern (139, 141, 143, 145) an die Audioanschlüsse (41, 43).
Ausgeben eines ersten Analogsignales, welches einer ersten Klangwellenform entspricht, aus dem ersten Audiokanal an einen ersten Audioanschluß (41), und
Ausgeben eines zweiten Analogsignales, welches einer zweiten Klangwellenform entspricht, aus dem zweiten Audiokanal an einen zweiten Audioanschluß (43).
Mischen der Mehrzahl von Analogsignalen für die Ausgabe an den Audioanschluß (41, 43).
Periodendatenregister (126a), welche mit dem Datenbus (23) verbunden sind, um Audioperiodendaten unter Ansprechen auf ein erstes Freigabesignal zu speichern,
eine Periodenzählereinrichtung (127a), welche mit der Periodendatenspeichereinrichtung (126a) verbunden ist, um eine Periodenzählung zu speichern,
einen Steuerschaltkreis (129), der mit der Periodenzählereinrichtung (127a) verbunden ist und welcher auf ein Taktsignal und auf die Periodenzählung anspricht, um das Laden und Auslesen von Periodendaten zu steuern, indem er ein Periodenladesignal und ein Periodenzählungssteuersignal an die Periodenzählereinrichtung (127a) ausgibt bzw. bereitstellt,
einen Steuerschaltkreis (129), der mit der Periodenzählereinrichtung (127a) verbunden ist, um ein Klangdatensteuersignal bei einer Frequenz, welche durch die Periodenzählung bestimmt wird, an eine Audiodatenspeichereinrichtung (125) bereitzustellen,
ein Längendatenregister (126b), welches mit dem Datenbus (23) verbunden ist, um Audiolängendaten unter Ansprechen auf ein zweites Freigabesignal zu speichern,
eine Längenzählereinrichtung (127b), welche mit dem Längendatenregister (126b) für die Speicherung einer Längenzählung verbunden ist,
einen Steuerschaltkreis (129), der mit der Längenzählereinrichtung (127b) verbunden ist und welche auf ein Taktsignal sowie auf die Längenzählung anspricht, um das Laden und Auslesen von Längendaten zu steuern, indem ein Längendatenladesignal und ein Längenzählungssteuersignal an die Längenzählereinrichtung (127b) ausgegeben wird,
ein Lautstärkedatenregister (126c), welches mit dem Datenbus (23) verbunden ist, um Audiolautstärkedaten unter Ansprechen auf ein drittes Freigabesignal zu speichern,
eine Lautstärkenzählereinrichtung (127c), welche mit dem Lautstärkedatenregister (126c) für den Empfang der Audiolautstärkedaten verbunden ist,
einen Steuerschaltkreis (129), der mit der Lautstärkezähleinrichtung (127a) verbunden ist und der auf ein Taktsignal und auf die Lautstärkezählung anspricht, um das Laden und Auslesen von Audiolautstärkedaten zu steuern, indem ein Lautstärkeladesignal und ein Lautstärkezählungssteuersignal für die Lautstärkezähleinrichtung (127c) bereitgestellt wird,
einer DMA-Zugriffsanfrageeinrichtung (45), welche mit dem Steuerschaltkreis (129) verbunden ist, um eine DMA-Zugriffsanfrage bereitzustellen, um zu bewirken, daß Klangdaten, die in dem Systemspeicher gespeichert sind, auf dem Datenbus (23) angeordnet werden, wobei die Klangdaten der Klangwellenform entsprechen,
eine Audiodatenregistereinrichtung (125), die mit dem Steuerschaltkreis (129) verbunden ist, um die Klangdaten, welche der Klangwellenform entsprechen, unter Ansprechen auf das Klangdatensteuersignal zu speichern,
eine D/A-Wandlereinrichtung (139), die mit der Audiodatenregistereinrichtung (125) verbunden ist, um die Klangdaten, welche der zweiten Wellenform entsprechen, in ein Analogsignal umzuwandeln,
einen Steuerschaltkreis (129), der mit der Auslesung von Audiolautstärkedaten aus der Lautstärkezähleinrichtung (127) verbunden ist und auf diese anspricht, um ein Wandlersteuersignal für die D/A-Wandlereinrichtung (139) bereitzustellen, um die Amplitude des Analogsignals zu steuern, und
eine Einrichtung für das Ausgeben des Analogsignales, welches der Klangwellenform entspricht, und zwar von der D/A-Wandlereinrichtung zu einem Audioanschluß (41).
einen ersten Audiokanal für die Ausgabe eines ersten analogen Signales, welches einer ersten Klangwellenform entspricht, an einen ersten Audioanschluß (41), und
einen zweiten Audiokanal für die Ausgabe eines zweiten analogen Signales, welches einer zweiten Klangwellenform entspricht, an einen zweiten Audioanschluß (43).
eine Einrichtung zum Mischen der Mehrzahl von analogen Signalen für die Ausgabe an den Audioanschluß (41, 43).
einen Datenbus,
einen Adreßbus,
einen Registeradressendecoder, der mit dem Adreßbus verbunden ist, wobei der Decoderausgang eine Mehrzahl von individuellen Zeitgeberimpulssignalen für eine Freigabe bereitstellt,
einen Schaltkreis für Parallel-Reihenumsetzung für den DMA-Zugriff, um eine Mehrzahl von DMA-Zugriffsanfragen aufzunehmen und sie in der Reihenfolge ihres Empfangs auszugeben,
eine Mehrzahl von Interrupt-Statusregistern, die mit dem Datenbus verbunden sind und die so angeschlossen sind, daß sie Systeminterrupt-Signale aufnehmen,
einen Interrupt-Steuerschaltkreis, der mit der Mehrzahl von Interrupt-Statusregistern verbunden ist, wobei der Interrupt-Steuerschaltkreis eine Interruptcode-Ausgangsgröße vom Mikroprozessortyp bereitstellt,
einen linken Audiokanalanschluß,
einen rechten Audiokanalanschluß,
einen Festplatten(disc)-Anschluß,
einen UART-Anschluß,
zumindest einen von einer Mehrzahl identischer Potentiometeranschlüsse,
einen UART-Steuer- und Interface-Schaltkreis, der so angeschlossen ist, daß er Daten aus dem Datenbus empfängt und dann an den Datenbus abschickt, und der so angeschlossen ist, daß er eine Empfangsinformation zu dem UART-Anschluß schickt, wobei der UART-Steuer- und Interface-Schaltkreis eine Verbindung hat, um bestimmte Freigabesignale aus dem Registeradreßdecoder zu empfangen,
zumindest einen Potentiometersteuer- und Interface-Schaltkreis, der so angeschlossen ist, daß er Daten aus dem Datenbus empfängt und an diesen abschickt, und der so angeschlossen ist, daß er das Signalniveau an dem einen Potentiometeranschluß mit Energie versorgt und überwacht, wobei der Potentiometersteuer- und Interface-Schaltkreis eine Verbindung hat, um bestimmte Freigabesignale aus dem Registeradreßdecoder zu empfangen, wodurch die Datenübertragung mit dem Datenbus gesteuert wird,
einen Steuer- und Interface-Schaltkreis für den linken Audiokanal, welcher so angeschlossen ist, daß er Daten aus dem Datenbus empfängt und Audiosignale an den linken Audiokanalanschluß übermittelt, wobei dieser Steuer- und Interface-Schaltkreis für den linken Audiokanal eine Verbindung derart hat, daß er bestimmte Freigabesignale von dem Registeradreßdecoder erhält, wodurch die Datenübertragung von dem Datenbus gesteuert wird, und eine Verbindung mit dem Parallel-Reihenumsetzer-Schaltkreis für den DMA-Zugriff hat, um Anfragen für linke Audiokanaldaten an den Datenbus zu richten,
einen Steuer- und Interface-Schaltkreis für den rechten Audiokanal, welcher so angeschlossen ist, daß er Daten von dem Datenbus empfängt und Audiodaten an den rechten Audiokanalanschluß übermittelt, wobei der Steuer- und Interface-Schaltkreis für den rechten Audiokanal eine Verbindung derart hat, daß er bestimmte Freigabesignale aus dem Registeradreßdecoder erhält, wodurch die Datenübertragung von dem Datenbus gesteuert wird, und eine Verbindung zu dem Parallel-Serielumsetzer-Schaltkreis für den DMA-Zugriff hat, um für rechte Audiokanaldaten auf dem Datenbus anzufragen, und
einen Festplattensteuer- und Interface-Schaltkreis, der so angeschlossen ist, daß er Daten an den Datenbus sendet und von diesem empfängt, wobei der Festplattensteuer- und Interface-Schaltkreis einen Anschluß hat, um bestimmte Freigabesignale von dem Registeradreßdecoder zu empfangen, wodurch der Datentransfer mit dem Datenbus gesteuert wird, wobei der Festplattensteuer- und Interface-Schaltkreis so angeschlossen ist, daß er Information an den Festplattenanschluß sendet und von diesem empfängt und eine Verbindung hat, so daß er bestimmte Freigabesignale von dem Registeradreßdecoder erhält, wodurch die Datenübertragung mit dem Datenbus gesteuert wird, wobei der Festplattensteuer- und Interface-Schaltkreis so angeschlossen ist, daß er Information an den Festplattenanschluß sendet und von diesem empfängt und eine Verbindung mit dem Parallel-Serielumsetzer-Schaltkreis für den DMA-Zugriff hat, um eine Anfrage für Festplattendaten auf den Datenbus zu richten.
de mémorisation de données de période audio dans un registre (126a) de période, connecté au bus (23) de données, en réponse à un premier signal de validation ;
de mémorisation des données de période audio, en tant que compte de période, dans un compteur (127a) de période connecté au registre (126a) de période en réponse à un signal de chargement de période provenant d'un circuit (129) de commande connecté au compteur (127a) de période ;
de commande de la lecture des données de période du compteur (127a) de période en réponse à un signal de commande de compte de période provenant du circuit (129) de commande ;
de délivrance d'un signal de commande de données sonores par le circuit (129) de commande à un registre (125) de données audio à une fréquence déterminée par le compte de période ;
de mémorisation de données de longueur audio dans un registre (126b) de longueur connecté au bus (23) de données en réponse à un deuxième signal de validation ;
de mémorisation des données de longueur audio en tant que compte de longueur dans un compteur (127b) de longueur connecté au registre (126b) de longueur et au circuit (129) de commande en réponse à un signal de chargement de longueur provenant du circuit (129) de commande ;
de commande de la lecture des données de longueur du compteur (126b) de longueur en réponse à un signal de commande de compte de longueur provenant du circuit (129) de commande ;
de mémorisation de données de volume audio dans un registre (126c) de volume connecté au bus (23) de données en réponse à un troisième signal de validation ;
de mémorisation des données de volume audio dans un compteur (127c) de volume connecté au registre (126b) de volume et au circuit (129) de commande en réponse à un signal de chargement de volume provenant du circuit (129) de commande ;
de commande de la lecture des données de volume audio du compteur (127c) de volume en réponse à un signal de commande de compte de volume provenant du circuit (129) de commande ;
de délivrance d'une demande d'accès DMA (45) par le circuit (129) de commande pour provoquer un placement de données sonores mémorisées dans la mémoire de système sur le bus (23) de données, dans lequel les données sonores correspondent à la forme d'onde sonore ;
de mémorisation des données sonores correspondant à la forme d'onde sonore dans le registre (125) de données audio en réponse au signal de commande de données sonores ;
de conversion des données sonores correspondant à la forme d'onde sonore en un signal analogique dans un convertisseur de numérique en analogique (139) connecté au registre (125) de données audio ;
de délivrance d'un signal de commande de convertisseur par le circuit (129) de commande au convertisseur de numérique en analogique (139) en réponse aux données de volume audio lues à partir du compteur (127c) de volume pour commander l'amplitude du signal analogique ; et
de délivrance du signal analogique correspondant à la forme d'onde sonore par le convertisseur de numérique en analogique (139) à un accès audio (41).
la délivrance d'une pluralité de signaux analogiques correspondant à une pluralité de formes d'onde sonores par une pluralité de convertisseurs de numérique en analogique (139, 141, 143, 145) à l'accès audio (41, 43).
la délivrance d'un premier signal analogique correspondant à une première forme d'onde sonore du premier canal audio à un premier accès audio (41) ; et
la délivrance d'un second signal analogique correspondant à une seconde forme d'onde sonore du second canal audio à un second accès audio (43).
le mélange, les uns avec les autres, de la pluralité de signaux analogiques pour délivrance à l'accès audio (41, 43).
un registre (126a) de données de période connecté au bus (23) de données, destiné à mémoriser des données de période audio en réponse à un premier signal de validation;
un moyen (127a) formant compteur de période, connecté au moyen (126a) de mémorisation de données de période, destiné à mémoriser un compte de période ;
un circuit (129) de commande, connecté au moyen (127a) formant compteur de période et sensible à un signal d'horloge et au compte de période, destiné à commander le chargement et la lecture de données de période en délivrant un signal de chargement de période et un signal de commande de compte de période au moyen (127a) formant compteur de période ;
un circuit (129) de commande, connecté au moyen (127a) formant compteur de période, destiné à délivrer un signal de commande de données sonores, à une fréquence déterminée par le compte de période, à un moyen (125) formant registre de données audio ;
un registre (126b) de données de longueur, connecté au bus (23) de données, destiné à mémoriser des données de longueur audio en réponse à un deuxième signal de validation ;
un moyen (127b) formant compteur de longueur, connecté avec le registre (126b) de données de longueur, destiné à mémoriser un compte de longueur ;
un circuit (129) de commande, connecté au moyen (127b) formant compteur de longueur et sensible à un signal d'horloge et au compte de longueur, destiné à commander le chargement et la lecture de données de longueur en délivrant un signal de chargement de longueur et un signal de commande de compte de longueur au moyen (127b) formant compteur de longueur ;
un registre (126c) de données de volume, connecté au bus (23) de données, destiné à mémoriser des données de volume audio en réponse à un troisième signal de validation ;
un moyen (127c) formant compteur de volume, connecté au registre (126c) de données de volume, destiné à recevoir les données de volume audio ;
un circuit (129) de commande, connecté au moyen (127a) formant compteur de volume et sensible à un signal d'horloge et au compte de volume, destiné à commander le chargement et la lecture de données de volume audio en délivrant un signal de chargement de volume et un signal de commande de compte de volume au moyen (127c) formant compteur de volume ;
un moyen (45) de demande d'accès DMA, connecté au circuit (129) de commande, destiné à fournir une demande d'accès DMA pour provoquer le placement de données sonores mémorisées dans la mémoire de système sur le bus (23) de données, dans lequel les données sonores correspondent à la forme d'onde sonore ;
un moyen (125) formant registre de données audio, connecté au circuit (129) de commande, destiné à mémoriser les données sonores correspondant à la forme d'onde sonore en réponse au signal de commande de données sonores ;
un moyen (139) formant convertisseur de numérique en analogique, connecté au moyen (125) formant registre de données audio, destiné à convertir les données sonores correspondant à la forme d'onde sonore en un signal analogique ;
un circuit (129) de commande, connecté au moyen (127c) formant compteur de volume et sensible à la lecture de données de volume audio à partir de celui-ci, destiné à délivrer un signal de commande de convertisseur au moyen (139) formant convertisseur de numérique en analogique pour commander l'amplitude du signal analogique ; et
un moyen destiné à délivrer le signal analogique correspondant à la forme d'onde sonore du moyen formant convertisseur de numérique en analogique à un accès audio (41).
un premier canal audio destiné à délivrer un premier signal analogique, correspondant à une première forme d'onde sonore, à un premier accès audio (41) ; et
un second canal audio destiné à délivrer un second signal analogique, correspondant à une seconde forme d'onde sonore, à un second accès audio (43).
un moyen destiné à mélanger, les uns avec les autres, la pluralité de signaux analogiques pour délivrance à l'accès audio (41, 43).
un bus de données ;
un bus d'adresse ;
un décodeur d'adresse de registre connecté audit bus d'adresse, ladite sortie de décodeur fournissant une pluralité de signaux d'impulsion de cadencement de validation individuels ;
un circuit sérialiseur d'accès DMA destiné à prendre une pluralité de demandes d'accès DMA et à les sortir en ordre sériel de réception ;
une pluralité de registres d'états d'interruption connectés audit bus de données et connectés pour recevoir lesdits signaux d'interruption de système ;
un circuit de commande d'interruption connecté à ladite pluralité de registres d'états d'interruption, ledit circuit d'interruption fournissant une sortie de code d'interruption de type microprocesseur ;
un accès de canal audio gauche ;
un accès de canal audio droit ;
un accès de disque ;
un accès d'UART (circuit émetteur/récepteur universel asynchrone) ;
au moins l'un d'une pluralité d'accès identiques de potentiomètre ;
un circuit de commande et d'interface d'UART connecté pour recevoir des données dudit bus de données et pour envoyer des données audit bus de données, et connecté pour envoyer une information reçue par ledit accès d'UART, ledit circuit de commande et d'interface d'UART comportant une connexion pour recevoir certains desdits signaux de validation dudit décodeur d'adresse de registre ;
au moins un circuit de commande et d'interface de potentiomètre connecté pour recevoir des données dudit bus de données et pour envoyer des données audit bus de données, et connecté pour alimenter et gérer le niveau de signal audit accès de potentiomètre, ledit circuit de commande et d'interface de potentiomètre comportant une connexion pour recevoir certains desdits signaux de validation dudit décodeur d'adresse de registre, ledit transfert de données par ledit bus de données étant ainsi commandé ;
un circuit de commande et d'interface de canal audio gauche connecté pour recevoir des données dudit bus de données et pour envoyer des signaux audio audit accès de canal audio gauche, ledit circuit de commande et d'interface de canal audio gauche comportant une connexion pour recevoir certains desdits signaux de validation dudit décodeur d'adresse de registre, ledit transfert de données par ledit bus de données étant ainsi commandé, et comportant une connexion avec ledit circuit sérialiseur d'accès DMA pour demander des données de canal audio gauche audit bus de données ;
un circuit de commande et d'interface de canal audio droit connecté pour recevoir des données dudit bus de données et pour envoyer des signaux audio audit accès de canal audio droit, ledit circuit de commande et d'interface de canal audio droit comportant une connexion pour recevoir certains desdits signaux de validation dudit décodeur d'adresse de registre, ledit transfert de données par ledit bus de données étant ainsi commandé, et comportant une connexion avec ledit circuit sérialiseur d'accès DMA pour demander des données de canal audio droit audit bus de données ; et
un circuit de commande et d'interface de disque connecté pour envoyer et recevoir des données par ledit bus de données, ledit circuit de commande et d'interface de disque comportant une connexion pour recevoir certains desdits signaux de validation dudit décodeur d'adresse de registre, ledit transfert de données par ledit bus de données étant ainsi commandé, ledit circuit de commande et d'interface de disque étant connecté pour envoyer et recevoir de l'information par ledit accès de disque, et comportant une connexion pour recevoir certains desdits signaux de validation dudit décodeur d'adresse de registre, ledit transfert de données par ledit bus de données étant ainsi commandé, ledit circuit de commande et d'interface de disque étant connecté pour envoyer et recevoir de l'information par ledit accès de disque et comportant une connexion avec ledit circuit sérialiseur d'accès DMA pour demander des données de disque audit bus de données.