Method of using a semiconductor device comprising a substrate having a dielectrically isolated semiconductor island

Description

FIELD OF THE INVENTION

[0001] The present invention relates to a method of using a semiconductor device, said semiconductor device comprising a semiconductor substrate having a dielectrically isolated island region.

BACKGROUND OF THE INVENTION

[0002] Dielectrically isolated island structures are commonly employed in integrated circuit architectures for supporting a variety of circuit components, such as bipolar transistor devices, junction field effect devices, DMOS circuits, etc. In a typical (NPN) bipolar configuration, shown in Figure 1, a high impurity concentraton (N+) buried subcollector region (11) is formed at the bottom of an island (e.g. silicon) region (10) that is dielectrically isolated from a support substrate (12) (e.g. silicon) by means of a layer of insulator material (e.g. silicon oxide) (14) therebetween. The thickness of subcollector region (11) may be on the order of five to fifteen µm (microns), depending on how heavily doped it is and to what magnitude of Dt product it is subjected during wafer processing. The thickness of the N- island (10), in the upper surface of which a P base region (15), an N+ emitter region (16) (formed in base region 15) and an N+ collector contact region (17) are formed, must be sufficiently large to support the base-collector depletion region layer without causing the peak field in the depletion layer to exceed the field at which the transistor goes into collector-emitter breakdown with the base open circuited, BVCEO. For a 100V BVCEO NPN device having an HFE of 400, an N-thickness beneath the base, on the order of ten µm, is required. The minimum resistivity for such a device is about 10 ohm·cm. With a collector-base junction depth in the range of two to eight µm, minimum island thickness will therefore be relatively large (on the order of 22 µm) and therefor costly to manufacture.

[0003] The large size of such thick islands is also due to the fact that their sidewalls are sloped or inclined as a result of the application of an anisotropic etchant through a photolithographic mask the size of which defines the bottom of the island. The minimum front surface dimension of the finished island cannot be less than the minimum bottom dimension plus two times cot a times the island thickness, where a is the angle between the island sidewall and the island surface. This angle for typical dielectric isolation fabrication techniques using 〈100〉 oriented wafers is on the order of 55 degrees. As a consequence, in the case of the above-referenced island having a minimum thickness of 22 µm, the minimum island width will be 31 µm, plus a minimum bottom dimension on the order to 10 µm, yielding a minimum lateral island dimension of 41 µm for a 100V buried layer NPN transistor. As this width is considerably greater than that normally attributed to small components, it effectively represents wasted space.

[0004] In laid-open publication JP 58-171856 (A) a semiconductor integrated circuit device wherein dv/dt strength is improved by reducing the collector resistance of a npn bipolar transistor by forming within an island forming n-type single crystal Si region a n⁺ low resistance layer. Within this low resistance layer a n⁺⁺-type collector layer and laterally spaced therefrom a p-type base layer are formed. Within the base layer a n⁺⁺ emitter layer is formed.

[0005] In patent publication US 4,232,328 a semiconductor device structure with dielectrically isolated integrated circuit complementary bipolar transistors disposed in dielectrically isolated islands for high voltage use is disclosed. In this structure the substrate supporting the islands can be biased with positive as well as negative voltages to modify current flour direction of the transistors.

[0006] It is thus the problem underlying the present invention to provide for a method of using a semiconductor device with an improved high breakdown transistor structure formed in a thin dielectrically isolated region while retaining a low collector (or drain) resistance.

SUMMARY OF THE INVENTION

[0007] This problem is solved by providing a method of using a semiconductor device having the features of claim 1.

[0008] In accordance with the present invention, a dielectrically isolated island structure is provided, in which the impurity concentration of the island region is tailored to provide a region of reduced resistance for providing a low resistance current path from an island location directly beneath the base region to the collector contact, and the potential of the support substrate is established at a value which is less than the maximum collector voltage, so that the portion of the collector (island) directly beneath the base is depleted of carriers prior to the electric field at that location reaching the value that causes BVCEO breakdown, so as not to effectively reduce BCVEO. Since the support substrate bias potential depletes some of the region of the island beneath the base region of carriers, the doping of the island can be increased compared to the case where the substrate is not biased, while maintaining the electric field at this location less than the BVCEO field.

[0009] More particularly, a bipolar transistor structure is formed within a dielectrically isolated island region in a support substrate by forming a base region in a first surface portion of the island region, such that the semiconductor material of the island region extends beneath the base region and thereby separates a bottom portion of the base region from the bottom of the island region.

[0010] The support substrate may surround the dielectrically isolated island or may be configured as a semiconductor (silicon) on insulator architecture in which a channel of conductive (doped polysilicon) material dielectrically isolated from both the substrate and the island region is disposed adjacent to (the side surfaces of) the island region. The polysilicon channel may be biased at a voltage different from that of the substrate, because its bias does not influence the region beneath the base (as it is not a boundary to that region). As a consequence, unlike the depletion region-control substrate bias, the voltage applied to the polysilicon channel is not to be constrained.

[0011] An emitter region is formed in the base region and a collector contact is formed in a surface portion of the island region spaced apart from the base region. The impurity concentration of the island collector region is greater at its interface with the base region than at the bottom portion of the island, so as to provide a low collector resistance path through the collector from a location immediately beneath the base to the collector contact. In addition, the substrate is biased at a potential, relative to the potential of the collector island region, such that, in the presence of a voltage bias differential applied between the island region and the base, that portion of the collector region which extends beneath the base region and separates the bottom of the base from the bottom of the island region is depleted of carriers prior to the occurrence of a breakdown voltage field between the collector island region and the base.

[0012] Tailoring of the impurity concentration of the island region at its interface with the base region may be accomplished by introducing (ion implantation, diffusion) of impurities into the surface of the island region to form a higher (than the island) impurity region that extends from the surface of the island to a depth some defined distance deeper than the depth of the base, so that it extends beneath the bottom of the base region and above the bottom of the lower impurity concentration island region. The tailored doping may also extend completely through the island region, so that the island region acquires a graded impurity concentration profile decreasing from the surface of the island region and extending to a depth (e.g. its entire thickness) deeper than the depth of the base region. Again, the lowest impurity concentration of the collector island region occurs beneath the bottom of the base region.

[0013] Where a lower reduction in collector resistance can be tolerated as a tradeoff for purposes of gaining flexibility in choice of island thickness for a given BVCEO, the depth of the impurity concentration-tailoring region may be less than that of the base region, so that it terminates at a side portion of the base region.

[0014] Reduced collector resistance may also be achieved by forming a semiconductor guard region of the same conductivity type as the base region, contiguous with and having a depth greater than that of the base region, so that the guard region effectively interrupts any surface path through tie island to the collector contact region. The substrate is biased at potential, relative to that of the island region, such that a portion of the island region which extends beneath the base and separates the bottom of the base region from the bottom of the island region is depleted of carriers prior to the occurrence of a breakdown voltage field between the collector island region and the base region in the presence of a voltage bias differential applied between the island region and the base.

[0015] The deep guard region may be formed in the shape of a ring, contiguous with the lateral perimeter of the base, or it may be contiguous with one end of the base and extend across the width of the island region so as to intersect dielectric material through which the island region is dielectrically isolated from the substrate. Additionally, as already disclosed above, an impurity concentration-tailoring region may be provided.

[0016] Furthermore, the above-described impurity concentration-tailoring region may be employed to reduce the resistance of the drain-drift region of a DMOS structure. In such a structure, the island region acts as the drain, with the channel being formed in a surface body region of opposite conductivity type with respect to the island. A drain contact region is formed in a surface portion of the island region spaced apart from the channel region. The source region is formed in the opposite conductivity type surface body region containing the channel. Overlying the channel is a gate insulator layer, the gate metal itself overlapping the source and island regions between which the channel is defined.

[0017] As in the bipolar transistors disclosed above, the resistance-reducing region extends from the surface of the island to some defined distance deeper than the depth of the channel-containing body region, so that it extends beneath the bottom of the channel-containing body region and above the bottom of the lower impurity concentration island region. Again, the lowest impurity concentration of the island region occurs beneath the bottom of the body region. The support substrate is biased at a voltage less than the drain voltage, so that the island region between the body region and the underlying support substrate becomes totally depleted of carriers before the breakdown field is reached in that region.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] 

Figure 1 diagrammatically illustrates the device structure of a conventional dielectrically isolated island region containing an NPN bipolar transistor having a high impurity concentration (N+) buried subcollector region;

Figure 2 diagrammatically illustrates a semiconductor device having a dielectrically isolated island containing an NPN bipolar transistor structure, to explain the present invention;

Figure 3 shows the incorporation of the device of Figure 2 into an SOI architecture;

Figure 4 shows a modification of the device in Figure 2, in which the depth of the impurity concentration-tailoring region is less than that of the base region;

Figure 5 shows a further semiconductor device having a deep semiconductor guard region contiguous with the base region, to explain the present invention;

Figure 6 is a sectional perimeter of a version of the further semiconductor device having a deep guard region; and

Figure 7 shows an arrangement for reducing the resistance of the drain-drift region of a DMOS structure, to explain the present invention.

DETAILED DESCRIPTION

[0019] Referring now to Figure 2 a first device to explain the present invention is shown as comprising a bipolar (e.g. NPN) transistor structure 20 formed within an (N type silicon) island region 21 dielectrically isolated from a (silicon) support substrate 12 by means of an (oxide) insulator layer 14 at the bottom 22 and sidewalls 24 of island region 21. (It should be noted that the invention is not limited to using a particular polarity type of device, an NPN structure being shown and described merely as an example.) As in the prior art configuration shown in Figure 1, discussed above, transistor 20 contains a (P type) base region 15 disposed in a first surface portion of N island region 21, such that the semiconductor material of island region 21 extends beneath the bottom 25 of base region 15 and thereby separates the bottom 25 of the base region from the bottom 22 of the island region.

[0020] Support substrate 12 may surround dielectrically isolated island 21, as shown in Figure 2, or it may be configured as a semiconductor (silicon) on insulator architecture, diagrammatically illustrated in Figure 3 as having a channel 31 of conductive (doped polysilicon) material disposed adjacent to (the side surfaces of) island region 21 and dielectrically isolated from both substrate 12 and island region 21 by insulator layer 34. Polysilicon channel 31 may be biased at a voltage different from that of substrate 12, so that its bias does not influence that portion of island region 21 beneath base 15 (as the channel is not a boundary to that region). As a consequence, the voltage applied to the polysilicon channel need not be constrained.

[0021] NPN transistor 20 further includes an N+ emitter region 16 formed in a surface portion of base region 15, and an N+ collector contact region 17 formed in a surface portion of the island region spaced apart from base region 15 by a separation region 18 therebetween. In the devices illustrated in Figures 2 and 3, and unlike the prior art architecture of Figure 1, an upper (N type) portion 23 of island region 21, which extends from the top surface 27 of the island to a depth beneath the bottom 25 of base region 15, has an impurity concentration which is greater at its interface with the base region than a lower (N- type) portion 26 adjacent to the bottom 22 of the island. Region 23 may be formed (by ion implant, diffusion) non-selectively, without the need for special masking, or it may be selectively introduced into only specified island regions within substrate 12, as required by a particular design.

[0022] As described previously, this relatively higher impurity concentration of upper portion 23 provides a low collector resistance path through the (collector) island from a location 41 within the collector island beneath that portion of base region 15 which underlies emitter region 16 through the N type material of the upper portion 23 of the island to collector contact region 17. Normally, at a given collector voltage, this region of increased doping would cause a higher electric field (resulting in a lower BVCEO) in the base-collector depletion layer that is formed in the portion 45 of island region 21 beneath base region 15 than would occur in the absence of the increased doping. This unwanted decrease in BVCEO is obviated by biasing substrate 12 at a potential, relative to the potential of the collector island region 21, such that, in the presence of a voltage bias differential applied between the island (collector) region 21 and emitter region 16, that portion 45 of the collector island region 21 which extends beneath base region 15 and separates the bottom 25 of the base from the bottom 22 of the island region 21 becomes depleted of carriers prior to the occurrence of a breakdown voltage field between the collector island region 21 and emitter region 16. Namely, because of the application of a substrate bias, that portion 41 of the region 45 beneath the base becomes depleted of carriers, so that its doping may be increased to a higher concentration than would be possible in the absence of a substrate bias, while maintaining the electric field at that location at less than the BVCEO field. When portion 45 of the collector island region 21 beneath base 15 is fully depleted by the combined action of the substrate bias and reverse base-collector junction bias prior to reaching the breakdown field, the collector voltage may be increased further until a breakdown field is reached in a lateral portion of the base-collector junction (away from region 45).

[0023] As pointed out above, and as depicted in the devices of Figures 2 and 3, the tailoring of the impurity concentration profile of island region 21 for providing a reduced resistance path between the base and the collector contact region 17 may be accomplished by introducing (ion implantation, diffusion) impurities into the upper surface 27 of the island region 21, so that higher (than the island) impurity concentration region 23 extends from the upper surface 27 of the island to a location some defined distance deeper than the depth of base region 15, whereby region 23 extends beneath the bottom 25 of the base region, yet still leaving a lower N- portion 26 of increased resistivity adjacent to the bottom 22 of island region 21.

[0024] This tailored doping may also extend completely through the island region, so that the island region acquires a graded impurity concentration profile decreasing from upper surface 27 and extending to bottom 22 of island region. Again, the upper part of the island will be more heavily doped, so that the lowest impurity concentration of the collector island region occurs beneath the bottom of the base region.

[0025] Where a lower reduction in collector resistance can be tolerated as a tradeoff for purposes of gaining flexibility in choice of island thickness for a given BVCEO, the depth of the impurity concentration-tailoring region 23 may be relatively shallow or less than that of base region 15, so that it terminates at a side portion 51 of the base region, as illustrated in the device of Figure 4.

[0026] In accordance with a further device to explain the invention, diagrammatically illustrated in Figure 5, reduced collector resistance is achieved by forming a deep semiconductor guard region 61 of the same conductivity type as, contiguous with and having a depth in collector island region 21 greater than that of base region 15, so that the deep guard region 61 effectively interrupts any surface path from that portion 41 of the collector island 21 underlying the emitter region 16 to collector contact region 17. Substrate 12 is biased at a voltage which is less than the collector voltage, such that the combined action of the base-collector bias and the substrate bias depletes that portion 65 of island region 21 between the bottom 63 of deep guard region 61 and the bottom 22 of island region 21 of carriers prior to the occurrence of a breakdown voltage field between the collector island region and the base region. Once a depletion region has been formed between the substrate and deep guard region 61, a further increase in the base-collector voltage will cause little change in the field underlying the emitter region 16 (namely within the confines of the deep P type guard region, due to the screening action of the depletion region). As a consequence, collector-to-emitter voltage can be increased further, thereby achieving a higher BVCEO than would otherwise be obtainable in a collector of the same doping and thickness.

[0027] To provide such a surrounding screen, deep guard region 61 may be formed in the shape of a ring contiguous with the lateral perimeter of the base, as indicated in Figure 5. It may also be formed so as to be contiguous with one end of base region 15 and extend across the width of the island region 21, so as to intersect dielectric material 14 through which the island region is dielectrically isolated from the substrate 12, as shown by the sectional perspective illustration of Figure 6. Collector resistance is kept low because thicker or more heavily doped islands (which have lower collector resistance) can be used to achieve the desired BVCEO due to the deep P screening effect.

[0028] In addition, this further device may be augmented by the introduction of the impurity concentration-tailoring region 23, described above. Preferably, N region 23 is no deeper than guard region 61, as shown in broken lines in Figures 5 and 6, so that a depletion region is formed between the guard region 61 and the substrate 12 at the lowest possible voltage.

[0029] In accordance with another device to explain the invention, the above-described impurity concentration-tailoring region may be employed to reduce the resistance of the drain-drift region of a DMOS structure, diagrammatically illustrated in Figure 7 as comprising additional surface insulator and gate electrode structure. More particularly, in the DMOS device shown in Figure 7, N island region 21 acts as the drain, having an N+ surface drain contact region 71. A channel-containing P type body region 72 is formed in a surface portion of the island spaced apart from the drain contact 71. An N+ source region 74 is formed in a surface portion of body region 72 so as define the width of the channel region 75 between the island 21 and the body region 72. Overlying the channel is a thin gate insulator (oxide) layer 81. A layer of gate conductor material (e.g. doped polysilicon, metal) 82 is formed on the gate insulator layer and overlaps the source region 74 and island region 21, so as to extend over channel region 75.

[0030] As in the bipolar transistors described above, a (drain drift) resistance-reducing region 83 extends from the top surface 84 of the island to some defined distance deeper than the depth of the channel-containing body region 72, so that it extends beneath the bottom 76 of the channel-containing body region and above the bottom 22 of the lower impurity concentration island region. Again, the lowest impurity concentration of the island region occurs beneath the bottom of the body region. The support substrate is biased at a voltage less than the drain voltage, so that the island region between the body region and the underlying support substrate becomes totally depleted of carriers before the breakdown field is reached in that region.

[0031] In each of the foregoing devices, biasing of the substrate 12 may be accomplished by means of an ohmic contact to the substrate or by a non-mechanical coupling mechanism, as long as the substrate assumes a voltage less than the voltage of the collector (island), so that the region between the base (or channel body in the case of a DMOS device), and the substrate is fully depleted before a breakdown field is reached. Such non-contact biasing of the substrate may be effected by leakage current equalization (net current to the substrate must be zero) or capacitive coupling. Either technique will establish a substrate bias that is intermediate the most negative and most positive voltages applied to the integrated circuit.

[0032] As will be appreciated from the foregoing description of the present invention, the considerable occupation area (and thickness) of transistor structures that achieve low collector resistance by means of a buried subcollector region at the bottom of the island is substantially reduced by means of a thin dielectrically isolated island structure, in which the impurity concentration of the reduced thickness island region is tailored to provide a region of reduced resistance for providing a low resistance current path from an island location directly beneath the emitter region to the collector contact. In accordance with the present invention, the potential of the support substrate is established at a value which is less than the collector voltage, so that the portion of the collector (island) directly beneath the emitter projection onto the base is depleted of carriers prior to the electric field at that location reaching BVCEO, so as not to effectively reduce BVCEO. Since the support substrate bias potential depletes some of the region of the island beneath the base region of carriers, the doping of the island can be increased compared to the case where the substrate is not biased, while maintaining the electric field at this location less than the BVCEO field.

Claims

1. A method of using a semiconductor device, said semiconductor device comprising a semiconductor substrate (12) having a dielectrically isolated island region (21) of semiconductor material of a first conductivity type, a first semiconductor region (15, 72) of a second conductivity type, opposite to said first conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said first conductivity type of said island region extends beneath said first semiconductor region and thereby separates a bottom portion (25, 76) of said first semiconductor region from a bottom portion (22) of said island region, and wherein the impurity concentration of said island region is greater at a portion of the an interface of said island region with said first semiconductor region than at said bottom portion of said island region, and a second semiconductor region (17, 71) of said first conductivity type, formed in a first surface portion of said first semiconductor region;
wherein said method comprises

applying a bias voltage to said substrate (12) relative to the potential of said island region (21), such that a portion (41, 45) of said island region (21) which extends beneath said first semiconductor region (15, 72) and separates a bottom portion (25, 76) of said first semiconductor region from a bottom portion (22) of said island region is depleted of carriers prior to the occurrence of a breakdown voltage field between said island region and said first semiconductor region in the presence of a reverse voltage bias differential between said island region and said first semiconductor region.

2. A method according to claim 1, wherein an upper portion (23, 83) of the island region extending from the top surface of the island region to deeper than the first semiconductor region with respect to said top surface and including said portion of the interface of said island region with the first semiconductor region has an impurity concentration such that the lowest impurity concentration of the island is beneath said upper portion, including the bottom portion of said island region.

3. A method according to claim 1, wherein an upper portion (23, 83) of the island region extending from the top surface of the island region to shallower than the first semiconductor region with respect to said top surface and including said portion of the interface of said island region with the first semiconductor, said portion adjoining a side portion of the first semiconductor region, has an impurity concentration such that the lowest impurity concentration of the island is beneath said upper portion, including the bottom portion of said island region.

4. A method according to claim 2 or 3, wherein the upper layer has furthermore a graded impurity concentration profile decreasing from the surface of the island region.

5. A method according to claim 4 depending on claim 2, wherein the entire thickness of said island region is graded.

6. A method according to one of claims 2 to 5, wherein a semiconductor guard region (61) of said second conductivity type and having a depth greater than that of said first semiconductor region (15, 72) is contiguous with said first semiconductor region.

7. A method according to claim 6 depending on one of claims 2, 4, and 5, wherein said semiconductor guard region (61) of said second conductivity type has a depth greater than that of said first, upper portion (23) of said island region.

8. A method according to claim 6 or 7, wherein said further semiconductor guard region (61) is formed in the shape of a ring, contiguous with the lateral perimeter of said first semiconductor region.

9. A method according to one of claims 1 to 8, further having a channel (31) of material dielectrically isolated from said substrate (12) and said island region (21), disposed adjacent to said island region.

10. A method according to claim 9, wherein said channel (31) of material is biased at a first bias voltage and said substrate (12) is biased at a second bias voltage, which is different from the first bias voltage biasing the channel.

Ansprüche

1. Verfahren zur Verwendung eines Halbleiterbauelements, wobei das Halbleiterbauelement ein Halbleitersubstrat (12) mit einem dielektrisch isolierten Inselbereich (21) aus Halbleitermaterial eines ersten Leitfähigkeitstyps, einen ersten Halbleiterbereich (15, 72) eines dem ersten Leitfähigkeitstyp entgegengesetzten, zweiten Leitfähigkeitstyps, der in einem ersten Oberflächenteil des Inselbereichs derart ausgebildet ist, daß sich das Halbleitermaterial des ersten Leitfähigkeitstyps des Inselbereichs unter den ersten Halbleiterbereich erstreckt und dadurch einen unteren Teil (25, 76) des ersten Halbleiterbereichs von einem unteren Teil (22) des Inselbereichs trennt, wobei die Störstellenkonzentration des Inselbereichs in einem Teil der Grenzfläche des Inselbereichs zu dem ersten Halbleiterbereich größer als in dem unteren Teil des Inselbereichs ist, und einen zweiten Halbleiterbereich (17, 71) des ersten Leitfähigkeitstyps beinhaltet, der in einem ersten Oberflächenteil des ersten Halbleiterbereichs ausgebildet ist;
wobei das Verfahren beinhaltet:

Anlegen einer Vorspannung an das Substrat (12) relativ zu dem Potential des Inselbereichs (21) derart, daß ein Teil (41, 45) des Inselbereichs (21), der sich unter den ersten Halbleiterbereich (15, 72) erstreckt und einen unteren Teil (25, 76) des ersten Halbleiterbereichs von einem unteren Teil (22) des Inselbereichs trennt, vor dem Auftreten eines Durchbruchspannungsfelds zwischen dem Inselbereich und dem ersten Halbleiterbereich bei Vorhandensein eines Vorspannungsunterschieds in Sperrrichtung an Ladungsträgern verarmt ist.

2. Verfahren nach Anspruch 1, wobei ein oberer Teil (23, 83) des Inselbereichs, der sich von der Oberseite des Inselbereichs tiefer als der erste Halbleiterbereich bezüglich der Oberseite erstreckt und den Teil der Grenzfläche des Inselbereichs zu dem ersten Halbleiterbereich beinhaltet, eine Störstellenkonzentration derart aufweist, daß die geringste Störstellenkonzentration der Insel unterhalb des oberen Teils liegt, einschließlich des unteren Teils des Inselbereichs.

3. Verfahren nach Anspruch 1, wobei ein oberer Teil (23, 83) des Inselbereichs, der sich von der Oberseite des Inselbereichs weniger tief als der erste Halbleiterbereich bezüglich der Oberseite erstreckt und den Teil der Grenzfläche des Inselbereichs zu dem ersten Halbleiter beinhaltet, wobei der Teil, der an einen Seitenteil des ersten Halbleiterbereichs angrenzt, eine Störstellenkonzentration derart aufweist, daß die geringste Störstellenkonzentration der Insel unterhalb des oberen Teils liegt, einschließlich des unteren Teils des Inselbereichs.

4. Verfahren nach Anspruch 2 oder 3, wobei die obere Schicht des weiteren ein gradiertes Störstellenkonzentrationsprofil aufweist, das von der Oberfläche des Inselbereichs aus abnimmt.

5. Verfahren nach Anspruch 4 in Verbindung mit Anspruch 2, wobei die gesamte Dicke des Inselbereichs gradiert ist.

6. Verfahren nach einem der Ansprüche 2 bis 5, wobei ein Halbleiterschutzbereich (61) des zweiten Leitfähigkeitstyps mit einer Tiefe von mehr als jener des ersten Halbleiterbereichs (15, 72) zu dem ersten Halbleiterbereich benachbart ist.

7. Verfahren nach Anspruch 6 in Verbindung mit einem der Ansprüche 2, 4 und 5, wobei der Halbleiterschutzbereich (61) des zweiten Leitfähigkeitstyps eine Tiefe aufweist, die größer als jene des ersten, oberen Teils (23) des Inselbereichs ist.

8. Verfahren nach Anspruch 6 oder 7, wobei der weitere Halbleiterschutzbereich (61) in Form eines Rings ausgebildet ist, der an den lateralen Umfang des ersten Halbleiterbereichs angrenzt.

9. Verfahren nach einem der Ansprüche 1 bis 8, das des weiteren einen Kanal (31) aus Material aufweist, der von dem Substrat (12) und dem Inselbereich (21) dielektrisch isoliert ist und benachbart zu dem Inselbereich angeordnet ist.

10. Verfahren nach Anspruch 9, wobei der Kanal (31) aus einem Material mit einer ersten Vorspannung vorgespannt ist und das Substrat (12) mit einer zweiten Vorspannung vorgespannt ist, die sich von der ersten Vorspannung unterscheidet, welche den Kanal vorspannt.

Revendications

1. Méthode d'utilisation d'un dispositif semi-conducteur, ce dispositif semi-conducteur comprenant un substrat (12) possédant un îlot semi-conducteur à isolation diélectrique (21) et constitué d'un matériau d'un premier type de conductivité, une première zone semi-conductrice (15, 72) possédant un deuxième type de conductivité opposé au premier type de conductivité et formée d'une première portion de surface de cet îlot, de telle sorte que le matériau semi-conducteur du premier type de conductivité de l'îlot se situe sous la première zone semi-conductrice en séparant ainsi la partie inférieure (25, 76) de la première zone semi-conductrice, de la partie inférieure (22) de l'îlot, et où la concentration d'impuretés de l'îlot est plus importante sur une partie d'interface située entre l'îlot et la première zone semi-conductrice que sur la partie inférieure de l'îlot, et une deuxième zone semi-conductrice (17, 71) de premier type de conductivité, formée d'une première partie de surface de la première zone semi-conductrice;
cette méthode d'utilisation comprend

l'application d'une tension polarisée sur le substrat (12), relative par rapport au potentiel de l'îlot (21), de telle manière qu'une partie (41, 45) de l'îlot (21), qui s'étend sous la première zone semi-conductrice (15, 72) et qui sépare une partie inférieure (25, 76) de la première zone semi-conductrice d'une partie inférieure (22) de l'îlot, est appauvrie en particules chargées précédemment par la présence d'un champ de décharge disruptif entre l'îlot et la première zone semi-conductrice en présence d'une tension opposée de polarisation différentielle entre l'îlot et la première zone semi-conductrice.

2. Une méthode d'utilisation conforme à la revendication 1, où une partie supérieure (23, 83) de l'îlot située entre la surface supérieure de l'îlot jusqu'à un niveau inférieur à la première zone semi-conductrice en ce qui concerne la surface supérieure de l'îlot, et incluant la partie d'interface de l'îlot avec la première zone semi-conductrice, cette partie supérieure possédant un taux de concentration d'impuretés tel que la concentration d'impuretés la plus faible se situe sous cette partie supérieure, incluant la partie inférieure de l'îlot.

3. Une méthode d'utilisation conforme à la revendication 1, où une partie supérieure (23, 83) de l'îlot située entre la surface supérieure de l'îlot jusqu'à un niveau légèrement inférieur à la première zone semi-conductrice en ce qui concerne la surface supérieure de l'îlot, et incluant la partie d'interface de l'îlot avec la première zone semi-conductrice, cette partie étant adjascente à une partie latérale de la première zone semi-conductrice, cette partie supérieure possédant un taux de concentration d'impuretés tel que la concentration d'impuretés la plus faible se situe sous cette partie supérieure, incluant la partie inférieure de l'îlot.

4. Une méthode d'utilisation conforme aux revendications 2 ou 3, où la couche supérieure présente en supplément un profil progressif de la concentration d'impuretés qui décroît en partant de la surface de l'îlot.

5. Une méthode d'utilisation conforme à la revendication 4 dépendante de la revendication 2, où toute l'épaisseur de l'îlot est progressive.

6. Une méthode d'utilisation conforme à l'une des revendications 2 à 5, où une zone semi-conductrice de protection (61) appartenant au second type de conductivité et possédant une profondeur plus importante que celle de la première zone semi-conductrice (15, 72), est adjacente à la première zone semi-conductrice.

7. Une méthode d'utilisation conforme à la revendication 6 dépendante de l'une des revendications 2, 4 et 5, où la zone semi-conductrice de protection (61) appartenant au second type de conductivité possède une profondeur plus importante que celle de la partie supérieure (23) de l'îlot.

8. Une méthode d'utilisation conforme aux revendications 6 ou 7, où la zone semi-conductrice de protection (61) possède la forme d'un anneau adjacent au périmètre latéral de la première zone semi-conductrice.

9. Une méthode d'utilisation conforme à l'une des revendications 1 à 8, et comportant en supplément un canal (31) constitué d'un matériau à isolation diélectrique par rapport au substrat (12) et à l'îlot (21), et adjacent à l'îlot.

10. Une méthode d'utilisation conforme à la revendication 9, où le canal (31) est polarisé suivant la polarisation de la tension première et le substrat (12) est polarisé suivant la tension secondaire qui est différente de la polarité de la tension primaire du canal.

Drawing