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(11) | EP 0 682 427 B1 |
| (12) | EUROPEAN PATENT SPECIFICATION |
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CORRELATION DETECTOR AND COMMUNICATION APPARATUS KORRELATIONSDETEKTOR UND NACHRICHTENGERÄT DETECTEUR DE CORRELATION ET APPAREIL DE COMMUNICATION |
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| Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention). |
TECHNICAL FIELD
[0001] The present invention relates to a correlation detector of a radio receiver in a CDMA (Code Division Multiple Access) system which carries out multiple access by using a spread spectrum in mobile communications.
[0002] In particular, the present invention relates to a CDMA synchronizing circuit that synchronizes a spreading code for despreading the received signal to a spreading code in a received signal in CDMA communications.
BACKGROUND ART
[0003] CDMA communications perform multiple access propagation by spreading information into wideband signals using spreading codes with rates higher than the rate of the information, and are roughly divided into direct sequence (DS) systems that spread modulated signals by high rate spreading codes, and frequency hopping (FH) systems. The FH system resolves each symbol into smaller elements called chips, and translates the chips into signals with different center frequency at a high speed. Since the implementation of the FH system is difficult, the DS system is generally used. The DS system recovers the original narrowband signal by despreading the wideband received input signal at a receiving end, followed by demodulation. In the despreading process, correlation detection is performed between the spreading code included in the received signal and a spreading code generated at the receiving end.
[0004] Thus, the receiver for receiving the spread signal in the DS system is usually provided with a replica (reference PN sequence) of the PN sequence (received PN sequence) in the received signal, and establishes synchronization between the reference PN sequence and the received PN sequence. Fig. 1 shows a conventional synchronization circuit using a matched filter. The received signal applied to an input terminal 10 is supplied to a memory circuit 11 with taps. The number of taps of the tapped memory circuit 11 is the same as the number of chips in a spreading code interval (that is, a processing gain PG). The outputs of the taps of the memory circuit 11 are multiplied by the reference spreading code stored in a tap coefficient circuit 13 by multipliers 12. The resultant products are summed by an integrator 14, which outputs the sum from its output terminal 16 as a correlation value 15.
[0005] Using the matched filter makes it possible to quickly establish the synchronization because the peaks of the correlation value appear at the same interval as that of the spreading code. However, since the capacity of the tapped memory circuit 11 and the number of the multipliers 12 increase in proportion to the processing gain, the power consumption of the receiver will increase with the interval of the spreading code. Therefore, the conventional synchronizing circuit is not appropriate for portable devices or mobile devices.
[0006] Using a sliding correlation detector as shown in Fig. 2 makes possible power saving and downsizing of the circuit. In Fig. 2, a received signal 21 inputted to the input terminal 10 is multiplied by a spreading code, which is generated by a spreading code replica generator 30, by a multiplier 22 to obtain the correlation between the two. The resultant product is passed through a bandpass filter (BPF) 23, followed by peak power detection by a square-law detector 24. The detected power is integrated over a fixed time (normally, ± one chip interval) by an integral-dump circuit 25. The integrated result is compared with a threshold value by a threshold value decision circuit 26 which decides that initial acquisition has been completed if the integrated result exceeds the threshold value, and proceeds to the next step (tracking mode). If the integrated result is less than the threshold value, the decision circuit 26 supplies a control voltage 28 to a voltage controlled clock generator (VCCG) 29 which slides the phase of the replica so that the phase of the spreading code generated by the spreading code replica generator 30 is shifted by 1/N chip interval (N is a natural number equal to or greater than one). The initial acquisition has been completed by repeating the processing until the synchronized point is found.
[0007] According to this method, it is necessary to integrate the spreading replica over the fixed time every time the replica is shifted by 1/N chip interval, and to detect the synchronized point in the interval of the spreading code by comparing the integrated result. This will lengthen the acquisition time, and hence, it is not appropriate for a system which requires a quick acquisition.
[0008] In addition, the conventional correlation detector presents another problem in that it provides a rather large error in maintaining (tracking) the synchronization.
[0009] Fig. 3 is a block diagram showing a conventional DLL (Delay Locked Loop) correlation detector 44. In Fig. 3, the same functional blocks are designated by the same numerals as in Fig. 2. The reference numeral 10 designates a spreaded signal input terminal, 102 designates a decided data output terminal, 111 denotes a multiplier, and 510 designates a delay circuit. The correlation detector 44 calculates correlations between the input modulated signal and code sequences formed by advancing and retarding the chip phase of the replica by 1/N, respectively. The correlated signals are passed through bandpass filters (BPFs) 53 and 54 which eliminate unnecessary high frequency components, and are detected by square-law detectors 55 and 56. The squared amplitude components are summed by an adder 57 in the opposite phase, so that an error signal voltage is obtained which indicates an amount of a phase difference. The error signal voltage is passed through a loop filter 58, and is fed back to a VCCG 29 to correct the phase of the replica code sequence. The phase advance (or retardation) time δ ranges from 0 to Tc, where Tc is the chip interval.
[0010] Applying the CDMA system to cellular communications requires high accuracy transmission power control that keeps constant base station's received levels of signals sent from all the mobile stations. The CDMA system can increase the capacity in terms of the number of subscribers per frequency band as compared with the FDMA system or the TDMA system. This is because conventional systems which employ frequency orthogonality cannot utilize the same carrier frequencies in the contiguous cells, and even space diversity systems cannot reuse the same frequencies within four cells.
[0011] In contrast with this, the CDMA system makes it possible to reuse the same carrier frequency in the contiguous cells because the signals of the other communicators are regarded as white noise. Accordingly, the CDMA system can increase the capacity in terms of the number of subscribers as compared with the FDMA system or the TDMA system. If the processing gain is pg, the number of spreading code sequences that completely orthogonalize with each other is pg. This number of the code sequences, however, will be insufficient when information data is spread by using only code sequences of one symbol interval long. To overcome this problem, the number of the spreading codes is increased almost infinitely by superimposing long code sequences of a very long interval over short code sequences of one symbol interval.
[0012] Unlike M sequences that have definite autocorrelation characteristics, the autocorrelation of Gold sequences and that of the sequences obtained by superimposing very long code sequences over the Gold sequences will have undesired peaks of considerable amplitudes in addition to the normal correlation peak in one symbol interval. As a result, when the received signal level is low, a lock may be lost in the conventional delay-locked loop using one chip interval lock. Let us formulate the operation principle of the delay-locked loop of Fig. 3. First, the input signal is expressed by the following equation.
where S is average signal power, c(t-τt) is a received spreading code including a propagation delay, m(t-τt) represents data modulation including the propagation delay, ω0 is the angular frequency of a carrier, and θ(t) = θ0 + Ω0t is an unknown carrier phase which is represented as the sum of a constant term and a term proportional to the Doppler frequency. The power spectrum density of n(t) is N0/2. δω0 is an angular frequency error between the center frequency of a modulation signal and a local oscillation frequency. In addition, the bandpassed expression of input thermal noise ni(t) is given by
where NC(t) and NS(t) are assumed to be approximately and statistically independent and steady. The spreading replica sequence of the advanced phase and that of the retarded phase can be expressed as follows:
where τ̂t is a propagation delay estimated by the DLL at the receiving side. The crosscorrelation output of the phase detector is expressed as
where Km is the gain of the phase detector which is assumed to be equal in both branches, and
represents the average of a set.
[0013] Figs. 4A - 4B illustrate the autocorrelation outputs in terms of the received chip phase error. Here,
is a normalized propagation delay error. H(s) is a lowpass expression of a transfer function H(s) of the bandpass filter, and
is a process of a PN sequence.
[0014] The output of the square-law detector can be expressed as follows using RPN±(x) which is a function obtained by shifting the autocorrelation function of PN by a time period of +x.
where
Here, H/(p)×(t) expresses an output response of the BPF to x(t). If the bandwidth BL is sufficiently smaller than the chip rate, the effect of the auto-noise caused by the PN sequence on the loop is negligible in the first-order approximation. Neglecting the auto-noise and the secondary harmonic caused by the square-law detection, the input to the loop filter can be expressed by the following equation.
where
According to the foregoing, a normalized delay estimate of the output of the spreading code replica generator is expressed by the following equation using e(t).
where F(s) is the transfer function of the loop filter, and KVCC is the gain of a voltage controller in the VCCG which drives the PN sequence generator. Placing K = Km2 KVCC, K represents the loop gain. Substituting equation (7) into (8),
Thus, estimated error εt is expressed as
[0015] Resolving the first term in the blanket of the above equation into an average value term and modulated auto-noise term gives
where < > expresses an average in time, and
where Sm(f) is a power spectrum density of the data modulation. The M2 term is the integral of the data modulation power spectrum density over the passband of the filter, and indicates the data modulation power in the passband. Since the bandwidth of the loop is much smaller than the data symbol rate, the auto-noise associated with the second term of equation (11) is negligible.
[0016] From equation (10), the following equation is obtained.
where a dot placed over characters represents a time differential, and η is given by
[0017] Briefly, the average of squared tracking jitter due to noise component is expressed as follows:
where BL is an equivalent noise bandwidth of the LPF, and Ne(t) is expressed as
where f(εt) represents a square-law detection curve.
[0018] Since the conventional DLL uses the square-law detector as shown in equation (15), the noise component is also squared. This will increase the tracking jitter as shown in equation (14).
[0019] A paper entitled "A Modified PN Code Tracking Loop" by Yost et al (IEEE Transactions on Communications, Vol. Com-30, No. 5, May 1982) describes a non coherent PN code tracking loop where, instead of using the sum channel as the reference, the on time or data channel is utilised.
[0020] US patent 4468784 describes a mixer driver circuit in a code correlator for a spread spectrum communications system. The mixer driver circuit simultaneously multiplies an input RF signal with two phase offset digitally encoded bit streams.
[0021] US patent 4841544 describes a spread spectrum receiver which converts a received signal into an IF signal centred about a frequency corresponding to the code fundamental frequency offset by a Doppler shift. The IF signal is then digitised and sampled at a local clock frequency to develop N-bit digital signals. In phase and quadrature component signals are then derived from the digitised IF signals. The tracker uses the component signals to track the Doppler shift, to maintain the local sampling frequency and to maintain the local code generator in synchrony with the code of the received signal.
DISCLOSURE OF THE INVENTION
[0022] Therefore, an object of the present invention is to provide a low power consumption CDMA synchronising circuit capable of high speed synchronisation. Another object of the present invention is to provide a correlation detector that can perform high accuracy tracking capable of eliminating the square loss resulting from the emphasis of the noise component by the square law detector, which differs from the conventional code tracking circuit.
A first aspect of the invention provides a synchronising apparatus including a correlation detector for maintaining synchronisation between a received signal and a despreading code by using a correlation between the received signal and the despreading code, the received signal being CDMA spread and the despreading code being used for despreading the received signal, said correlation detector comprising: a spreading code replica generating means for generating a phase advanced replica of a CDMA spreading code with an advance phase and a phase retarded replica of the CDMA spreading code with a retarded phase with respect to the received signal; first multiplying means for multiplying said received signal by said phase advanced replica of the CDMA spreading code so as to output a first correlation detection signal; and second multiplying means for multiplying said received signal by said phase retarded replica of the CDMA spreading code so as to output a second correlation detection signal; the apparatus being characterised in that it comprises: carrier frequency error compensating means for compensating for a carrier frequency error associated with said first and second correlation detection signals; and adding means for summing in opposite phase said first and second correlation detection signals, which have been compensated by said carrier frequency error compensating means; an averaging circuit for averaging an output signal of said adding means along a time axis; and wherein said spreading code replica generating means is further operable to generate an in phase replica of said CDMA spreading code with the same phase, and wherein the correlation detector further comprises: third multiplying means for multiplying said received signal by said in-phase replica of the CDMA spreading code from said spreading code replica generating means; integrating circuit means for integrating an output signal of said third multiplier means; automatic frequency control circuit means for detecting the carrier frequency error based on an output of said integrating circuit means, to output it to said carrier frequency error compensator; a demodulator for generating a decided signal of received data based on an output signal of said automatic frequency control circuit means; an inverse modulation circuit for inversely modulating an output signal of said averaging circuit by the decided signal of the received data; and clock generating circuits for generating a clock signal whose phase is controlled by an output from said inverse modulation circuit to control said spreading code replica generator.
[0023] A second aspect of the invention provides a synchronising method using a correlation detector for tracking between a received signal and a despreading code by the use of a correlation between the received signal and the despreading code, the received signal being CDMA spread and the despreading code being used for despreading the received signal, said method comprising the steps of: generating an in-phase replica of a CDMA spreading code with the same phase, a phase advanced replica of the CDMA spreading code with an advance phase and a phase retarded replica of the CDMA spreading code with a retarded phase with respect to the received signal; firstly multiplying said received signal by said phase advanced replica of the CDMA spreading code so as to output a first correlation detection signal; secondly multiplying said received signal by said phase retarded replica of the CDMA spreading code so as to output a second correlation detection signal; compensating for a carrier frequency error associated with said first and second correlation detection signals; summing in opposite phase said first and second correlation detection signals, which have been compensated at said carrier frequency error compensating step; averaging an output at said summing step along a time axis; third multiplying said received signal by said in-phase replica of the CDMA spreading code; integrating an output at said third multiplying step; detecting the carrier frequency error based on an output at said integrating step so as to use it at said carrier frequency error compensating step; generating a decided signal of received data based on an output at said integrating step; inversely modulating an output at said averaging step by the decided signal of the received data; and controlling a phase of a replica code to be output based on the output at said inversely modulating step.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024]
Fig. 1 is a block diagram showing a synchronizing circuit or an initial acquisition circuit of a conventional matched filter;
Fig. 2 is a block diagram showing a conventional sliding correlator;
Fig. 3 is a block diagram showing a conventional DLL.
Figs. 4A-4C are diagrams illustrating crosscorrelation output signals in terms of a phase error of received signal;
Fig. 5 is a block diagram showing a basic arrangement of a first embodiment of a correlation detector in accordance with the present invention;
Fig. 6 is a block diagram showing another basic arrangement of the first embodiment of a correlation detector in accordance with the present invention;
Fig. 7 is a block diagram showing details of hardware of the correlation detector in accordance with the present invention; and
Fig. 8 is a block diagram showing another embodiment of a correlation detector in accordance with the present invention.
BEST MODE FOR CARRYING OUT THE INVENTION
[0025] The best mode for carrying out the invention will now be described with reference to the accompanying drawings.
EMBODIMENT 1
[0026] Fig. 5 shows an embodiment of the present invention. A received signal 21 applied to the input terminal 10 is selectively supplied through a switching circuit 42 to an initial acquisition circuit 43 consisting of a matched filter or to a correlation detector 44. The initial acquisition circuit 43 has an arrangement similar to that of Fig. 1. The correlation detector 44 has a function similar to the correlation detectors of Figs. 2 and 3. When the initial acquisition has not yet been completed, the received signal is supplied to the initial acquisition circuit (matched filter) 43 in accordance with a switching signal 46 from an acquisition decision circuit 45, so that the correlation detection is performed. The correlation value detected by the matched filter 43 is compared with a threshold value in the acquisition decision circuit 45. If the correlation value is greater than or equal to the threshold value, the acquisition decision circuit 45 decides that the initial acquisition has been completed, and changes the switching circuit 42 using the switching signal 46. Thus, the received signal is inputted to multipliers 47 and 48 in the correlation detector 44. The acquisition decision circuit 45 provides an initial reset signal 49 to a VCCG 29 and a spreading code replica generator 30.
[0027] The received signal 21 after the initial acquisition is multiplied by spreading codes 51 and 52 by the multipliers 47 and 48, the spreading codes being generated by the spreading code replica generator 30, and having phases shifted forward and backward in time by an amount T (less than one chip interval). The two products are passed through bandpass filters (BPF) 53 and 54, and are square-law detected by square-law detectors 55 and 56, in which correlation values are detected. The correlation values are summed in the opposite phase by an adder 57. The sum is passed through a loop filter 58, and becomes a control voltage of the VCCG 29. The clock signal generated by the VCCG 29 regulates the phase of the spreading code replica generator 30, tracks the synchronous point, and maintains the synchronization.
[0028] Fig. 6 illustrates an example, in which the spreading code replica generator 30I is synchronized with the outputs of the quadrature detector 62 which detects the received signal 21 applied to the input terminal 10. In this figure, portions corresponding to those of Fig. 5 are designated by the same reference numerals. Suffixes I and Q are attached to the same numerals as in Fig. 5 to represent processing circuits of the two detected outputs I and Q of the quadrature detector 62. The detected outputs I and Q are passed through lowpass filters 63 and 64, converted into digital signals by A/D converters 65 and 66, and supplied to switching circuits 42I and 42Q. The outputs of the initial acquisition circuits 43I and 43Q are square-law detected by square-law detectors 71 and 72, summed by an adder 73, and supplied to the acquisition decision circuit 45 which decides whether the initial acquisition is established or not.
[0029] A spreading code replica generator 30I in the correlation detector 44 generates an advanced spreading code 51I with an advanced phase and a retarded spreading code 52I with a retarded phase. Likewise, a spreading code replica generator 30Q generates an advanced spreading code 51Q with the advanced phase and a retarded spreading code 52Q with the retarded phase. The detected output component I outputted from the switching circuit 42I is multiplied by the advanced spreading code 51I and the retarded spreading code 52I by multipliers 47I and 48I. Likewise, the detected output component Q outputted from the switching circuit 42Q is multiplied by the advanced spreading code 51Q and the retarded spreading code 52Q by multipliers 47Q and 48Q.
[0030] The detected correlation values with the advanced spreading codes 51I and 51Q, which are outputted from the multipliers 47I and 47Q, are passed through bandpass filters (BPFs) 53I and 53Q, square-law detected by square-law detectors 55I and 55Q, and are summed by an adder 67. Similarly, the detected correlation values with the retarded spreading codes 52I and 52Q, which are outputted from the multipliers 48I and 48Q, are passed through bandpass filters (BPFs) 54I and 54Q, square-law detected by square-law detectors 56I and 56Q, and are summed by an adder 68. The outputs of the adders 67 and 68 are summed in the opposite phase by the adder 57. These operations are similar to those of Fig. 5.
[0031] According to the first embodiment, the synchronization process is separated into an initial acquisition process, and a tracking process using the correlation detector. The input PN sequence is acquired so that the phase difference between the input PN sequence and the reference PN sequence is settled within a range sufficiently smaller than ± one chip interval during the initial acquisition because the autocorrelation of the PN sequence is established only within a range of ± one chip. The tracking processing holds the phase difference between the input PN sequence and the reference PN sequence within the range.
EMBODIMENT 2
[0032] Fig. 7 is a block diagram of a correlation detector of a second embodiment. In Fig. 7, the same functional blocks are designated by the same reference numerals as in Figs. 1 - 6. As shown in Fig. 7, a signal applied to the input terminal 10 is quasi-coherent detected by a detector 104 using a local signal generated by a local oscillator 103. The local signal has a fixed frequency substantially equal to the center frequency of the modulated signal. The correlation detector includes multipliers 47 and 48 for detecting correlations between the received spreading code and replicas of the spreading code; bandpass filters 83 and 84 for extracting only correlation detection signals from the products; a carrier frequency error compensator 208 for compensating the filtered output signals with a carrier frequency error signal detected by an automatic frequency control circuit; an adder 57 for summing in the opposite phase the correlation detection signal associated with an advanced phase replica and the correlation detection signal associated with a retarded phase replica; a loop filter 58 for averaging the phase error of the correlation detection; a multiplier 111 for performing correlation detection using a replica in phase with the spreading code included in the received signal; an integral-dump circuit 112 for integrating the output signal of the multiplier 111 over M chip intervals; an automatic frequency control circuit 213 for detecting the carrier frequency error from the output signal of the integral-dump circuit to compensate the carrier frequency error; a demodulator 113 for making decision of the received data after compensating the received phase error of the signal obtained by the correlation detection; a multiplier 114 for performing inverse modulation of the decided data using the phase error signal outputted from the loop filter; a voltage controlled clock generator 29 for controlling the clock phase by the phase error signal outputted from the multiplier 114; and the spreading code replica generator 30 driven by the clock signal outputted from the voltage controlled clock generator 29.
[0033] The modulated signal, which is down-converted by the fixed oscillation frequency substantially equal to the center frequency of the modulated signal, is deprived of harmonic components, and is multiplied by the replica of the spreading code in phase with the spreading code in the modulated signal, followed by a predetermined length of time integral. Thus, correlation peaks are detected. The correlation detection signal undergoes decision by the demodulation circuit which performs coherent detection or delay detection. On the other hand, the modulated signal is multiplied by the replica of the spreading code with an advanced phase Δ with respect to the spreading code in the modulated signal, and also multiplied by the replica of the spreading code with a retarded phase Δ, thereby eliminating the harmonic components.
[0034] The error signals between the correlation associated with the advanced phase replica of the spreading code and the correlation associated with the retarded phase replica of the spreading code are added in the opposite phase by the adder 57, and its output is integrated and averaged by the loop filter 58. This results in an error voltage corresponding to the phase error between the spreading code in the received signal and the replica of the spreading code. Inverse modulation by multiplying the error voltage by the decided data outputted from the demodulator eliminates the error in the phase error signal due to the modulated signal. A delay is inserted after the phase error detection loop in order to match the absolute times of the processings of the phase error detection loop and the data decision loop.
[0035] In the conventional DLL, a despread signal includes, a phase error signal component that is a component of an error between the center frequency of the received signal and the frequency of the local oscillator of the quadrature detector. The despread signal also includes data modulation components and vestigial components of a carrier signal component. To eliminate the carrier frequency offset component and the data modulation components, the despread signal may be squared by a square-law detector. This, however, will increase noise components because they are also squared, and the noise components will be added to the chip phase error, thereby increasing phase jitter.
[0036] Accordingly, it is necessary to obviate the square-law detector to prevent the noise component from increasing. In view of this, the present embodiment eliminates the carrier frequency offset component from the despread signal by the AFC, and removes the data modulation component by inversely modulating the demodulated and detected signal into the despread signal.
[0037] Since the quasi-coherent detected signal includes a carrier offset signal, the detected signal is involved with phase rotations. Consequently, the carrier offset signal must be removed. This is achieved by detecting, by the automatic frequency control circuit 213, the offset component of the carrier signal from the correlation peaks in the data decision loop, and by correcting the two correlation detected signals of the chip phase error detection loop by the carrier offset signal in the opposite phase directions.
SUPPLEMENTS
[0038] Fig. 8 is a block diagram showing detailed hardware of the correlation detector described in the second embodiment. In this figure, the same elements are designated by the same reference numerals as in Fig. 7. In Fig. 8, the reference numerals 304 designates a 90-degree phase shifter, 65 and 66 designate A/D converters, 308 and 309 designate complex multipliers, 313 designates a delay circuit, 314 designates a complex multiplier, and 317 designates a decision circuit. The reference numeral 410 designates a carrier frequency error compensation circuit, and 416 designates an automatic frequency control circuit.
[0039] In the correlation detector, a received IF modulated signal is quadrature-detected by the quadrature detector. The quadrature-detected I and Q channel signals are deprived of harmonic components, and are converted into digital values by the A/D converters 65 and 66, followed by the correlation detection by applying complex signal processings on I (In-phase) and Q (Quadrature) components. The correlation detection is carried out by complex multiplication of the modulation spread signal by the I and Q components of the replicas of the spreading code. The two replicas of the spreading code is the same if the in-phase and quadrature components of the primary modulated signal are spread by the same spreading code.
[0040] The operation will now be described when the primary modulation is QPSK and the secondary modulation is BPSK. The data to be modulated are primary modulated independently by binary data which are independently set for I and Q channels (QPSK modulation). The I and Q channel data are spread (secondary modulated) by the same spreading codes. The input signal to the receiver is expressed by the following equation.
The signals after multiplying the input signal of equation (3) by the replicas of the spreading code at the receiver will be expressed as follows if a conventional calculation method is applied.
The chip phase error signal at the output of the loop filter is expressed by the following equation.
As shown by equation (18), since modulated signal powers of individual symbol components are multiplied by the phase error signal in the primary QPSK modulation, the primary modulated signal components can be eliminated by inversely modulating the I and Q components of the data after decision into the phase error signal.
INDUSTRIAL APPLICABILITY
[0041] As described above in detail, according to the present invention, the correlation detection during the acquisition phase which requires a high speed synchronization is carried out in the initial acquisition circuit using a matched filter, and the correlation detection during the tracking phase which requires power saving rather than high speed synchronization is performed by the sliding correlation detector. This makes it possible to achieve the high speed acquisition, and power saving during the tracking because the power consumption of the initial acquisition circuit during the tracking is negligible.
[0042] In addition, according to the present invention, since the tracking loop of the received chip phase eliminates the primary modulated signal components which are included in the phase error signal of the replica signals, components only depending on the crosscorrelation can be extracted. This makes high accuracy tracking possible.
a spreading code replica generating means (30) for generating a phase advanced replica of a CDMA spreading code with an advance phase and a phase retarded replica of the CDMA spreading code with a retarded phase with respect to the received signal;
first multiplying means (47) for multiplying said received signal by said phase advanced replica of the CDMA spreading code so as to output a first correlation detection signal; and
second multiplying means (48) for multiplying said received signal by said phase retarded replica of the CDMA spreading code so as to output a second correlation detection signal;
the apparatus being characterised in that it comprises:
carrier frequency error compensating means (208) for compensating for a carrier frequency error associated with said first and second correlation detection signals; and
adding means (57) for summing in opposite phase said first and second correlation detection signals, which have been compensated by said carrier frequency error compensating means (208);
an averaging circuit (58) for averaging an output signal of said adding means along a time axis;
and wherein said spreading code replica generating means (30) is further operable to generate an in phase replica of said CDMA spreading code with the same phase, and wherein the correlation detector further comprises:
third multiplying means (111) for multiplying said received signal by said in-phase replica of the CDMA spreading code from said spreading code replica generating means (30);
integrating circuit means (112) for integrating an output signal of said third multiplier means;
automatic frequency control circuit means (213) for detecting the carrier frequency error based on an output of said integrating circuit means (112), to output it to said carrier frequency error compensator (208);
a demodulator (113) for generating a decided signal of received data based on an output signal of said automatic frequency control circuit means (213);
an inverse modulation circuit (114) for inversely modulating an output signal of said averaging circuit (58) by the decided signal of the received data; and
clock generating circuits (115, 29) for generating a clock signal whose phase is controlled by an output from said inverse modulation circuit (114) to control said spreading code replica generator (30).
a switching circuit (42) operable to receive the received signal;
an initial acquisition circuit means (43) for receiving an output of said switching circuit and for taking a correlation between said output and a reference spreading code so as to output a correlation value;
an acquisition decision circuit means (45) connected to said initial acquisition circuit (43), for judging completion of synchronisation based on the correlation value and for outputting the judgement result to said switching circuit means (42); and wherein
said correlation detector (44) is operable to receive another output of said switching circuit means and to take a correlation between said other output and a reference spreading code generated in a spreading code replica generator incorporated therein; and
said switching circuit means (42) being operable to output a received signal to said initial acquisition circuit means (43) at the time of asynchronism while outputting a received signal to said correlation detector (44) after the completion of synchronisation based on the output of said acquisition detection circuit means (45).
an orthogonal detector (62) for orthogonally detecting the CDMA spread received signal based on two detected signals (I, Q) whose phases are orthogonal to each other;
two A/D converters (65, 66) for converting the two detected signals into digital signals, respectively, and wherein, in said correlation detector (44):
said spreading code replica generating means comprises a spreading code replica generator (30) for respectively generating an in-phase replica of the CDMA spreading code with an advance phase and a phase retarded replica of the CDMA spreading code with a retarded phase with respect to said two digital signals;
said first multiplying means comprises a first multiplier (47) for respectively multiplying said two digital signals by said phase advance replica of the CDMA spreading code so as to output two first correlation detection signals;
said second multiplying means comprises a second multiplier (48) for respectively multiplying said two digital signals by said phase retarded replica of the CDMA spreading code so as to output two second correlation detection signals;
said carrier frequency error compensating means comprises a carrier frequency error compensator (208) for compensating for respective carrier frequency errors associated with said two first and said two second correlation detection signals;
said third multiplying means comprises two third multipliers (111) for respectively multiplying said two digital signals by said in-phase replica of the CDMA spreading code from said spreading code replica generator;
said integrating circuit means comprises two integrating circuits (112) for respectively integrating output signals of said third multipliers; and
said automatic frequency control circuit means comprises an automatic frequency control circuit (213) for detecting the carrier frequency errors based on output of said two integrating circuits, to output them to said carrier frequency error compensator.
an orthogonal detector (62) for orthogonally detecting the CDMA spread received signal based on two detected signals (I, Q) whose phases are orthogonal to each other;
two A/D converters (65, 66) for converting the two detected signals into digital signals, respectively;
two switching circuits (42I, 42Q) for inputting the two digital signals, respectively;
two initial acquisition circuits (43I, 43Q) for inputting one of outputs of said two switching circuits and taking a correlation between the output and a reference spreading code so as to output a correlation value;
acquisition decision circuits (45) respectively connected to said two initial acquisition circuits, for judging completion of synchronisation based on the correlation value and for outputting the judgement result to said switching circuit; and
synchronising apparatus including a correlation detector (44) in accordance with claim 1, said correlation detector being operable to input the other output of said two switching circuits and taking a correlation between the output and a reference spreading code generated in a spreading code replica generator incorporated therein;
said two switching circuits (42I, 42Q) being operable to output a received signal to said initial acquisition circuit at the time of asynchronism while outputting a received signal to said correlation detector after the completion of synchronisation based on the output of said acquisition decision circuit; and
wherein, in said correlation detector (44),
said spreading code replica generating means (30) is operable to generate said in-phase replica, said phase advanced replica, and said phase retarded replica with respect to said two digital signals;
said first multiplying means comprises two first multipliers (47) for respectively multiplying said two digital signals by said phase advanced replica of the CDMA spreading code so as to output first correlation detection signals;
said second multiplying means comprises two second multipliers (48) for respectively multiplying said two digital signals by said phase retarded replica of the CDMA spreading code so as to output second correlation detection signals;
said carrier frequency error compensating means comprises a compensator (208) operable to compensate for respective carrier frequency errors associated with said two first and said two second correlation detection signals;
said third multiplying means comprises two third multipliers (111) for respectively multiplying said two digital signals by said in-phase replica of the CDMA spreading code from said spreading code replica generator;
said integrating circuit means comprises two integrating circuits (112) for respectively integrating output signals of said third multipliers;
and said automatic frequency control circuit means comprises an automatic frequency control circuit (213) for detecting the carrier frequency errors based on outputs of said two integrating circuits, to output them to said carrier frequency error compensator.
generating an in-phase replica of a CDMA spreading code with the same phase, a phase advanced replica of the CDMA spreading code with an advance phase and a phase retarded replica of the CDMA spreading code with a retarded phase with respect to the received signal;
firstly multiplying said received signal by said phase advanced replica of the CDMA spreading code so as to output a first correlation detection signal;
secondly multiplying said received signal by said phase retarded replica of the CDMA spreading code so as to output a second correlation detection signal;
compensating for a carrier frequency error associated with said first and second correlation detection signals;
summing in opposite phase said first and second correlation detection signals, which have been compensated at said carrier frequency error compensating step;
averaging an output at said summing step along a time axis;
third multiplying said received signal by said in-phase replica of the CDMA spreading code;
integrating an output at said third multiplying step;
detecting the carrier frequency error based on an output at said integrating step so as to use it at said carrier frequency error compensating step;
generating a decided signal of received data based on an output at said integrating step;
inversely modulating an output at said averaging step by the decided signal of the received data; and
controlling a phase of a replica code to be output based on the output at said inversely modulating step.
taking a correlation between the received signal and a reference spreading code so as to perform initial acquisition; and
taking a correlation between the received signal and the reference spreading code for tracking, after completion of the synchronisation, in accordance with the method of claim 5.
einer Spreizcodekopieerzeugungseinrichtung (30) zur Erzeugung einer in der Phase voreilenden Kopie eines CDMA-Spreizdoces mit einer voreilenden Phase und einer in der Phase nachlaufenden Kopie eines CDMA-Spreizcodes mit einer in bezug auf das empfangene Signal nachlaufenden Phase,
einer ersten Multiplikationseinrichtung (47) zur Multiplikation des empfangen Signals mit der in der Phase voreilenden Kopie des CDMA-Spreizcodes derart, dass ein erstes Korrelationserfassungssignal ausgegeben wird, und
einer zweiten Multiplikationseinrichtung (48) zur Multiplikation des empfangen Signals mit der in der Phase nacheilenden Kopie des CDMA-Spreizcodes derart, dass ein zweites Korrelationserfassungssignal ausgegeben wird,
wobei das Gerät dadurch gekennzeichnet ist, dass es aufweist:
eine Trägerfrequenzfehlerkompensationseinrichtung (208) zur Kompensation eines den ersten und zweiten Korrelationserfassungssignalen zugehörigen Trägerfrequenzfehlers, und
eine Addiereinrichtung zur Summierung, in gegenüberliegenden Phasen, der ersten und zweiten Korrelationserfassungssignale, die durch die Frequenzfehlerkompensationseinrichtung (208) kompensiert worden sind,
eine Durchschnittsbildungsschaltung (58) zur Bildung eines Durchschnitts eines Ausgangssignals der Addiereinrichtung entlang einer Zeitachse,
und wobei die Spreizcodekopieerzeugungseinrichtung (30) weiterhin zur Erzeugung eines In-Phasen-Kopie des CDMA-Spreizcodes mit derselben Phase betreibbar ist, und wobei die Korrelationserfassungseinrichtung weiterhin aufweist:
eine dritte Multiplikationseinrichtung (111) zur Multiplikation des empfangenen Signals mit der In-Phasen-Kopie des CDMA-Spreizcodes aus der Spreizcodekopieerzeugungseinrichtung (30),
einer Integrierschaltungseinrichtung (112) zum Integrieren eines Ausgangssignals der dritten Multiplikationseinrichtung,
einer automatischen Frequenzsteuerungsschaltung (213) zur Erfassung des Trägerfrequenzfehlers auf der Grundlage eines Ausgangs der Integrierschaltungseinrichtung (112), um diesen der Trägerfrequenzfehlerkompensationseinrichtung (208) zuzuführen,
einer Demodulationseinrichtung (113) zur Erzeugung eines Entscheidungssignals der empfangen Daten auf der Grundlage eines Ausgangssignals der automatischen Frequenzsteuerungsschaltung (213),
einer inversen Modulationsschaltung (114) zur inversen Modulation eines Ausgangssignals der Durchschnittsbildungsschaltung (58) durch das Entscheidungssignal der empfangenen Daten, und
Takterzeugungsschaltungen (115, 29) zur Erzeugung eines Taktsignals, dessen Phase durch einen Ausgang der inversen Modulationsschaltung (114) gesteuert wird, um den Spreizcodekopiegenerator (30) zu steuern.
eine Schalt-Schaltung (42), die zum Empfang des empfangenen Signals betreibbar ist,
einer Anfangsbeschaffungsschaltungseinrichtung (43) zum Empfang eines Ausgangs der Schalt-Schaltung und zur Vornahme einer Korrelation zwischen dem Ausgang und einem Referenzspreizcode, um einen Korrelationswert auszugeben,
einer Beschaffungsentscheidungsschaltungseinrichtung (45), die mit der Anfangsbeschaffungsschaltung (43) verbunden ist, zur Beurteilung des Abschlusses der Synchronisation auf der Grundlage des Korrelationswerts und zur Ausgabe des Beurteilungsergebnisses zu der Schalt-Schaltung (42), und wobei
die Korrelationserfassungseinrichtung (44) zum Empfang eines anderen Ausgangs der Schalt-Schaltungseinrichtung und zum Vornehmen einer Korrelation zwischen dem anderen Ausgang und einem Referenzspreizcodes betreibbar ist, der in einer darin eingebauten Spreizcodekopieerzeugungseinrichtung erzeugt wird, und
die Schalt-Schaltungseinrichtung (42) zur Ausgabe eines empfangenen Signals zu der Anfangsbeschaffungsschaltungseinrichtung (43) zum Zeitpunkt einer Asynchronisation betreibbar ist, während ein empfangenes Signal zu der Korrelationserfassungseinrichtung (44) nach dem Abschluss der Synchronisation auf der Grundlage des Ausgangs der Beschaffungserfassungsschaltungseinrichtung (45) ausgegeben wird.
eine Orthogonalerfassungseinrichtung (62) zur orthogonalen Erfassung des CDMA-gespreizten empfangen Signals auf der Grundlage zweier erfasster Signale (I, Q), deren Phasen zueinander orthogonal sind,
zwei A/D-Wandler (65, 66) zur jeweiligen Umwandlung der zwei erfassten Signale in digitale Signale, und wobei in der Korrelationserfassungseinrichtung (44)
die Spreizcodekopieerzeugungseinrichtung einen Spreizcodekopiegenerator (30) zur jeweiligen Erzeugung einer In-Phasen-Kopie des CDMA-Spreizcodes mit einer voreilenden Phase und einer in der Phase nachlaufenden Kopie des CDMA-Spreizcodes mit einer nachlaufenden Phase in bezug auf die zwei digitalen Signale aufweist,
die erste Multiplikationseinrichtung einen ersten Multiplizierer (47) zur jeweiligen Multiplikation der zwei digitalen Signale mit der in der Phase voreilenden Kopie des CDMA-Spreizcodes aufweist, um zwei erste Korrelationserfassungssignale auszugeben,
die zweite Multiplikationseinrichtung einen zweiten Multiplizierer (48) zur jeweiligen Multiplikation der zwei digitalen Signale mit der in der Phase nachlaufenden Kopie des CDMA-Spreizcodes aufweist, um zwei zweite Korrelationserfassungssignale auszugeben,
die Trägerfrequenzfehlerkompensationseinrichtung einen Trägerfrequenzfehlerkompensator (208) zur Kompensation der jeweiligen den zwei ersten und zwei zweiten Korrelationserfassungssignalen zugehörigen Trägerfrequenzfehlern aufweist,
die dritte Multiplikationseinrichtung zwei dritte Multiplizierer (111) zur jeweiligen Multiplikation der zwei digitalen Signale mit der In-Phasen-kopie des CDMA-Spreizcodes aus dem Spreizcodekopiegenerator aufweist,
die Integrierschaltungseinrichtung zwei Integrierschaltungen (112) zur jeweiligen Integration der Ausgangssignale der dritten Multiplizierer aufweist, und
die automatische Frequenzsteuerungsschaltung eine automatische Frequenzsteuerungsschaltung (213) zur Erfassung der Trägerfrequenzfehler auf der Grundlage des Ausgangs der zwei Integrierschaltungen aufweist, um diese zu dem Trägerfrequenzfehlerkompensator auszugeben.
eine Orthogonalerfassungseinrichtung (62) zur orthogonalen Erfassung des CDMA-Spreizempfangssignal auf der Grundlage zweier erfasster Signale (I, Q), deren Phasen zueinander orthogonal sind,
zwei A/D-Wandler (65, 66) zur jeweiligen Umwandlung der zwei erfassten Signale in digitale Signale,
zwei Schalt-Schaltungen (42I, 42Q) zur jeweiligen Eingabe der zwei digitalen Signale,
zwei Anfangsbeschaffungsschaltungen (43I, 43Q)) zum Empfang eines der Ausgänge der zwei Schalt-Schaltungen und zur Vornahme einer Korrelation zwischen dem Ausgang und einem Referenzspreizcode, um einen Korrelationswert auszugeben,
Beschaffungsentscheidungsschaltungen (45), die jeweils mit den zwei Anfangsbeschaffungsschaltungen verbunden sind, zur Beurteilung des Abschlusses der Synchronisation auf der Grundlage des Korrelationswerts und zur Ausgabe des Beurteilungsergebnisses zu der Schalt-Schaltung, und wobei
das Synchronisationsgerät eine Korrelationserfassungseinrichtung gemäß Patentanspruch 1 aufweist, wobei die Korrelationserfassungseinrichtung zum Empfang eines anderen Ausgangs der Schalt-Schaltungseinrichtung und zum Vornehmen einer Korrelation zwischen dem anderen Ausgang und einem Referenzspreizcodes betreibbar ist, der in einem darin eingebauten Spreizcodekopiegenerator erzeugt wird, und
die zwei Schalt-Schaltungseinrichtung (42I, 42Q) zur Ausgabe eines empfangenen Signals zu der Anfangsbeschaffungsschaltungseinrichtung (43) zum Zeitpunkt einer Asynchronisation betreibbar ist, während ein empfangenes Signal zu der Korrelationserfassungseinrichtung (44) nach dem Abschluss der Synchronisation auf der Grundlage des Ausgangs der Beschaffungserfassungsschaltungseinrichtung (45) ausgegeben wird, und
wobei in der Korrelationserfassungseinrichtung (44)
die Spreizcodekopieerzeugungseinrichtung (30) zur Erzeugung der In-Phasen-Kopie, einer in der Phase vorauseilenden Kopie und einer in der Phase nachlaufenden Kopie bezug auf die zwei digitalen Signale betreibbar ist,
die erste Multiplikationseinrichtung zwei erste Multiplizierer (47) zur jeweiligen Multiplikation der zwei digitalen Signale mit der in der Phase voreilenden Kopie des CDMA-Spreizcodes aufweist, um zwei erste Korrelationserfassungssignale auszugeben,
die zweite Multiplikationseinrichtung einen zweiten Multiplizierer (48) zur jeweiligen Multiplikation der zwei digitalen Signale mit der in der Phase nachlaufenden Kopie des CDMA-Spreizcodes aufweist, um zwei zweite Korrelationserfassungssignale auszugeben,
die Trägerfrequenzfehlerkompensationseinrichtung einen Kompensator (208) aufweist, der zur Kompensation der jeweiligen den zwei ersten und zwei zweiten Korrelationserfassungssignalen zugehörigen Trägerfrequenzfehlern betreibbar ist,
die dritte Multiplikationseinrichtung zwei dritte Multiplizierer (111) zur jeweiligen Multiplikation der zwei digitalen Signale mit der In-Phasen-Kopie des CDMA-Spreizcodes aus dem Spreizcodekopiegenerator aufweist,
die Integrierschaltungseinrichtung zwei Integrierschaltungen (112) zur jeweiligen Integration der Ausgangssignale der dritten Multiplizierer aufweist, und
die automatische Frequenzsteuerungsschaltung eine automatische Frequenzsteuerungsschaltung (213) zur Erfassung der Trägerfrequenzfehler auf der Grundlage des Ausgangs der zwei Integrierschaltungen aufweist, um diese zu dem Trägerfrequenzfehlerkompensator auszugeben.
Erzeugen einer In-Phasen-Kopie eines CDMA-Spreizcodes mit derselben Phase, einer in der Phase vorauseilenden Kopie des CDMA-Spreizdoces mit einer voreilenden Phase und einer in der Phase nachlaufenden Kopie eines CDMA-Spreizcodes mit einer nachlaufenden Phase in bezug auf das empfangene Signal,
erstes Multiplizieren des empfangen Signals mit der in der Phase vorauseilenden Kopie des CDMA-Spreizcodes derart, dass ein erstes Korrelationserfassungssignal ausgegeben wird,
zweites Multiplizieren des empfangen Signals mit der in der Phase nacheilenden Kopie des CDMA-Spreizcodes derart, dass ein zweites Korrelationserfassungssignal ausgegeben wird,
Kompensieren eines den ersten und zweiten Korrelationserfassungssignalen zugehörigen Trägerfrequenzfehlers,
Summieren, in gegenüberliegenden Phasen, der ersten und zweiten Korrelationserfassungssignale, die durch die Frequenzfehlerkompensationseinrichtung (208) kompensiert worden sind,
Bilden eines Durchschnitts eines Ausgangssignals in dem Summierschritt entlang einer Zeitachse,
drittes Multiplizieren des empfangenen Signals mit der In-Phasen-Kopie des CDMA-Spreizcodes,
Integrieren eines Ausgangssignals in dem Multiplizierschritt,
Erfassen des Trägerfrequenzfehlers auf der Grundlage eines Ausgangs in dem Integrierschritt, um diesen in dem Trägerfrequenzfehlerkompensationsschritt zu verwenden,
Erzeugen eines Entscheidungssignals der empfangen Daten auf der Grundlage eines Ausgangssignals in dem Integrierschritt,
inverses Modulieren eines Ausgangssignals der Durchschnittsbildungsschaltung (58) durch das Entscheidungssignal der empfangenen Daten, und
Steuern einer Phase eines auszugebenen Kopiecodes auf der Grundlage des Ausgangs in dem Inversmodulationsschritt.
Vornehmen einer Korrelation zwischen dem empfangenen Signal und einem Referenzspeizcode zur Durchführung einer anfänglichen Beschaffung, und
Vornehmen einer Korrelation zwischen dem empfangenen Signal dem Referenzspreizcode zur Nachführung, nach Abschluss der Synchronisation, entsprechend dem Verfahren gemäß Patentanspruch 5.
des moyens (30) de production de duplications du code d'étalement pour produire une duplication avancée en phase d'un code d'étalement par CDMA ayant une phase d'avance et une duplication retardée en phase du code d'étalement par CDMA ayant une phase retardée par rapport au signal reçu ;
des premiers moyens (47) de multiplication destinés à multiplier le signal reçu par la duplication avancée en phase du code d'étalement par CDMA de manière à émettre en sortie un premier signal de détection de corrélation ; et
des deuxièmes moyens (48) de multiplication destinés à multiplier le signal reçu par la duplication retardée en phase du code d'étalement par CDMA de manière à émettre en sortie un second signal de détection de corrélation ;
le dispositif étant caractérisé en ce qu'il comporte :
des moyens (208) de compensation d'erreur de fréquence de porteuse destinés à compenser une erreur de fréquence de porteuse associée aux premier et second signaux de détection de corrélation ; et
des moyens (57) d'addition destinés à sommer en phase opposée les premier et second signaux de détection de corrélation, qui ont été compensés par les moyens (208) de compensation d'erreur de fréquence de porteuse ;
un circuit (58) de formation de moyenne destiné à moyenner un signal de sortie des moyens d'addition le long d'un axe du temps ;
et dans lequel les moyens (30) de production de duplications du code d'étalement peuvent en outre fonctionner pour produire une duplication en phase du code d'étalement par CDMA ayant la même phase, et dans lequel le détecteur de corrélation comporte en outre :
des troisièmes moyens (111) de multiplication destinés à multiplier le signal reçu par la duplication en phase du code d'étalement par CDMA provenant des moyens (30) de production de duplications du code d'étalement ;
des moyens (112) de circuit d'intégration destinés à intégrer un signal de sortie des troisièmes moyens multiplicateurs ;
des moyens (213) de circuit de commande automatique de fréquence destinés à détecter l'erreur de fréquence de porteuse sur la base d'une sortie des moyens (112) de circuit d'intégration, pour émettre celle-ci en sortie vers le compensateur (208) d'erreur de fréquence de porteuse ;
un démodulateur (113) destiné à produire un signal décidé de données reçues sur la base d'un signal de sortie des moyens (213) de circuit de commande automatique de fréquence ;
un circuit (114) de modulation inverse destiné à moduler en inverse un signal de sortie du circuit (58) de formation de moyenne par le signal décidé des données reçues ; et
des circuits (115, 29) de production d'horloge destinés à produire un signal d'horloge dont la phase est commandée par une sortie du circuit (114) de modulation inverse pour commander le générateur (30) de duplications du code d'étalement.
un circuit (42) de commutation pouvant fonctionner pour recevoir le signal reçu ;
des moyens (43) de circuit d'acquisition initiale destinés à recevoir une sortie du circuit de commutation et destinés à prendre une corrélation entre la sortie et un code d'étalement de référence de manière à émettre en sortie une valeur de corrélation ;
des moyens (45) de circuit de décision d'acquisition connectés au circuit (43) d'acquisition initiale, pour juger l'achèvement de la synchronisation sur la base de la valeur de corrélation et pour émettre en sortie le résultat du jugement aux moyens (42) de circuit de commutation ; et dans lequel
le détecteur (44) de corrélation peut fonctionner pour recevoir un autre signal de sortie des moyens de circuit de commutation et prendre une corrélation entre l'autre signal de sortie et un code d'étalement de référence produit dans un générateur de duplications du code d'étalement incorporé en son sein ; et
les moyens (42) de circuit de commutation pouvant fonctionner pour émettre en sortie un signal reçu vers les moyens (43) de circuit d'acquisition initiale à l'instant d'une absence de synchronisation tout en émettant en sortie un signal reçu vers le détecteur (44) de corrélation après l'achèvement de la synchronisation sur la base du signal de sortie des moyens (45) de circuit de détection d'acquisition.
un détecteur (62) orthogonal pour détecter de manière orthogonale le signal reçu étalé par CDMA fondé sur deux signaux (I, Q) détectés dont les phases sont orthogonales l'une à l'autre ;
deux convertisseurs (65, 66) analogiques/numériques pour convertir les deux signaux détectés en signaux numériques respectivement, et dans lequel dans le détecteur (44) de corrélation :
les moyens de production de duplications du code d'étalement comportent un générateur (30) de duplications du code d'étalement pour respectivement produire une duplication en phase du code d'étalement par CDMA ayant une phase d'avance et une duplication retardée en phase du code d'étalement par CDMA ayant une phase retardée par rapport aux deux signaux numériques ;
les premiers moyens de multiplication comportent un premier multiplicateur (47) pour respectivement multiplier les deux signaux numériques par la duplication d'avance de phase du code d'étalement par CDMA de manière à émettre en sortie deux premiers signaux de détection de corrélation ;
les deuxièmes moyens de multiplication comportent un deuxième multiplicateur (48) pour respectivement multiplier les deux signaux numériques par la duplication retardée en phase du code d'étalement par CDMA de manière à émettre en sortie deux deuxièmes signaux de détection de corrélation ;
les moyens de compensation d'erreur de fréquence de porteuse comportent un compensateur (208) d'erreur de fréquence de porteuse pour compenser pour des erreurs de fréquence de porteuse respectives associées aux dits deux premiers signaux de détection de corrélation et auxdits deuxièmes signaux de détection de corrélation ;
des troisièmes moyens multiplicateurs comportent deux troisièmes multiplicateurs (111) destinés à respectivement multiplier lesdits deux signaux numériques par la duplication en phase du code d'étalement par CDMA provenant du générateur de duplications du code d'étalement ;
les moyens de circuit d'intégration comportent des circuits (112) d'intégration destinés à respectivement intégrer des signaux de sortie des trois multiplicateurs ; et
les moyens de circuit de commande automatique de fréquence comportent un circuit (213) de commande automatique de fréquence destiné à détecter des erreurs de fréquence de porteuse sur la base de la sortie des deux circuits d'intégration, pour les émettre en sortie vers le compensateur d'erreur de fréquence de porteuse.
un détecteur (62) orthogonal destiné à détecter de manière orthogonale le signal reçu étalé par CDMA sur la base de deux signaux (I, Q) détectés dont les phases sont orthogonales l'une à l'autre ;
deux convertisseurs (65, 66) analogiques/numériques destinés à convertir les deux signaux détectés en des signaux numériques, respectivement ;
deux circuits (42I, 42Q) de commutation destinés à entrer les deux signaux numériques, respectivement ;
deux circuits (43I, 43Q) d'acquisition initiale destinés à entrer l'un des signaux de sortie des deux circuits de commutation et à prendre une corrélation entre la sortie et un code d'étalement de référence de manière à émettre en sortie une valeur de corrélation ;
des circuits (45) de décision d'acquisition respectivement connectés auxdits deux circuits d'acquisition initiale, pour juger l'achèvement de la synchronisation sur la base de la valeur de corrélation et pour émettre en sortie le résultat de jugement au circuit de commutation ; et
un dispositif de synchronisation comportant un détecteur (44) de corrélation conformément à la revendication 1, le détecteur de corrélation pouvant fonctionner pour entrer l'autre signal de sortie des deux circuits de commutation et prendre une corrélation entre le signal de sortie et un code d'étalement de référence produit dans un générateur de duplications du code d'étalement incorporé en son sein ;
les deux circuits (42I, 42Q) de commutation pouvant fonctionner pour émettre en sortie un signal reçu vers le circuit d'acquisition initiale à l'instant d'une absence de synchronisation, tout en émettant en sortie un signal reçu vers le détecteur de corrélation après l'achèvement de la synchronisation sur la base du signal de sortie du circuit de décision d'acquisition ; et
dans lequel dans le détecteur (44) de corrélation, les moyens (30) de production de duplications du code d'étalement peuvent fonctionner pour produire la duplication en phase, la duplication avancée en phase et la duplication retardée en phase par rapport auxdits deux signaux numériques ;
les premiers moyens de multiplication comportent deux premiers multiplicateurs (47) destinés à multiplier respectivement les deux signaux numériques par la duplication avancée en phase du code d'étalement par CDMA de manière à émettre en sortie les premiers signaux de détection de corrélation ;
les deuxièmes moyens de multiplication comportent deux deuxièmes multiplicateurs (48) destinés à respectivement multiplier les deux signaux numériques par la duplication retardée en phase du code d'étalement par CDMA de manière à émettre en sortie des deuxièmes signaux de détection de corrélation ;
les moyens de compensation d'erreur de fréquence de porteuse comportent un compensateur (208) pouvant fonctionner pour compenser des erreurs de fréquence de porteuse respectives associées aux deux premiers signaux de détection de corrélation et aux deux deuxièmes signaux de détection de corrélation ;
les troisièmes moyens de multiplication comportent deux troisièmes multiplicateurs (111) destinés respectivement à multiplier les deux signaux numériques par la duplication en phase du code d'étalement par CDMA provenant du générateur de duplications du code d'étalement ;
les moyens de circuit d'intégration comportant deux circuits (112) d'intégration destinés respectivement à intégrer des signaux de sortie des troisièmes multiplicateurs ;
les moyens de circuit de commande automatique de fréquence comportant un circuit (213) de commande automatique de fréquence destiné à détecter des erreurs de fréquence de porteuse sur la base des signaux de sortie des deux circuits d'intégration, pour les émettre en sortie vers le compensateur d'erreur de fréquence de porteuse.
produire une duplication en phase d'un code d'étalement par CDMA ayant la même phase, une duplication avancée en phase du code d'étalement par CDMA ayant une phase d'avance et une duplication retardée en phase du code d'étalement par CDMA ayant une phase retardée par rapport au signal reçu ;
multiplier premièrement le signal reçu par la duplication avancée en phase du code d'étalement par CDMA de manière à émettre en sorte un premier signal de détection de corrélation ;
multiplier deuxièmement le signal reçu par la duplication retardée en phase du code d'étalement par CDMA de manière à émettre en sortie un deuxième signal de détection de corrélation ;
compenser une erreur de fréquence de porteuse associée aux premiers et deuxièmes signaux de détection de corrélation ;
sommer en phase opposée les premier et deuxième signaux de détection de corrélation qui ont été compensés à l'étape de compensation d'erreur de fréquence de porteuse ;
calculer la moyenne d'un signal de sortie à l'étape de sommation le long d'un axe temporel ;
multiplier troisièmement le signal reçu par la duplication en phase du code d'étalement par CDMA ;
intégrer un signal de sortie à la troisième étape de multiplication ;
détecter l'erreur de fréquence de porteuse sur la base d'un signal de sortie à l'étape d'intégration de manière à l'utiliser à l'étape de compensation d'erreur de fréquence de porteuse ;
produire un signal décidé de données reçues sur la base d'un signal de sortie à l'étape d'intégration ;
moduler en inverse un signal de sortie à l'étape de calcul de la moyenne par le signal décidé des données reçues ; et
commander une phase d'un code de duplication pour qu'il soit émis en sortie sur la base du signal de sortie à l'étape de modulation en inverse.
prendre une corrélation entre le signal reçu et un code d'étalement de référence de manière à effectuer une acquisition initiale ; et
prendre une corrélation entre le signal reçu et le code d'étalement de référence pour effectuer un suivi, après achèvement de la synchronisation, conformément au procédé de la revendication 5.