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(11) | EP 1 347 513 A3 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | Low voltage drop and high thermal performance ball grid array package |
| (57) A low voltage drop and thermally enhanced integrated circuit (IC) package and a method
for assembling said package are described. A substantially planar substrate (302)
having a plurality of contact pads on a first surface is electrically connected through
the substrate to a plurality of solder ball pads on a second surface of the substrate.
An IC die (304) having a first surface is mounted to the first surface of the substrate.
The IC die has a plurality of I/O pads electrically connected to the plurality of
contact pads on the first surface of the substrate. A heat sink assembly (702) is
coupled to a second surface of the IC die and to a first contact pad on the first
surface of the substrate to provide a thermal path from the IC die to the first surface
of the substrate. The heat sink assembly can also provide an electrical path from
the IC die to the first surface of the substrate. The heat sink assembly may have
one or two heat sink elements to provide thermal and/or electrical connectivity between
the IC die and the substrate. |