SOLID-STATE HIGH VOLTAGE LINEAR REGULATOR CIRCUIT

Description

Field of the Invention

[0001] The present invention relates generally to high voltage regulators, and more particularly to solid-state circuits for high voltage regulation.

Background of the Invention

[0002] Many applications demand a regulated high voltage that is free from variations in voltage level. Designing an inexpensive and reliable circuit that provides a regulated high voltage, however, has proved to be problematic. While it has been recognized that it would be advantageous to use solid-state devices in a regulator circuit because of their low cost and small size, it has been difficult to design such a circuit. For example, although bipolar junction transistors (BJTs) have been used in the design of high voltage regulator circuits, the regulator circuits have failed to achieve the necessary performance for practical use. In certain circumstances, the current necessary to drive the bipolar junction transistors can exceed the actual load current being regulated. Moreover, bipolar junction transistors cannot tolerate overvoltages for an extended period. Based on the perceived shortcomings of bipolar junction transistors in specific, and solid-state devices in general, current regulators have therefore typically been constructed using different technologies.

[0003] We are also aware of the teachings of US-A-5043598 which discloses a solid-state voltage regulator having all of the features of the pre-characterizing portion of Claim 1.

Summary of the Invention

[0004] According to our invention a solid-state high voltage regulator circuit for supplying a regulated voltage to a load, the solid-state high voltage regulator circuit comprises:

(a) a high voltage generator connected by a line and an output terminal to the load;

(b) a voltage divider coupled to the line between the high voltage generator and the output terminal wherein the voltage divider is configured to provide a stepped-down voltage indicative of a voltage at the output terminal.

(c) an error amplifier coupled to receive the stepped-down voltage and a reference voltage wherein the error amplifier is configured to generate a control signal indicative of a difference in level between the stepped-down voltage and the reference voltage the control signal being used to regulate the output of the high voltage regulator circuit;
   characterized by:

(d) a current regulation stage having a sense impedance and configured to adjust a regulator current flowing through the sense impedance, the current regulation stage being either coupled in a shunt configuration with the high voltage generator, whereby regulation of the output voltage is achieved by shunting current from the high voltage generator through the sense impedance, or the current regulation stage being coupled in a series configuration with the high voltage generator whereby the output voltage to the load is regulated by adjusting the current flowing through the sense impedance to develop a voltage that is added to the voltage supplied by the high voltage generator.

[0005] The present invention provides a solid-state regulator circuit for regulating a high voltage in a controlled manner. The regulator circuit consists of multiple MOSFET transistor stages connected in cascade. In the preferred embodiment, a blocking diode is connected in parallel with each stage. Each stage in the regulator circuit can be biased on or off. When biased on, the stage provides a conductive path. When biased off, the stage acts as an open circuit up to the breakdown value of the blocking diode across each stage. The first stage in the regulator circuit is a current regulation stage that includes a current sense resistor in the conductive path of the regulator circuit. The stages coupled to the current regulation stage do not contain a sense resistor, and will hereinafter be referred to as the component stages.

[0006] In order to control the current flow through the regulator circuit, the current regulation stage is connected to a feedback circuit. The feedback circuit generates a signal that changes the bias point of a transistor in the current regulation stage. Changing the bias point of the transistor adjusts the amount of current that is flowing through the regulator circuit.

[0007] In accordance with one aspect of the invention, the regulator circuit may be connected to a high voltage generator in a shunt configuration. In the shunt configuration, the high voltage generator is connected to a load through a shunt resistor. The last component stage and the feedback circuit are connected at a point between the shunt resistor and the load. The current regulation stage is connected to ground. If the output from the high voltage generator exceeds a desired level, the feedback circuit adjusts the bias point of the current regulation stage to shunt additional current through the shunt resistor connected to the high voltage generator. The additional current causes a greater voltage drop through the resistor, charging the output voltage applied to the load. In this manner, the voltage applied to the load is regulated by charging the current through the shunt resistor.

[0008] In accordance with another aspect of the invention, the regulator circuit may be connected to a high voltage generator in a series configuration. In the series configuration, the component stages and the current regulation stage are connected in series with one of the output terminals from the high voltage generator. For example, the regulator circuit may be connected between ground and a first terminal of the high voltage generator that is floating with respect to ground. The feedback circuit is connected between a second terminal of the high voltage generator and the current regulation stage. Based on the monitored output voltage from the high voltage generator, the feedback circuit adjusts the amount of current flowing through the current regulation stage. In this manner, the output from the high voltage generator is maintained at a desired level.

[0009] In accordance with still another aspect of the invention, the series of discrete blocking diodes across the regulator circuit will avalanche at a known voltage rating. The blocking diodes provide a measure of overvoltage protection by entering into avalanche if a voltage across the regulator circuit exceeds the sum total of the avalanche ratings of the blocking diodes.

[0010] In accordance with still another aspect of the invention, the number of component stages can be varied to change the voltage that is regulated. Each component stage contributes to the regulation of a voltage roughly equivalent to the avalanche voltage rating of the blocking diode across the stage. The number of component stages may therefore be selected depending on the voltage that is to be regulated, allowing the regulator circuit to be simply and easily configured to operate in different environments.

[0011] An advantage of the disclosed regulator circuit is that it allows high voltages to be regulated using MOSFET transistors. MOSFET transistors are readily available, relatively inexpensive, displace a very small volume, and are of minimal weight. Constructing the regulator circuit using MOSFET transistor stages coupled in cascade therefore creates a very economical and small high voltage regulator.

Brief Description of the Drawings

[0012] The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIGURE 1 is a schematic of a solid-state regulator circuit of the present invention connected in a shunt configuration; and

FIGURE 2 is a schematic of a solid-state regulator circuit of the present invention connected in a series configuration.

Detailed Description of the Preferred Embodiment

[0013] FIGURE 1 depicts the preferred embodiment of a regulator circuit 10 in accordance with the present invention. Regulator circuit 10 consists of a number of component stages 12a, 12b, and 12c connected in cascade with a current regulation stage 14. As will be described in additional detail below, the regulator circuit may operate in one of two states. In an "off" state, the component stages 12a, 12b, and 12c and the current regulation stage 14 are initially biased off so that there is no conductive path provided through the regulator circuit. In an "on" state, the component stages and the current regulation stage are biased on so that a conductive path is provided through the regulator circuit. The amount of current that flows through the regulator circuit is controlled by the current regulation stage 14 in a manner that will be described below.

[0014] The regulator circuit 10 is depicted in FIGURE 1 in a shunt configuration. One end of the regulator circuit 10 is connected between the output of a high voltage generator 16 and a load. The other end of the regulator circuit is connected to ground 18. A feedback circuit comprised of a voltage divider 20 and an error amplifier 22 is connected between the load and the current regulation stage 14. The feedback circuit monitors the output voltage supplied to the load, and changes the amount of current that is shunted by the regulator circuit 10 in order to maintain the output voltage at a desired level, i.e., provide an essentially constant voltage to the load despite variations that otherwise would affect the output voltage at terminal V_out.

[0015] Examining the feedback circuit in closer detail, the output voltage from the high voltage generator 16 is connected in series with a shunt resistor R1. The current flowing through shunt resistor R1 determines the output voltage at the load. That is, the voltage drop across the resistor is subtracted from the output voltage generated by the high voltage generator to determine the voltage applied to the load. The regulator circuit 10 therefore adjusts the current flowing through the shunt resistor in order to maintain a desired output voltage at the load.

[0016] The voltage divider 20 consists of a resistive and capacitive network that steps down the output voltage at the load. The voltage divider consists of a resistor R2 in series with a resistor R3 connected between line 24 and ground. Resistor R3 is preferably much smaller than resistor R2 so that the output voltage produced by the high voltage generator is greatly stepped down for use in the feedback circuit. A line 26 is connected to the point where resistor R2 connects with resistor R3. Line 26 provides the stepped-down voltage from the voltage divider to the error amplifier 22. The capacitive network includes capacitors C2, C3 and C4 connected in series between the output end of resistor R1 and ground, and an additional capacitor C 1 connected between the junction of resistors R2 and R3 and the junction of capacitors C2 and C3. A resistor R4 is connected in parallel with capacitor C3. A resistor R5 and a Zener diode Z1 are connected in parallel with capacitor C4. The capacitive network provides instantaneous feedback information to the error amplifier. The capacitive coupling associated with the capacitive network increases bandwidth of the voltage divider. A provision which defeats the capacitive coupling allows capacitor C2 to charge upon initial circuit actuation is composed of components C3, Z1, C4, R4, R5. Zener Z1 performs the function of a switch providing a current shunt of smaller value capacitor C4 during the charging of C2. The Zener voltage is set for approximately five volts.

[0017] In an actual embodiment of the voltage divider, the components of the voltage divider have the following values:

Component	Part Number or Rating
Resistor R2	500 Meg
Resistor R3	250 K
Resistor R4	47 Meg
Resistor R5	47 Meg
Capacitor C1	0.01µF
Capacitor C2	1000pF
Capacitor C3	0.68µF
Capacitor C4	0.10µF
Zener Diode Z1	IN6489, 4.74

[0018] The error amplifier 22 compares the stepped down output at the load with a reference voltage and produces an error signal that is proportional to the difference in the two voltage levels. The error amplifier consists of an operational amplifier U1 having the non-inverting input connected to line 26 through a resistor R7. The inverting input of operational amplifier U1 is coupled to a voltage reference (V_ref) terminal 28 through a resistor R8. The inverting input of the operational amplifier U1 is also connected to the output of the amplifier by a capacitor C5, and by the series connection of a resistor R9 and a capacitor C6. The voltage reference terminal is maintained at a reference voltage level that corresponds to the desired output at the load. In the preferred embodiment, the reference voltage is a stable DC voltage that does not fluctuate like the high voltage generator. The reference voltage may be supplied by a number of circuits, such as from an LH0070-2 device.

[0019] The voltage applied to the load is compared by the error amplifier 22 with the desired voltage as represented by the reference voltage on the V_ref terminal. The error amplifier produces an error signal that is proportional to the difference between the desired voltage and the output voltage at the load. The error signal is provided to the current regulation stage 14 on a line 30. The slew rate of the error amplifier is slowed by the network consisting of capacitors C5, C6 and resistor R9, which filter any high frequency variations in the error signal. In an actual embodiment of the error amplifier, the components of the error amplifier have the following values:

Component	Part Number or Rating
Resistor R7	10 K
Resistor R8	10 K
Resistor R9	100 K
Capacitor C5	10pF
Capacitor C6	0.01µF
Operational Amplifier U1	TL064, LM124
Resistor R10	100Ω

[0020] The output from the error amplifier 22 is connected to the current regulation stage 14 of the regulator circuit 10 through a resistor R10. The current regulation stage is constructed around a pair of transistors TRA and TRB, preferably both MOSFETs. A sense impedance, preferably a sense resistor RS, is connected between the source of transistor TRA and ground 18. The sense resistor RS is selected to have a peak power capability sufficient to conduct the desired current when the regulator circuit is turned on. A diode DD and a capacitor CD are connected between the source of transistor TRA and the drain of transistor TRB. A capacitor CF is also connected in parallel with the sense resistor RS.

[0021] Transistors TRA and TRB are both biased by the error signal produced by the error amplifier. A resistor RG and a Zener diode ZG are connected in parallel between the gate and source of transistor TRB. Resistor RG and Zener diode ZG are selected to prevent the transistor from conducting due to leakage current during biased-off operation, to protect the transistor from gate-to-source stress during biased-on operation, and to allow the desired gate-to-source voltage to turn the transistor on when a conductive path is generated through the regulator circuit. The gate of transistor TRA is connected in series with a diode DB and a resistor RB. Diode DB is selected to ensure that reverse current will not flow from the current regulation stage. Resistor RB is sized to limit the current flow into the transistor when the regulator circuit is turned on. In an actual embodiment of the regulator circuit, which is designed to regulate an approximate 10,000 volts output, the circuit elements for the current regulation stage are as follows:

Component	Part Number or Rating
Diode DD	BYD37M
Capacitor CD	10pF
Transistors TRA	1RFR020, MTD IN80E
Zener diode ZG	BZX84015, 15V
Resistor RG	10 K ohm
Diode DB	BYD37M
Resistor RB	1 K ohm
Resistor RS	1 K ohm
Capacitor CF	0.01µF
Resistor RZ	4.99 K ohm

[0022] The drain of transistor TRB is connected to the first component stage 12a. It is noted that each component stage 12a, 12b and 12c is constructed with the same circuit elements. For purposes of this description, a generic component stage 12a will therefore be discussed as representative of all of the component stages. Component stage 12a is constructed around a pair of transistors TR, which in the preferred embodiment of this circuit are a pair of MOSFETs connected in cascade. Component stage 12a is similar to the current regulation stage, in that both stages are constructed around a pair of transistors. The component stages do not, however, contain a sense resistor in the conductive path. A diode DD and a capacitor CD are connected across the transistors TR. Diode DD and capacitor CD serve the same functions as the corresponding components in the current regulation stage, that is, they are selected to provide overvoltage protection for the circuit. A Zener diode ZG and a resistor RG are also connected across the gate and source of each transistor. The Zener diode ZG and the resistor RG also serve the same roles as they do in the current regulation stage.

[0023] The gate of each transistor TR in the component stage is connected to a biasing voltage through a resistor RB and a diode string DB. The diode string DB contains a different number of diodes for each transistor in the component stages. In order to ensure that only one component stage operates in a linear mode, the number of diodes within the diode string associated with a particular component stage increases by one for each transistor within the stage. Thus, in the representative regulator circuit depicted in FIGURE 1, component stage 12a contains diode strings having two and three diodes, component stage 12b contains diode strings having four and five diodes, and component stage 12c contains diode strings having six and seven diodes. Before turning on, the voltage drop across the component stage must therefore exceed the voltage drop required to turn on the previous component stage by a value equal to the voltage drop across one diode DB. This method has the advantage of producing additional output stability due to the required voltage drop increase for conduction of an additional transistor.

[0024] The drain of the transistor TR in the last component stage 12c is connected to the output voltage line 24 through the series connection of diode string DS and a resistor R6. Diode string DS is a string of Zener diodes that allow the output voltage at the load to exceed the voltage level that may be shunted by the component stages and current regulation stage alone. The diode string drops a fixed voltage providing a lower voltage at the component stages. The number of diodes within the diode string may therefore be changed rather than requiring the addition of component stages in certain applications.

[0025] Before the regulator circuit is turned on, all the component stages are nonconducting. The biasing potential provided to each of the component stages is sufficient to raise the potential at the gates of the component stage transistors TR so that they will become biased on when the gate-to-source turn-on voltage for each transistor is exceeded by a voltage across resistor RG. That is, each transistor TR will become biased on when the current flow through the associated resistor RG causes a voltage drop across the resistor that exceeds the turn-on voltage of each transistor. When biased off, the resistance of each component stage exceeds one gigaohm. The regulator circuit therefore acts as an open circuit.

[0026] The regulator circuit is turned on when the high voltage generator begins to generate an output voltage on line 24. The high voltage at the load is stepped down by the voltage divider 20 and compared by the error amplifier 22 with the reference voltage level. The error signal generated by the error amplifier is applied to the current regulation stage 14, biasing transistor TRA so that it begins to conduct current through the sense resistor RS. After transistor TRA is biased on, a current path is provided through diode DB, resistor RB, and resistor RG of the directly adjacent transistor TRB, and through the current regulation stage transistor TRA and the sense resistor RS to ground. When the voltage across resistor RG rises sufficiently above the gate-to-source potential threshold of transistor TRB, the transistor is biased on.

[0027] The turning-on process repeats for the transistors TR in the component stages. The transistors TR in each component stage remain biased off, and non-conducting, until the transistors in the component stage that is located nearer to the current regulation stages enter into conduction. The number of transistors TR that are biased on depends on the current through the current regulation stage 14. Depending on the current being shunted, some, but not necessarily all of the transistors in the component stages will be biased on. One transistor TR will operate in a linear mode. The transistors TR closer to the current regulation stage will operate in saturation. The transistors TR higher in the component stack will remain biased off, however the current will flow through the blocking diodes DD around the biased off transistors. The conductive path through the regulator circuit during operation therefore extends through the avalanching diodes DD, through the transistor TR operating in linear operation, through the transistors TR operating in saturation, and through the current regulation stage to ground 14. The transistor operating in a linear mode will change depending on the current being shunted. Ultimately, current is shunted through the regulator circuit 10 to maintain the output voltage at a desired level. When this occurs, current will be shunted through the regulator circuit 10 away from the load connected to output line 24.

[0028] The amount of current that is shunted away from the load depends on the biasing point of the current regulation stage 14. The biasing point of the current regulation stage is adjusted by the changing voltage applied to the current regulation stage by the error amplifier 22. The reference voltage V_ref is selected so that the output from the high voltage generator 16 is regulated at a desired level. In this manner, the amount of current through the current regulation stage is closely controlled.

[0029] While three component stages 12a, 12b and 12c are depicted in FIGURE 1, it will be appreciated that a greater or lesser number of component stages may be included within the regulator circuit. Each component stage contributes to regulating a voltage equal to the maximum avalanche voltage of the blocking diode for that stage. The diode ratings of each component stage and the current regulation stage are therefore used to determine the number of component stages necessary to regulate a particular voltage. For example, if the regulator circuit were to regulate 6,000 volts, and if blocking diodes DD rated at 1,000 volts were used in the regulator circuit, a total of five component stages would be required in the regulator circuit. The total avalanche voltage of the five blocking diodes in the component stages and the single blocking diode in the current regulation stage would add to a number approximating the required regulated voltage of 6,000 volts. It will be appreciated that a greater or lesser number of component stages could be used to select the regulated voltage of the regulator circuit. Moreover, diodes having different ratings may also be selected to change the regulated voltage capability. As noted above, the number of Zener diodes in the diode string DS may also be changed to reduce the number of required component stages.

[0030] The regulator circuit 10 disclosed in FIGURE 1 is advantageous in that it uses solid-state MOSFETs to regulate high voltages. Using MOSFETs reduces the cost of the regulator circuit, allows the regulator circuit to be incorporated into a very small package, and allows the regulator circuit to operate reliably in high voltage applications.

[0031] FIGURE 2 depicts an alternative embodiment of a regulator circuit 50 in a series configuration with a high voltage generator 52. The high voltage generator 52 is in a floating configuration, wherein the generator is not grounded. The construction and operation of the regulator circuit 50 is similar to the regulator circuit 10 depicted in FIGURE 1. The operation of the regulator circuit will therefore be broadly described, with the reader directed to the corresponding text of FIGURE 1 for additional details.

[0032] The high voltage generator 52 is connector to a load by a line 54, and to the regulator circuit 50 by a line 53. Unlike the regulator circuit 10 shown in FIGURE 1 which contained multiple component stages, the regulator circuit 55 shown in FIGURE 2 contains only a single current regulation stage 55. The current regulation stage is constructed around a pair of transistors TRA and TRB, preferably both MOSFETs. A sense impedance, preferably a sense resistor RS, is connected between the source of transistor TRA and ground 66. The sense resistor RS is selected to have a peak power capability sufficient to conduct the desired current when the regulator circuit is turned on. A diode DD and a capacitor CD are connected between the source of transistor TRA and the drain of transistor TRB.

[0033] The current regulation stage 55 operates in the same manner as does the current regulation stage in the regulator circuit 10 depicted in FIGURE 1. The current regulator stage is connected to a feedback circuit consisting of an error amplifier 62 and a voltage divider 56. The voltage divider 56 is coupled to the output line 54 that extends from the high voltage generator to the load. The voltage divider 56 generates a signal on a line 58 that is proportional to the output voltage produced by the high voltage generator. The stepped-down signal is provided on line 58 to the error amplifier 62.

[0034] The error amplifier 62 compares the stepped-down voltage signal with a reference voltage V_ref. The error amplifier contains an operational amplifier U2 that acts as an inverting buffer. The output from operational amplifier U2 is provided to operational amplifier U3, which operates as a comparator to compare the measured voltage level on the output line 54 with a voltage reference V_ref. An error signal is generated that is proportional to the difference between the measured voltage on the output line 54 and the reference voltage V_ref., and provided to the current regulation stage 55 on a line 64.

[0035] The error signal changes the biasing point of transistor TRA, controlling the amount of current that is conducted through the current regulation stage. The impedance of the current regulation stage varies with the current flow through the stage. Since the current regulation stage 55 is coupled in series with the high voltage generator 52, the voltage drop across the current regulation stage will be summed with the voltage generated by the high voltage generator. By changing the amount of current that flows through the current regulation stage, the output voltage provided to the load is also changed. In this manner, the output voltage applied to the load is closely regulated.

[0036] Those skilled in the art will appreciate that additional circuitry is present within the feedback circuit of the regulator circuit 50 to minimize noise, slow the response of the feedback circuit, and prevent oscillations in the output from the high voltage generator. Those skilled in the art will also appreciate that additional component stages may be added to the current regulation stage 55 if higher voltages are to be regulated. The use of the regulator circuit 50 in a series configuration allows the high voltage generator 52 to remain floating.

[0037] While the preferred embodiment of the invention has been illustrated and described, it will be apparent that various changes can be made therein without departing from the scope of the invention.

Claims

1. A solid-state high voltage regulator circuit for supplying a regulated voltage to a load, the solid-state high voltage regulator circuit comprising:

(a) a high voltage generator (16; 52) connected by a line (24; 54) and an output terminal (V_out) to the load;

(b) a voltage divider (20; 56) coupled to the line (24; 54) between the high voltage generator (16; 52) and the output terminal (V_out), wherein the voltage divider (20; 56) is configured to provide a stepped-down voltage indicative of a voltage at the output terminal (V_out);

(c) an error amplifier (22; 62) coupled to receive the stepped-down voltage and a reference voltage (V_ref), wherein the error amplifier (22; 62) is configured to generate a control signal indicative of a difference in level between the stepped-down voltage and the reference voltage (V_ref), the control signal being used to regulate the output of the high voltage regulator circuit;
   characterized by:

(d) a current regulation stage (14, 12a, 12b, 12c; 55) having a sense impedance (RS) and configured to adjust a regulator current flowing through the sense impedance (RS), the current regulation stage (14, 12a, 12b, 12c) being either coupled in a shunt configuration with the high voltage generator (16), whereby regulation of the output voltage is achieved by shunting current from the high voltage generator (16) through the sense impedance (RS), or the current regulation stage (55) being coupled in a series configuration with the high voltage generator (52) whereby the output voltage to the load is regulated by adjusting the current flowing through the sense impedance (RS) to develop a voltage that is added to the voltage supplied by the high voltage generator (52).

2. The solid-state high voltage regulator circuit of Claim 1, further characterized by the current regulation stage (14, 12a, 12b, 12c; 55) comprising an input lead (30; 64), an output lead connected to ground (18; 66) and a regulated current path therebetween through the sense resistor (RS), the regulated current flowing in the regulated current path, wherein the regulation stage (14, 12a, 12b, 12c; 55) is configured to adjust the regulator current in response to the control signal.

3. The solid-state high voltage regulator circuit of Claim 2, further characterized by a first component stage (14) having a normally nonconductive first solid-state component (TRA), wherein the first component stage (14) is configured to cause the first solid-state component (TRA) to become conductive when the control signal exceeds a predetermined threshold level, to shunt current from the output terminal (V_out) as a function of the current flowing in the regulated current path so as to maintain the voltage at the output terminal (V_out) at the desired preselected level.

4. The solid-state high voltage regulator circuit of Claim 3, further comprising a plurality of additional component stages (12a, 12b, 12c) coupled in cascade with the first component stage (14), the plurality of additional component stages (12a, 12b, 12c) coupling the input lead (30) of the first component stage (14) to the output terminal (V_out), each of the additional component stages (12a, 12b, 12c) having an input lead and an output lead and having a component current path that is normally nonconductive between the input and output leads, wherein each of the plurality of additional component stages (12a, 12b, 12c) is configured to cause the component current path of the additional component stage to become conductive as a function of the current flowing in the regulated current path.

5. The solid-state high voltage regulator circuit of Claim 2, wherein the current regulation stage (14, 12a, 12b, 12c; 55) includes at least one field effect transistor (TRA) with its channel region coupled between the input and output leads of the regulation stage, the channel region forming at least part of the regulated current path.

6. The solid-state high voltage regulator circuit of Claim 2, wherein the current regulation stage (14, 12a, 12b, 12c) is configured to increase the current flowing through the regulated current path when the voltage level at the output terminal (V_out) exceeds the preselected level to increase the current flowing through the sense impedance (RS), thereby causing the voltage at the output terminal (V_out) to decrease in the shunt configuration.

7. The solid-state high voltage regulator circuit of Claim 2, further characterized by the current regulation stage (55) being configured to decrease the current flowing through the regulated current path and sense impedance (RS) when the voltage level at the output terminal (V_out) is above the preselected level to decrease the current flowing through the sense impedance (RS), thereby causing the voltage at the output terminal (V_out) to decrease in the series configuration.

8. The solid-state high voltage regulator circuit of Claim 4, further characterized by the first component stage further comprising:

(a) a diode circuit (DB) coupled to receive a substantially constant bias voltage; and

(b) a field effect transistor (TRA) with its gate coupled to receive the output signal of the diode (DB) and with its channel region coupled between input and output leads of the first component stage, the channel region of the field effect transistor (TRA) forming at least part of the first component current path.

9. The solid-state high voltage regulator circuit of Claim 8, wherein each of the plurality of additional component stages (12a, 12b, 12c) includes:

(a) a diode circuit (DB) coupled to receive the bias voltage; and

(b) a field effect transistor (TR) with its gate coupled to receive an output signal from its corresponding diode circuit (DB) and with its channel region coupled to the input and output leads of its corresponding additional component stage, the diode circuit (DB) of each of the plurality of additional component stages (12a, 12b, 12c) having a greater number of cascaded diodes than the diode circuit (DB) of the additional component stage coupled next closes to the first component stage (14).

10. The solid-state high voltage regulator circuit of Claim 9, wherein the differing number of diodes in the diode circuits (DB) of the plurality of additional component stages (12a, 12b, 12c) prevents each of the plurality of component stages from becoming conductive before the component stage coupled next closest to the first component stage (14).

11. The solid-state high voltage regulator circuit of Claim 4, further comprising a plurality of shunting circuits (DD, CD), each of the plurality of shunting circuits (DD, CD) being coupled to input and output leads of a corresponding component stage (12a, 12b, 12c) of the plurality of additional component stages (12a, 12b, 12c) and the first component stage (14), each shunting circuit (DD, CD) being configured to provide a current path bypassing the corresponding component stage when the current path of the corresponding component stage is non-conductive.

12. The solid-state high voltage regulator circuit of Claim 11, wherein the plurality of additional component stages (12a, 12b, 12c) are configured so that when the field effect transistor (TR) of one of the plurality of additional component stages is biased in a linear operational mode, the field effect transistor (TR) of each if any of the plurality of component stages (12a, 12b, 12c) coupled closer to the regulator stage (14) is biased in a saturation mode and the field effect transistor (TR) of each if any of the plurality of component stages (12, 12b, 12c) coupled farther from the regulator stage (14) is biased in a non-conductive mode.

Ansprüche

1. Eine Festkörper-Hochspannungsregelschaltung zum Liefern einer geregelten Spannung an eine Last, wobei die Festkörper-Hochspannungsregelschaltung umfasst:

(a) einen Hochspannungsgenerator (16; 52), der durch eine Leitung (24; 54) und einen Ausgangsanschluss (V_out) mit der Last verbunden ist ;

(b) einen Spannungsteiler (20; 56), der zwischen dem Hochspannungsgenerator (16; 52) und dem Ausgangsanschluss (V_out) an die Leitung (24; 54) gekoppelt ist, wobei der Spannungsteiler (20; 56) konfiguriert ist, um eine heruntertransformierte Spannung bereitzustellen, welche auf eine Spannung an dem Ausgangsanschluss (V_out) hinweist;

(c) einen Fehlerverstärker (22; 62), welcher gekoppelt ist, um die heruntertransformierte Spannung und eine Referenzspannung (V_ref) zu erhalten, wobei der Fehlerverstärker (22; 62) konfiguriert ist, um ein Steuersignal zu generieren, welches auf eine Niveaudifferenz zwischen der heruntertransformierten Spannung und der Referenzspannung (V_ref) hinweist, wobei das Steuersignal verwendet wird, um die Ausgangsleistung der Hochspannungsregelschaltung zu regeln;
gekennzeichnet durch:

(d) eine Stromregelstufe (14, 12a, 12b, 12c; 55), die eine Abfühlimpedanz (RS) besitzt und konfiguriert ist, um einen Regelstrom anzupassen, der durch die Abfühlimpedanz (RS) fließt, wobei die Stromregelstufe (14, 12a, 12b, 12c) entweder in einer Parallelkonfiguration an den Hochspannungsgenerator (16) gekoppelt ist, wobei die Regelung der Ausgangsspannung durch Abzweigen von Strom von dem Hochspannungsgenerator (16) durch die Abfühlimpedanz (RS) erreicht wird, oder wobei die Stromregelstufe (55) in einer Reihenkonfiguration an den Hochspannungsgenerator (52) gekoppelt ist, wobei die Ausgangsspannung für die Last durch Anpassen des Stroms reguliert wird, der durch die Abfühlimpedanz (RS) fließt, um eine Spannung zu erzeugen, welche zu der Spannung hinzugefügt wird, die durch den Hochspannungsgenerator (52) geliefert wird.

2. Die Festkörper-Hochspannungsregelschaltung nach Anspruch 1, desweiteren gekennzeichnet durch die Stromregelstufe (14, 12a, 12b, 12c; 55), umfassend eine Eingangsleitung (30; 64), eine Ausgangsleitung, welche mit der Erde (18; 66) verbunden ist, und dazwischen einen geregelten Stromweg durch den Abfühlwiderstand (RS), wobei der geregelte Strom in dem geregelten Stromweg fließt, wobei die Stromregelstufe (14, 12a, 12b, 12c; 55) konfiguriert ist, um den Regelstrom als Antwort auf das Steuersignal anzupassen.

3. Die Festkörper-Hochspannungsregelschaltung nach Anspruch 2, desweiteren gekennzeichnet durch eine erste Komponentenstufe (14) mit einer normalerweise nichtleitenden ersten Festkörperkomponente (TRA), wobei die erste Komponentenstufe (14) konfiguriert ist, die erste Festkörperkomponente (TRA) zu veranlassen, leitend zu werden, wenn das Steuersignal einen vorbestimmten Schwellenwert übersteigt, um Strom von dem Ausgangsanschluss (V_out) als eine Funktion von dem Strom abzuzweigen, der in dem geregelten Stromweg fließt, um die Spannung an dem Ausgangsanschluss (V_out) auf dem gewünschten, vorausgewählten Niveau aufrechtzuerhalten.

4. Die Festkörper-Hochspannungsregelschaltung nach Anspruch 3, desweiteren umfassend eine Vielzahl zusätzlicher Komponentenstufen (12a, 12b, 12c), welche in Kaskade an die erste Komponentenstufe (14) gekoppelt sind, wobei die Vielzahl zusätzlicher Komponentenstufen (12a, 12b, 12c) die Eingangsleitung (30) der ersten Komponentenstufe (14) an den Ausgangsanschluss (V_out) koppeln, wobei jede der zusätzlichen Komponentenstufen (12a, 12b, 12c) eine Eingangsleitung und eine Ausgangsleitung und einen Komponentenstromweg besitzt, der normalerweise zwischen den Eingangs- und Ausgangsleitungen nichtleitend ist, wobei jede der Vielzahl zusätzlicher Komponentenstufen (12a, 12b, 12c) konfiguriert ist, um den Komponentenstromweg der zusätzlichen Komponentenstufe zu veranlassen als eine Funktion des Stroms leitend zu werden, der in dem geregelten Stromweg fließt.

5. Die Festkörper-Hochspannungsregelschaltung nach Anspruch 2, wobei die Stromregelstufe (14, 12a, 12b, 12c; 55) mindestens einen Feldeffekttransistor (TRA) enthält, dessen Kanalzone zwischen den Eingangs- und Ausgangsleitungen der Regelstufe gekoppelt ist, wobei die Kanalzone zumindest einen Teil des geregelten Stromwegs bildet.

6. Die Festkörper-Hochspannungsregelschaltung nach Anspruch 2, wobei die Stromregelstufe (14, 12a, 12b, 12c) konfiguriert ist, den Strom zu erhöhen, der durch den geregelten Stromweg fließt, wenn das Spannungsniveau am Ausgangsanschluss (V_out) das vorgewählte Niveau übersteigt, um den Strom zu erhöhen, der durch die Abfühlimpedanz (RS) fließt, wodurch die Spannung am Ausgangsanschluss (V_out) veranlasst wird, in der Parallelkonfiguartion abzunehmen.

7. Die Festkörper-Hochspannungsregelschaltung nach Anspruch 2, desweiteren gekennzeichnet durch die Stromregelstufe (55), welche konfiguriert ist, um den Strom zu reduzieren, der durch den geregelten Stromweg und die Abfühlimpedanz (RS) fließt, wenn das Spannungsniveau am Ausgangsanschluss (V_out) über dem vorgewählten Niveau ist, um den Strom zu reduzieren, der durch die Abfühlimpedanz (RS) fließt, wodurch die Spannung an dem Ausgangsanschluss (V_out) veranlasst wird, in der Reihenkonfiguration abzunehmen.

8. Die Festkörper-Hochspannungsregelschaltung nach Anspruch 4, desweiteren gekennzeichnet durch die erste Komponentenstufe, welche desweiteren umfasst:

(a) eine Diodenschaltung (DB), welche gekoppelt ist, um eine im Wesentlichen konstante Vorspannung zu erhalten; und

(b) einen Feldeffekttransistor (TRA), dessen Gate gekoppelt ist, um das Ausgangssignal der Diode (DB) zu erhalten, und dessen Kanalzone zwischen Eingangs- und Ausgangsleitungen der ersten Komponentenstufe gekoppelt ist, wobei die Kanalzone des Feldeffekttransistors (TRA) zumindest einen Teil des ersten Komponentenstromwegs bildet.

9. Die Festkörper-Hochspannungsregelschaltung nach Anspruch 8, wobei jede der Vielzahl zusätzlicher Komponentenstufen (12a, 12b, 12c) enthält:

(a) eine Diodenschaltung (DB), welche gekoppelt ist, um die Vorspannung zu erhalten; und

(b) einen Feldeffekttransistor (TR), dessen Gate gekoppelt ist, um ein Ausgangssignal von seiner entsprechenden Diodenschaltung (DB) zu erhalten, und dessen Kanalzone an die Eingangs- und Ausgangsleitungen seiner entsprechenden zusätzlichen Komponentenstufen gekoppelt ist, wobei die Diodenschaltung (DB) jeder der Vielzahl zusätzlicher Komponentenstufen (12a, 12b, 12c) eine größere Anzahl kaskadierter Dioden besitzt als die Diodenschaltung (DB) der zusätzlichen Komponentenstufe, welche am nächsten an die erste Komponentenstufe (14) gekoppelt ist.

10. Die Festkörper-Hochspannungsregelschaltung nach Anspruch 9, wobei die abweichende Anzahl an Dioden in der Diodenschaltung (DB) der Vielzahl zusätzlicher Komponentenstufen (12a, 12b, 12c) jede der Vielzahl von Komponentenstufen daran hindert, vor der Komponentenstufe leitend zu werden, welche am nächsten an die erste Komponentenstufe (14) gekoppelt ist.

11. Die Festkörper-Hochspannungsregelschaltung nach Anspruch 4, desweiteren umfassend eine Vielzahl von Parallelschaltungen (DD, CD), wobei jede der Vielzahl von Parallelschaltungen (DD, CD) an Eingangs- und Ausgangsleitungen einer entsprechenden Komponentenstufe (12a, 12b, 12c) der Vielzahl zusätzlicher Komponentenstufen (12a, 12b, 12c) und die erste Komponentenstufe (14) gekoppelt ist, wobei jede Parallelschaltung (DD, CD) konfiguriert ist, um einen Stromweg bereitzustellen, der die entsprechende Komponentenstufe umgeht, wenn der Stromweg der entsprechenden Komponentenstufe nichtleitend ist.

12. Die Festkörper-Hochspannungsregelschaltung nach Anspruch 11, wobei die Vielzahl zusätzlicher Komponentenstufen (12a, 12b, 12c) so konfiguriert sind, dass, wenn der Feldeffekttransistor (TR) einer der Vielzahl zusätzlicher Komponentenstufen in einer linearen Betriebsart betrieben wird, der Feldeffekttransistor (TR) jeder der Vielzahl von Komponentenstufen (12a, 12b, 12c), welche näher an die Regelstufe (14) gekoppelt sind, in einem Sättigungsmodus betrieben wird und der Feldeffekttransistor (TR) jeder der Vielzahl von Komponentenstufen (12, 12b, 12c), welche weiter entfernt von der Regelstufe (14) gekoppelt sind, in einem nichtleitenden Modus betrieben wird.

Revendications

1. Circuit régulateur de haute tension à l'état solide servant à appliquer une tension réglée à une charge, le circuit régulateur de haute tension à l'état solide comprenant:

(a) un générateur de haute tension (16; 52) raccordé par une ligne (24; 54) et par une borne de sortie (V_out) à la charge;

(b) un diviseur de tension (20; 56) couplé à la ligne (24; 54) entre le générateur de haute tension (16; 52) et la borne de sortie (V_out), le diviseur de tension (20; 56) étant configuré de manière à fournir une tension abaissée indicative de la tension sur la borne de sortie (V_out);

(c) un amplificateur d'erreur (22; 62) couplé pour recevoir la tension abaissée et une tension de référence (V_ref), l'amplificateur d'erreur (22; 62) étant configuré pour générer un signal de commande indicatif d'une différence de niveau entre la tension abaissée et la tension de référence (V_ref), le signal de commande étant utilisé pour régler le signal de sortie du circuit régulateur de haute tension;
   caractérisé en ce que:

(d) un étage de régulation de courant (14, 12a, 12b, 12c; 55) possédant une impédance de détection (RS) et configuré de manière à ajuster un courant du régulateur circulant dans l'impédance de détection (RS), l'étage de régulation du courant (14, 12a, 12b, 12c) étant couplé selon un montage en shunt avec le générateur de haute tension (16), auquel cas la régulation de la tension de sortie est réalisée par le shuntage du courant depuis le générateur de haute tension (16) par l'impédance de détection (RS), ou l'étage de régulation du courant (55) est couplé selon un montage en série avec le générateur de haute tension (52) de telle sorte que la tension de sortie appliquée à la charge est réglée par ajustement du courant circulant dans l'impédance de détection (RS), pour développer une tension qui est ajoutée à la tension délivrée par le générateur de haute tension (52).

2. Circuit régulateur de haute tension à l'état solide selon la revendication 1, caractérisé en outre en ce que l'étage de régulation du courant (14, 12a, 12b, 12c; 55) comprend un conducteur d'entrée (30; 64), un conducteur de sortie raccordé à la masse (18; 66) et un trajet de courant circulant entre eux et traversant la résistance de détection (RS), le courant réglé circulant dans le trajet de courant réglé, et dans lequel l'étage de régulation (14, 12a, 12b, 12c; 55) est configuré de manière à ajuster le courant de régulateur en réponse au signal de commande.

3. Circuit régulateur de haute tension à l'état solide selon la revendication 2, caractérisé en outre par un premier étage à composants (14) possédant un premier composant à l'état solide (TRA) normalement non conducteur, dans lequel le premier étage à composants (14) est configuré de manière à amener le premier composant à l'état solide (TRA) à devenir conducteur lorsque le signal de commande dépasse un niveau de seuil prédéterminé, de manière à shunter le courant provenant de la borne de sortie (V_out) en fonction du courant circulant dans le trajet de courant réglé de manière à maintenir la tension sur la borne de sortie (V_out) au niveau présélectionné désiré.

4. Circuit régulateur de haute tension à l'état solide selon la revendication 3, comprenant en outre une pluralité d'étages à composants additionnels (12a, 12b, 12c) couplé en cascade avec le premier étage à composants (14), la pluralité d'étages à composants additionnels (12a, 12b, 12c) couplant le conducteur d'entrée (30) du premier étage à composants (14) à la borne de sortie (V_out), chacun des étages à composants additionnels (12a, 12b, 12c) possédant un conducteur d'entrée et un conducteur de sortie et ayant un trajet de courant des composants, qui est normalement non conducteur entre les conducteurs d'entrée et de sortie, dans lequel chacun de la pluralité d'étages à composants additionnels (12a, 12b, 12c) est configuré de manière à amener le trajet de courant des composants de l'étage à composants additionnels à devenir conducteur en tant que fonction du courant circulant dans le trajet de courant réglé.

5. Circuit régulateur de haute tension à l'état solide selon la revendication 2, dans lequel l'étage de régulation de courant (14, 12a, 12b, 12c; 55) inclut au moins un transistor à effet de champ (TRA), dont la région de canal est couplé entre les conducteurs d'entrée et de sortie de l'étage de régulation, la région du canal constituant au moins une partie du trajet de courant réglé.

6. Circuit régulateur de haute tension à l'état solide selon la revendication 2, dans lequel l'étage de régulation du courant (14, 12a, 12b, 12c) est configuré de manière à augmenter le courant circulant dans le trajet de courant réglé lorsque le niveau de tension sur la borne de tension (V_out) dépasse le niveau présélectionné de manière à augmenter le courant circulant dans l'impédance de détection (RS), en amenant ainsi la tension sur la borne de sortie (V_out) à diminuer dans la configuration shunt.

7. Circuit régulateur de haute tension à l'état solide selon la revendication 2, caractérisé en outre en ce que l'étage de régulation du courant (55) est configuré de manière à réduire le courant circulant dans le trajet de courant réglé et dans l'impédance de détection (RS) lorsque le niveau de tension sur la borne de sortie (V_out) est supérieur au niveau préréglé de manière à réduire le courant circulant dans l'impédance de détection (RS), ce qui amène la tension sur la borne de sortie (V_out) à diminuer dans la configuration série.

8. Circuit régulateur de haute tension à l'état solide selon la revendication 4, caractérisé en outre en ce que le premier étage à composants comprend en outre:

(a) un circuit à diode (DB) couplé pour recevoir une tension de polarisation sensiblement constante; et

(b) un transistor à effet de champ (TRA) dont la grille est couplée de manière à recevoir le signal de sortie de la diode (DB) et dont la région de canal est couplée entre les conducteurs d'entrée et de sortie du premier étage à composants, la région de canal du transistor à effet de champ (TRA) formant au moins une partie du premier trajet de courant des composants.

9. Circuit régulateur de haute tension à l'état solide selon la revendication 8, dans lequel chacun de la pluralité d'étages à composants additionnels (12a, 12b, 12c) comprend:

(a) un circuit à diode (DB) couplé pour recevoir la tension de polarisation; et

(b) un transistor à effet de champ (TR) dont la grille est couplée de manière à recevoir un signal de sortie de la part du circuit à diode correspondant (DB) et dont la région de canal est couplée aux conducteurs d'entrée et de sortie de son étage à composants additionnels correspondant, le circuit à diode (DB) de chacun de la pluralité d'étages à composants additionnels (12a, 12b, 12c) possédant un nombre accru de diodes montées en cascade que le circuit à diode (DB) de l'étage à composants additionnels couplé, au plus près en second, au premier étage à composants (14).

10. Circuit régulateur de haute tension à l'état solide selon la revendication 9, dans lequel le nombre différent de diodes dans les circuits à diodes (DB) de la pluralité d'étages à composants additionnels (12a, 12b, 12c) empêche chacun de la pluralité d'étages à composants additionnels de devenir conducteurs avant que l'étage à composants couplé, au plus près en second, au premier étage à composants (14).

11. Circuit régulateur de haute tension à l'état solide selon la revendication 4, comprenant en outre une pluralité de circuits de shuntage (DD, CD), chacun de la pluralité de circuits de shuntage (DD, CD) étant couplé à des conducteurs d'entrée et de sortie d'un étage à composants correspondant (12a, 12b, 12c) et du premier étage à composants (14), chaque circuit de shuntage (DD, CD) étant configuré de manière à former un trajet de courant qui contourne l'étage à composants correspondants lorsque le trajet de courant de l'étage à composants correspondant est non conducteur.

12. Circuit régulateur de haute tension à l'état solide selon la revendication 11, dans lequel la pluralité d'étages à composants additionnels (12a, 12b, 12c) sont configurés de telle sorte que, lorsque le transistor à effet de champ (TR) de l'un de la pluralité d'étages à composants additionnels est polarisé dans un mode de fonctionnement linéaire, le transistor à effet de champ (TR) de chacun, s'il en existe un, de la pluralité d'étages à composants (12a, 12b, 12c) couplés au plus près de l'étage régulateur (14) étant polarisés dans un mode de saturation, et le transistor à effet de champ (TR) de chacun, s'il en existe un, de la pluralité d'étages à composants (12a, 12b, 12c) couplé dans une position plus éloignée de l'étage régulateur (14) est polarisée dans un mode non conducteur.

Drawing