Capacitor, display driving circuit and display device

Description

BACKGROUND

Field of the Invention

[0001] The present invention relates to a capacitor. More specifically, the present invention relates to a space-saving capacitor circuit for use in the pixel area of a light emitting display device. The present invention further relates to a display driving circuit and to a display device.

Description of the Related Technology

[0002] Generally, a flat display panel (FDP), is a display device, in which light emitting elements are arranged between two substrates. The importance of the FDP has been emphasized following the development of multimedia technologies. In response to this trend, various flat displays such as the liquid crystal display (LCD) using a method for scattering light as the liquid crystals are roiled by an applied voltage, the field emission display using a phosphor light emission by electron beam, and the organic light emitting display device (hereinafter, referred to as an OLED device) using light emission of organic materials have been developed.

[0003] There are a passive matrix method and an active matrix method to provide control circuits of FDP devices. In the passive matrix method, electrodes are formed crossing each other, and a line is selected in order to drive the device. The active matrix method uses thin film transistors (TFT) for driving light emitting elements of FDP devices. In the active matrix method, the FDP device operates in response to a voltage maintained by capacitance of a capacitor coupled to a gate of the thin film transistor.

[0004] A unit capacitor is disclosed in EP-A-698927. An active matrix type organic electroluminescent display device is disclosed in WO-A-03/071 511.

[0005] FIG. 1 shows a circuit diagram of an OLED device, for example. As shown in FIG. 1, a pixel circuit of the OLED device include an organic light emitting diode OLED, two transistors M1 and M2, and a capacitor C_st. A power voltage VDD is coupled to a source of the driving transistor M2, and the capacitor C_st is coupled between a gate and a source of the driving transistor M2. The capacitor C_st maintains a gate-source voltage of VGS of the driving transistor M2 for a predetermined period. The switching transistor M1 transmits a data voltage from a data line Dm to the gate of the transistor M2 in response to a selection signal from a current scan line Sn. A cathode of the organic light emitting diode OLED is coupled to a reference voltage of Vss and emits a light corresponding to a current applied through the driving transistor M2.

[0006] As shown, in the active matrix method, each pixel circuit includes a thin film transistor and a capacitor, and the pixel circuit operates in response to a voltage maintained by capacitance of the capacitor C_st that is coupled to the gate of the thin film transistor. A display quality of the pixel is better when comparing to the passive matrix method because an image corresponding to a data signal is continuously displayed in a frame, and therefore the active matrix method has become very popular these days.

[0007] FIG. 2 shows a sectional view of a configuration of a capacitor used in a display panel. A buffer layer 11 is formed on a substrate 10, and a conductive layer 12 forming an electrode of the capacitor is formed on the buffer layer 11. An insulation layer 13 is formed on the conductive layer 12, and a conductive layer 14 forming another electrode of the capacitor is formed on the insulation layer 13. Therefore the capacitor including the conductive layer 12 and the conductive layer 14 is formed. The capacitor is formed in an area forming a pixel circuit, and the horizontal widths of the capacitor are designed in view of the capacitance required according to characteristics of the display panel.

[0008] A thin film transistor is formed on a pixel area of the display panel in the active matrix method as well as the capacitor having a predetermined width, which may limit an area for forming display elements. Accordingly, an aperture ratio of the display panel may be decreased in an active matrix display device.

[0009] Further, OLED devices tend to use a pixel circuit having more than two capacitors and a plurality of thin film transistors in order to compensate a threshold voltage of a driving transistor. In such devices, the aperture ratio may be further decreased. In response to the trend, there is a high demand for a space-saving capacitor having proper capacitance in the pixel area.

[0010] The information disclosed in this Background of the Invention section is only for understanding of the background of the invention, and therefore, unless explicitly described to the contrary, it should not be taken as an admission of prior art.

SUMMARY OF CERTAIN INVENTIVE ASPECTS

[0011] The present invention provides a capacitor circuit for use in a display control circuit as recited in claim 1.

[0012] The present invention further provides a display driving circuit as recited in claim 5.

[0013] The present invention further provides a display device as recited in claim 9.

[0014] In the following detailed description, only the embodiments of the invention have been shown and described, simply by way of illustration of the best modes contemplated by the inventor(s) of carrying out the invention. As will be realized, the invention is capable of modification in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG. 1 shows a circuit representing a display element or pixel circuit of an OLED device.

[0016] FIG. 2 shows a sectional view of a configuration of a capacitor formed on a substrate of a display panel.

[0017] FIG. 3 shows a configuration of display elements and driving circuits of an OLED device according to an embodiment of the present invention.

[0018] FIG. 4 shows a circuit representing a pixel circuit of an OLED device according to an embodiment of the present invention.

[0019] FIG. 5 shows a top plan view of an integrated circuit layout of the pixel circuit shown in FIG. 4.

[0020] FIG. 6 shows a sectional view taken along the line I-I' shown in FIG. 5.

[0021] FIG. 7 shows a sectional view taken along the line II-II' shown in FIG. 5 for representing a sectional configuration of capacitors C_st and C_vth.

[0022] FIG. 8 shows a circuit representing the configuration shown in FIG. 7.

[0023] FIG. 9 shows a circuit representing the configuration shown in FIG. 7 when a previous selection signal Sn-1 is applied.

[0024] FIG. 10 shows a diagram representing potential of polysilicon layers 426 and 424 and electrodes 445 and 447 when the previous selection signal Sn-1 is applied.

[0025] FIG. 11 shows a circuit representing the configuration shown in FIG. 7 when a current selection signal Sn is applied.

[0026] FIG. 12 shows a diagram representing potential of the polysilicon layers 426 and 424 and the electrodes 445 and 447 when the current selection signal Sn is applied.

DETAILED DESCRIPTION OF EMBODIMENTS

[0027] In the specification, like elements are denoted by like numerals. When an element is coupled to another element, the element may be directly coupled to the other element or coupled to the other element via a third element. When an element is formed on or over another element, the element may be formed right on the other element or formed on the other element including a third element therebetween.

[0028] Various embodiments of the invention are now discussed in the context of an organic light emitting display (OLED) device. However, the principle disclosed in the following embodiments can be applied in any flat display panel devices, including liquid crystal displays, field emission displays, plasma displays, etc.

[0029] As to the definitions, a scan line which is transmitting a current selection signal is referred to as a "current scan line," and a scan line which transmitted a selection signal immediately before the current selection signal is referred to as a "previous scan line." A scan line which is transmitting the current select signal is referred to as a "current scan line," and a scan line which transmitted the select signal before the current select signal is transmitted is referred to as a "previous scan line." Further, a scan line which transmits the selection signal immediately after the current selection signal is referred to as a "next scan line." Some components belonging to the immediately above pixel (Pn-1) are shown in FIG. 5 and (') is added to their reference numbers.

[0030] As shown in FIG. 3, the OLED device includes an array of display elements 100, a scan driver 200, and a data driver 300. The display array 100 includes a plurality of data lines D1 to Dm extending in the column direction, a plurality of scan line S1 to Sn (while it is referred to as a gate line, hereinafter, it will be referred to as the scan line) extending in the row direction, and a plurality of pixel circuits 110. The data lines D1 to Dm transmit data signals representing an image signal to the pixel circuits 110. The scan lines S1 to Sn transmit selection signals to the pixel circuits 110. Each pixel circuit 110 is formed in a pixel area defined between two neighboring data lines and between two neighboring scan lines.

[0031] The scan driver 200 sequentially applies a selection signal to each of the respective scan lines S1 to Sn. The data driver 300 applies data voltages representing the image signal to the data lines D1 to Dm.

[0032] FIG. 4 shows an equivalent circuit representing a pixel circuit 110 of the OLED device according to an embodiment of the present invention. The illustrated embodiment is a pixel circuit coupled to an m-th data line Dm, a current scan line Sn, and a previous scan line Sn-1. The pixel circuit includes five transistors M1 to M5, two capacitors C_st and C_vth, and an organic light emitting diode (OLED).

[0033] The transistor M1 for driving the organic light emitting diode OLED is coupled between a voltage source VDD and the organic light emitting diode OLED. The transistor M1 transmits a current to the organic light emitting diode OLED via the transistor M2 depending upon the voltage applied to a gate of the transistor M1. The gate of the transistor M1 is coupled to a node A of the capacitor C_vth. The capacitor C_st and the transistor M4 are coupled in parallel between a node B of the capacitor C_vth and the power voltage VDD.

[0034] The transistor M5 transmits a data voltage of the data line Dm to the node B of the capacitor C_vth in response to the selection signal from the current scan line Sn. The transistor M4 couples between the node B of the capacitor C_vth and the power voltage VDD in response to the selection signal from the previous scan line Sn-1. The transistor M3 allows the transistor M1 to be diode-connected in response to the selection signal from the previous scan line Sn-1. The transistor M2 is coupled between the drain of the transistor M1 and the anode of the OLED, and intercepts the drain of the transistor M1 to the OLED in response to the selection signal from a light emitting control line En. The OLED emits a light corresponding to a current input from the transistor M2.

[0035] An operation of the pixel circuit will now be described. A low level selection signal is applied to the previous scan line Sn-1, the transistor M3 is turned on, and the transistor M1 is diode-connected. Accordingly, a voltage between the gate and the source of the transistor M1 varies until the voltage reaches a threshold voltage V_th of the transistor M1. The power voltage VDD is connected to the source of the transistor M1. Once the gate-source voltage of the transistor M1 reaches VDD+V_th, a voltage applied to the gate of the transistor M1 (the node A of the capacitor C_vth) is a sum of the power voltage VDD and the threshold voltage V_th. Also, the transistor M4 is turned on by the low level selection signal of scan line Sn-1, and the power voltage VDD is applied to the node B of the capacitor C_vth. The voltage of the capacitor C_vth is given as Equation 1.

[0036] In the foregoing equation, V_Cvth denotes a voltage drop between the two electrodes of the capacitor C_vth. V_CvthA denotes a voltage applied to the node A of the capacitor C_vth, and V_CvthB denotes a voltage applied to the node B of the capacitor C_vth.

[0037] Meanwhile, the transistor M2 which is an n-channel transistor is turned off by a low level signal of the light emitting control line En, and prevents current through the transistor M1 from flowing to the OLED. The transistor M5 is turned off because a high level signal is applied to the current scan line Sn when the current scan line Sn-1 is applied a low level signal.

[0038] When the low level selection signal is applied to the current scan line Sn, the transistor M5 is turned on, and a data voltage V_data is applied to the node B. The sum of the data voltage V_data and the threshold voltage V_th of the transistor M1 is applied to the gate of the transistor M1 because the threshold voltage V_th of the transistor M1 was applied to the capacitor C_vth during the previous scan (Sn-1) and the charge has not been cleared. The voltage V_gs between the gate and the source of transistor M1 is given as Equation 2. At this time, the low level signal is applied to the light emitting control line En and the transistor M2 is turned off.

[0039] The transistor M2 is turned on when the high level of the light emitting control line En is applied. Then, a current I_OLED flows to the OLED, and the OLED emits a light. The current I_OLED is given as Equation 3.

[0040] Here, I_OLED denotes current flowing through the OLED. V_gs denotes a voltage between the source and the gate of the transistor M1. V_th denotes a threshold voltage of the transistor M1. V_data denotes a data voltage, and β denotes a constant specific to the transistor M1.

[0041] As can be seen in Equation 3, in the illustrated pixel circuit, the current supplied to the organic light emitting diode OLED is independent of any deviation of the threshold voltage V_th of the transistor M1..

[0042] An arrangement of the pixel circuit according to the embodiment of the present invention will be described with reference to FIG. 5 and FIG. 6. FIG. 5 shows a top plan view representing an arrangement of the pixel circuit shown in FIG. 4, and FIG. 6 shows a sectional view taken along the dotted line I~I' shown in FIG. 5.

[0043] A polysilicon layer is used for a semiconductor layer, in FIG. 5. In FIG. 6, the areas doped with an n+ or p+ impurity are hatched. The blank (non-hatched) areas are intrinsic areas in the polysilicon layer. That is, channel areas of transistors respectively crossing gate electrode lines 442 and 443 are non-doped blank areas. On the other hand, drains and sources of the transistors are doped with the n+ or p+ impurities and therefore hatched.

[0044] Two pixel circuits are illustrated in FIG. 5, an upper pixel is a current pixel and a lower pixel is a next pixel. As shown in FIG. 5 and FIG. 6, a buffer layer 410 including a silicon dioxide is formed on an insulation substrate 400, and the polysilicon layers 421, 422, 423, 424, and 426 which are semiconductor layers are formed on the buffer layer 410.

[0045] In FIG. 5, the polysilicon layer 421 which is the semiconductor layer is formed in a lower part of the pixels in about "U" shape, and forms source, drain, and channel areas of the switching transistor M5 of the current pixel. The polysilicon layer 421' which is the semiconductor layer is formed in the like manner of the polysilicon layer 421, and forms source, drain, and channel areas of the switching transistor M5' of the previous pixel.

[0046] The polysilicon layer 422 is formed neighboring the polysilicon layer 421' in about "⊂" shape, and forms source, drain, and channel areas of the transistor M3 of the current pixel.

[0047] The polysilicon layer 423 is elongated in a middle of FIG. 5 in the column direction, and forms source, drain, and channel areas of the transistor M1 and source, drain, and channel areas of the transistor M2. The polysilicon layer 423 is arranged to be coupled to the polysilicon layer 422 as shown in FIG. 6, and the source area of the transistor M3 is electrically connected to the drain area of the transistor M1.

[0048] The polysilicon layer 424 is formed in a right side of the polysilicon layer 423 in about "U" shape, and forms source, drain, and channel areas of the transistor M4.

[0049] The polysilicon layer 426 is widely formed in the upper part of FIG. 5 in about "n" shape, and includes a first area forming an electrode of the capacitor C_vth in a left side and a second area forming an electrode of capacitor C_st in a right side. The first area and the second area are formed in a single body, and form a common electrode (node B shown in FIG. 4). The polysilicon layer 426 is electrically connected to the polysilicon layer 424, and coupled to the drain area of the transistor M4 and the electrodes of the capacitor C_st and capacitor C_vth.

[0050] As shown in FIG. 6, a gate insulating layer 430 is formed on the polysilicon layer 421, 422, 423, 424, and 426 formed as above.

[0051] Referring back to FIG. 5, electrode lines for forming gates and electrodes (hereinafter referred to as a "gate layer") are formed on the gate insulating layer 430. The gate layer includes an electrode line 441 corresponding to a current scan line Sn, an electrode line 442 corresponding to the light emitting control line En, an electrode line 443 corresponding to the previous scan line Sn-1, an electrode 445 corresponding to another electrode of the capacitor C_st, and an electrode 447 corresponding to another electrode of the capacitor C_vth.

[0052] The electrode line 441 which is elongated in the row direction crosses the polysilicon layer 421, and forms a gate of the transistor M5 of the current pixel. The electrode line 442 which is elongated in the row direction crosses the polysilicon layer 423, and forms the gate of the transistor M2 of the current pixel. The electrode line 443 which is elongated in the row direction crosses the polysilicon layer 422 and the polysilicon layer 424, and respectively forms the transistor M3 and the transistor M4 of the current pixel. The electrode line 443 also crosses the polysilicon layer 421' and forms the transistor M5' of the previous pixel.

[0053] The electrode 445 is overlapped with the second area (right side) of the doped polysilicon layer 426 forming the electrode (node B shown in FIG. 4) of the capacitor C_st, and forms the other electrode of the capacitor C_st. The electrode 447 is overlapped with the first area (left side) of the doped polysilicon layer 426 forming the electrode (node B) of the capacitor C_vth, and forms the other electrode (node A) of the capacitor C_vth. The electrode 447 is elongated crossing the polysilicon layer 423, and forms the gate of the transistor M1 (node A) electrically connected to the other electrode of the capacitor C_vth.

[0054] As shown in FIG. 6, the gate electrodes 441, 442, 443, 445, and 446 are formed on an interlayer insulating layer 450. A power electrode line 461, a data line 463, connecting electrode lines 465, 467, and 468 are formed on the interlayer insulating layer 450.

[0055] Referring to FIG. 5, the power electrode line 461, the data line 463, and the connecting electrode lines 465, 467, and 468 are electrically connected to elements through contact holes 451a, 451 b, 451c, 453a, 453b, 454, 455, 457, and 458. As shown in FIG. 5, the contact holes 451a, 451 b, 451c, 453a, 454, 457, and 458 represented by "■" are contact holes touching the polysilicon layer through the interlayer insulating layer 450 and the gate insulating layer 430, and the contact holes 453b and 455 represented by " " are contact holes touching the gate layer through the interlayer insulating layer 450.

[0056] The power electrode line 461 which is elongated in the column direction is widely formed in an area forming the capacitors C_st and C_vth. The power electrode line 461 contacts the source area of the transistor M1 of the polysilicon layer 423 through the contact hole 454 and is electrically connected to the source of the transistor M1. The power electrode line 461 contacts the electrode 445 through the contact hole 455 and is electrically connected to the other electrode of capacitor C_st. The power electrode line 461 contacts the source area of the transistor M4 of the polysilicon layer 424 through the contact hole 457 and is electrically connected to the source of the transistor M4.

[0057] The data line 463 is elongated in the column direction, contacts the source area of the transistor M5 of the polysilicon layer 421 through the contact hole 451 b, and is electrically connected to the source of the transistor M5. The data line 463 contacts the source area of the transistor M5' of the polysilicon layer 421' through the contact hole 451b', and is electrically connected to the source of the transistor M5'.

[0058] The connecting electrode line 465 contacts the drain area of the transistor M5 of the polysilicon layer 421 through the contact hole 451a, and also contacts a part of the polysilicon layer 426 through the contact hole 451c. That is, the connecting electrode line 465 electrically connects the drain of the transistor M5 to the electrode (node B) of the capacitor C_vth. The connecting electrode line 467 contacts the drain area of the transistor M3 of the polysilicon layer 422 through the contact hole 453a as shown in FIG. 6, and contacts the electrode 447 through the contact hole 453b. That is, the connecting electrode line 467 electrically connects the drain of the transistor M3 to the other electrode (node A) of the capacitor C_vth.

[0059] The connecting electrode 468 is formed neighboring the electrode line 442 as shown, contacts the drain area of the transistor M2 of the polysilicon layer 423 through the contact hole 458, and electrically connects the drain of the transistor M2 to an anode electrode (not shown) of the organic light emitting diode OLED formed on the connecting electrode 468.

[0060] A planarization layer 470 is formed on the above configured power electrode line 461, data line 463, and connecting electrode lines 465, 467, and 468. While the anode of the organic light emitting diode is not illustrated, the anode contacts the connecting electrode 468 through the contact hole penetrating the planarization layer 470, and is electrically connected to the drain of the transistor M2. A pixel define layer (PDL) is formed after the pixel electrode is formed, and a multi-layer structured organic layer including a light emitting layer (EML), an electron transport layer (ETL), and a hole transport layer (HTL) is formed on the pixel electrode of the light emitting area defined by the PDL.

[0061] As described, the capacitors C_vth and C_st are coupled to each other, and the polysilicon layer 426 is formed as the common electrode (node B) of the capacitors C_vth and C_st. The layers 445 and 447 are respectively formed as the other electrode of the capacitors C_vth and C_st according to the arrangement of the illustrated embodiment.

[0062] Arrangement and connection of the two capacitors C_st and C_vth coupled to each other in series will be described with reference to FIG. 7 to FIG. 12.

[0063] FIG. 7 shows a sectional view taken along the line II-II' shown in FIG. 5 for representing a sectional configuration of capacitors C_st and C_vth, and FIG. 8 shows an equivalent circuit diagram representing the configuration shown in FIG. 7.

[0064] In FIG. 7, the buffer layer 410 is formed on a substrate 400, and the polysilicon layer 426 and the polysilicon layer 424 in a single body are formed on the buffer layer 410. The polysilicon layer 426 is substantially entirely doped with n+ or p+ impurities and forms the common electrode (node B) of the capacitors C_vth and C_st. The polysilicon layer 424 forms source 424s, drain 424d, and channel 424c areas of the transistor M4. In FIG. 7, the hatched areas of the polysilicon layer 424 are doped with impurities and are the source 424s and drain 424d areas of the transistor M4, respectively. The area 424c of the polysilicon layer 424 located between the source 424s and drain 424d areas is not doped with impurities and forms the channel area 424c of the transistor M4. Accordingly, the common electrode (node B) of the capacitors C_st and C_vth is electrically connected to the drain of the transistor M4 because the polysilicon layer 426 (the common electrode) is directly coupled to the polysilicon layer 424d (drain of M4). The electrodes 445 and 447 are formed over a dielectric layer 428, which is formed on the polysilicon layer 426. The polysilicon layer 426, the electrode 445 and the intervening dielectric layer 428 form the capacitor C_st. The polysilicon layer 426, the electrode 447 and the intervening dielectric layer 428 form the capacitor C_vth. The connecting electrode 465 is electrically connected to the drain of the transistor M5 and contacts a terminal portion of the polysilicon layer 426 via the interconnect 451c. The data voltage V_data applied to the drain of the transistor M5 is transmitted to the polysilicon layer 426 when the transistor M5 is turned on in response to the current selection signal Sn.

[0065] The layers 443 is connected to the previous scan line Sn-1 and is provided over the intervening dielectric layer 428 formed on the channel area 424c of the polysilicon layer 424, and forms the gate of the transistor M4. Dielectric layers 450 are deposited over the structures 428, 445, 447 and 450. A layer 461 is formed over the dielectric layers 450 and forms a power electrode line. The power electrode line 461 contacts the source area 424s of the transistor M4 via the interconnect 457. Accordingly, when the transistor M4 is turned on in response to the previous selection signal Sn-1, the power voltage VDD is applied to the polysilicon layer 426 through the transistor M4.

[0066] The transistor M5, transistor M4, capacitors C_vth and C_st as configured in FIG. 7 is equivalently represented by FIG. 8. When a low level is applied to the selection signal Sn-1 of the previous scan line, the transistor M4 is turned on and the power voltage VDD is applied to the node B. When the low level is applied to the selection signal Sn of the current scan line, the transistor M5 is turned on and the data voltage V_data is applied to the node B.

[0067] Referring to FIG. 9 to FIG. 12, operations of the capacitors C_st and C_vth in a case that the previous selection signal Sn-1 is applied and in a case that the selection signal Sn is applied will be described.

[0068] FIG. 9 shows an equivalent circuit diagram representing the configuration shown in FIG. 7 when the previous selection signal Sn-1 is applied, and FIG. 10 shows a diagram representing potential of the polysilicon layers 426 and 424 and the electrodes 445 and 447 when the previous selection signal Sn-1 is applied.

[0069] A solid line shown in FIG. 9 shows that the transistor M4 is turned on and the power voltage VDD is applied to the node B when the selection signal Sn-1 is at the low level.

[0070] As shown in FIG. 10, a channel is formed in the channel area 424c of the polysilicon layer 424, and the power voltage VDD is applied to the source area 424s. The power voltage VDD is transmitted to the polysilicon layer 426 through the drain area 424d, and the potential of the polysilicon layers 424 and 426 is VDD. The power voltage VDD is applied to the electrode 445 via the interconnect 455. A first capacitor C_vth1 is formed between the electrode 447 (Note A) and the polysilicon layer 426 (node B) at the potential VDD, and a second capacitor C_vth2 is formed between the electrode 447 (node A) and the electrode line 461 at the same potential VDD, and therefore a multi-layer capacitor is formed. The first capacitor C_vth1 and second capacitor C_vth2 are parallelly connected as shown in FIG. 9. The potential of the polysilicon layer 426 is identical to that of the electrode 445, and therefore these layers do not operate as a capacitor as shown with dotted line in FIG. 9.

[0071] The current selection signal Sn is applied after the previous selection signal Sn-1 is applied. FIG. 11 shows an equivalent circuit diagram representing the configuration shown in FIG. 7 when the current selection signal Sn is applied. FIG. 12 shows a diagram representing the potentials of the polysilicon layers 426 and 424 and the electrodes 445 and 447 when the current selection signal Sn is applied.

[0072] FIG. 11 shows that the transistor M4 (dotted lines) is turned off and the transistor M5 (solid lines) is turned on when the selection signal Sn is at the low level. At this time, the data voltage V_data applied to the data line 463 (shown in FIG. 5) is applied to the node B.

[0073] In FIG. 12, the transistor M4 is turned off, and the power electrode line 461 is not equipotential with the polysilicon layer 426 which is one of the electrodes of the capacitor C_vth. The transistor M5 is turned on in response to the selection signal Sn, and the data voltage V_data is applied to the polysilicon layer 426 through the connecting electrode line 465. The potential of the electrode 445 is VDD because the electrode 445 is electrically connected to the power electrode line 461 via the interconnect 455. Accordingly, the polysilicon layer 426 and the electrode 445 form the capacitor C_st with a potential difference between V_data and VDD.

[0074] As described, the polysilicon layer 426 forms the common electrode (node B) of the capacitors C_st and C_vth, and therefore it is not necessary to form additional contact hole and an interconnect or extension between the drain of the transistor M4 and the common electrode 126 of the capacitor C_st and capacitor C_vth. The lacking of the contact holes makes the process of pixel formation simpler and less costly. Further, the aperture ratio can be improved because the light emitting area is increased by reducing the space needed for such interconnects and/or extensions.

[0075] In addition, sufficient capacitance is guaranteed because a planar area is narrowed by forming the capacitor C_vth as a multi-layer capacitor and two connecting electrodes performs an electrode of a capacitor. The capacitor C_st is coupled to the capacitor C_vth through the polysilicon layer 426, and therefore it is not necessary to form an additional connecting electrode for coupling the two capacitors. Accordingly, an area in which the two capacitors are provided is reduced in the pixel area, and the aperture ratio is improved because an area including the connecting electrode is reduced in the pixel area.

[0076] Accordingly to the exemplary embodiments of the present invention, it is not necessary to form the additional contact hole and connecting electrode line in order to couple the drain of the transistor to the common electrode of the capacitors C_st and C_vth because the polysilicon layer forms the common electrode of the capacitors C_st and C_vth coupled in series. The reduction of the contact holes allows a process of pixel formation to be more convenient, and the aperture ratio is improved because the light emitting area is increased by the reduction of the connecting electrode lines.

[0077] In addition, sufficient capacitance is guaranteed because a planar area is narrowed by forming the capacitor C_vth as a multi-layer capacitor and two connecting electrodes performs an electrode of a capacitor. The capacitor C_st is coupled to the capacitor C_vth through the polysilicon layer 426 in series, and therefore it is not necessary to form the additional connecting electrode for coupling the two capacitors in series. Accordingly, the area in which the two capacitors are provided is reduced in the pixel area, and the aperture ratio is improved because an area including the connecting electrode is reduced in the pixel area

[0078] In the exemplary embodiments of the present invention, the OLED device has been exemplified, the present invention covers display devices and semiconductor devices in which two capacitors are coupled to each other in series.

[0079] While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A capacitor circuit for use in a display control circuit, the capacitor comprising:

a first conductive layer (426) formed in a single body;

a first insulation layer (430) formed on the first conductive layer (426);

a second conductive layer (445) and a third conductive layer (447) separately formed on the first insulation layer (430);

a second insulation layer (450) formed on the second conductive layer (445) and the third conductive layer (447), and

a fourth conductive layer (461) formed on the second insulation layer (450) and electrically connected to the second conductive layer (445),

characterized in that the first conductive layer (426) is electrically connected to the fourth conductive layer (461) through a first switch (M4) adapted to be turned on in a first period and a second potential (V_Data) is applied to the first conductive layer (426) through a second switch (M5) adapted to be turned on in a second period.

2. The capacitor of claim 1, wherein fourth conductive layer (461) is overlapped with at least a part of the third conductive layer (447).

3. The capacitor of claim 1, wherein the first conductive layer (426) is a polysilicon layer doped with one or more impurities; second conductive layer (445) and the third conductive layer (447) is a first metal layer, and the fourth conductive layer (461) is a second metal layer formed on the second insulation layer (450) and electrically connected to the second conductive layer (445).

4. The capacitor circuit of claim 1, wherein the first conductive layer (426) and the second conductive layer (445) comprise a capacitor and/or wherein the second conductive layer (445) and fourth conductive layers (461) comprise a capacitor and/or wherein the first conductive layer (426) and the third conductive layer (447) comprise a capacitor and/or wherein the third conductive layer (447) is located at a level between the first and fourth conductive layers (426, 461) and/or wherein the third conductive layer (447) is located at substantially the same level as the second conductive layer (445).

5. A display driving circuit, comprising:

a first capacitor (Cvth) comprising a first electrode (426) and a fourth electrode (461), the fourth electrode (461) being electrically connected to a first voltage (VDD);

a second capacitor (Cst) comprising the first electrode (426) and a second electrode (445);

characterized by

a first switch (M4) interconnecting the first and fourth electrodes (426, 461), wherein when turned on, the first switch (M4) is configured to equipotentially connect the first and fourth electrodes (426, 461), thereby connecting the first voltage (VDD) to the first electrode (426); and a second switch (M5) interconnecting the first electrode (426) and a fifth electrode, the fifth electrode being electrically connected to a second voltage (V_data), wherein when turned on, the second switch (M5) is configured to equipotentially connect the first electrode (426) and fifth electrode, thereby connecting the second voltage (V_data) to the first electrode (426).

6. The display driving circuit of claim 5, wherein the first electrode (426) comprises a polysilicon layer.

7. The display driving circuit of claim 5, wherein the first capacitor (Cvth) further comprises a third electrode (447) electrically insulated from both the first and fourth electrodes (426, 461), wherein the first and third electrodes (426, 447) comprise a first sub-capacitor (Cvth1), and wherein the fourth and third electrodes (461, 447) comprise a second sub-capacitor (Cvth2).

8. The display driving circuit of claim 5, wherein the second capacitor (Cst) is configured to be charged with a voltage, which is a difference between the first voltage (VDD) and the second voltage (V_data) while the second switch (M5) is turned on.

9. A display device comprising an array of a plurality of display units (110), at least one of the display units (110) comprising:

a first conductive layer (426);

a fourth conductive layer (461) over the first conductive layer (426);

a third conductive layer (447) located between the first and fourth conductive layers (426, 461), the third conductive layer (447) is electrically insulated from both the first and fourth conductive layers (426, 461); and

a second conductive layer (445) located over the first conductive layer (426), the second conductive layer (445) is at a substantially equipotential with the third conductive layer (447),

characterized in that

the display further comprises a circuit interconnecting the first and fourth conductive layers (426, 461), wherein the circuit is configured to receive a first control signal and a second control signal, wherein when the first control signal is received, the circuit is configured to substantially equipotenitally connect the first and fourth conductive layers (426, 461), and wherein when the second control signal is received, the circuit is configured to have a voltage drop therein.

10. The display device of claim 9, wherein the first conductive layer (426) comprises a polysilicon layer doped with impurity.

11. The display device of claim 9, wherein at least one of the second and third conductive layers (445, 447) comprises a metal electrode layer.

12. The display device of Claim 9, wherein the circuit comprises a transistor (M4) comprising a gate, a source and a drain, wherein the gate is configured to receive the first and second control signals, wherein the source is electrically connected to the fourth conductive layer (461), and wherein the drain is electrically connected to the first conductive layer (426) and/or wherein, when the second control signal is received, the first conductive layer (426) is electrically connected to an electrode other than the fourth conductive layer (426).

13. The display device of claim 9, wherein the first and third conductive layers (426, 447) comprise a capacitor and/or wherein the third and fourth conductive layers (447, 461) comprise a capacitor and/or wherein first and second conductive layers (426, 445) comprise a capacitor.

Ansprüche

1. Ein Kondensatorschaltkreis zur Verwendung in einem Anzeigesteuerschaltkreis, wobei der Kondensator umfasst:

eine erste leitende Schicht (426), die in einem einzigen Körper ausgebildet ist;

eine erste Isolierschicht (430), die auf der ersten leitenden Schicht (426) ausgebildet ist;

eine zweite leitende Schicht (445) sowie eine dritte leitende Schicht (447), die getrennt auf der ersten Isolierschicht (430) angeordnet sind;

eine zweite Isolierschicht (450), die auf der zweiten leitenden Schicht (445) und der dritten leitenden Schicht (447) ausgebildet ist, und

eine vierte leitende Schicht (461), die auf der zweiten Isolierschicht (450) ausgebildet ist und elektrisch mit der zweiten leitenden Schicht (445) verbunden ist,

dadurch gekennzeichnet, dass

die erste leitende Schicht (426) durch einen ersten Schalter (M4), der dazu ausgelegt ist, in einem ersten Zeitabschnitt eingeschaltet zu sein, elektrisch mit der vierten leitenden Schicht (461) verbunden ist und ein zweites Potential (V_Data) durch einen zweiten Schalter (M5), der dazu ausgelegt ist, in einem zweiten Zeitabschnitt eingeschaltet zu sein, an die erste leitende Schicht (426) angelegt wird.

2. Der Kondensator nach Anspruch 1, wobei die vierte leitende Schicht (461) mit mindestens einem Teil der dritten leitenden Schicht (447) überlappt ist.

3. Der Kondensator nach Anspruch 1, wobei die erste leitende Schicht (426) eine mit einem oder mehreren Fremdatomen dotierte Polysiliziumschicht ist; die zweite leitende Schicht (445) und die dritte leitende Schicht (447) eine erste Metallschicht ist und die vierte leitende Schicht (461) eine auf der zweiten Isolierschicht (450) ausgebildete und elektrisch mit der zweiten leitenden Schicht (445) verbundene zweite Metallschicht ist.

4. Der Kondensatorschaltkreis nach Anspruch 1, wobei die erste leitende Schicht (426) und die zweite leitende Schicht (445) einen Kondensator umfassen und/oder wobei die zweite leitende Schicht (445) und vierten leitenden Schichten (461) einen Kondensator umfassen und/oder wobei die erste leitende Schicht (426) und die dritte leitende Schicht (447) einen Kondensator umfassen und/oder wobei die dritte leitende Schicht (447) auf einer Ebene zwischen den ersten und vierten leitenden Schichten (426, 461) angeordnet ist und/oder wobei die dritte leitende Schicht (447) im Wesentlichen auf derselben Ebene wie die zweite leitende Schicht (445) angeordnet ist.

5. Ein Anzeigeansteuerschaltkreis, umfassend:

einen eine erste Elektrode (426) und eine vierte Elektrode (461) umfassenden ersten Kondensator (Cvth), wobei die vierte Elektrode (461) elektrisch mit einer ersten Spannung (VDD) verbunden ist;

einen die erste Elektrode (426) und eine zweite Elektrode (445) umfassenden zweiten Kondensator (Cst);

gekennzeichnet durch

einen ersten Schalter (M4), der die ersten und vierten Elektroden (426, 461) miteinander verbindet, wobei der erste Schalter (M4), wenn eingeschaltet, dazu ausgelegt ist, die ersten und vierten Elektrode (426, 461) äquipotential zu verbinden und dadurch die erste Spannung (VDD) mit der ersten Elektrode (426) zu verbinden; und einen zweiten Schalter (M5), der die erste Elektrode (426) und eine fünfte Elektrode miteinander verbindet, wobei die fünfte Elektrode elektrisch mit einer zweiten Spannung (V_data) verbunden ist, wobei der zweite Schalter (M5), wenn eingeschaltet, dazu ausgelegt ist, die erste Elektrode (426) und die fünfte Elektrode äquipotential zu verbinden und dadurch die zweite Spannung (V_data) mit der ersten Elektrode (426) zu verbinden.

6. Der Anzeigeansteuerschaltkreis nach Anspruch 5, wobei die erste Elektrode (426) eine Polysiliziumschicht umfasst.

7. Der Anzeigeansteuerschaltkreis nach Anspruch 5, wobei der erste Kondensator (Cvth) ferner eine dritte Elektrode (447) umfasst, die elektrisch von den ersten und vierten Elektroden (426, 462) isoliert ist, wobei die ersten und dritten Elektroden (426, 447) einen ersten Unterkondensator (Cvth1) umfassen und wobei die vierten und dritten Elektroden (461, 447) einen zweiten Unterkondensator (Cvth2) umfassen.

8. Der Anzeigeansteuerschaltkreis nach Anspruch 5, wobei der zweite Kondensator (Cst) dazu ausgelegt ist, mit einer Spannung geladen zu werden, die eine Differenz zwischen der ersten Spannung (VDD) und der zweiten Spannung (V_data) ist, während der zweite Schalter (M5) eingeschaltet ist.

9. Eine Anzeigevorrichtung, die ein Feld einer Vielzahl von Anzeigeeinheiten (110) umfasst, wobei mindestens eine der Anzeigeeinheiten (110) umfasst:

eine erste leitende Schicht (426);

eine vierte leitende Schicht (461) über der ersten leitenden Schicht (426);

eine zwischen den ersten und vierten leitenden Schichten (426, 461) angeordnete dritte leitende Schicht (447), wobei die dritte leitende Schicht (447) von den ersten und vierten leitenden Schichten (426, 461) elektrisch isoliert ist; und

eine über der ersten leitenden Schicht (426) angeordnete zweite leitende Schicht (445), wobei die zweite leitende Schicht (445) im Wesentlichen äquipotential mit der dritten leitenden Schicht (447) ist,

dadurch gekennzeichnet, dass

die Anzeige ferner einen Schaltkreis umfasst, der die ersten und vierten leitenden Schichten (426, 461) miteinander verbindet, wobei der Schaltkreis derart konfiguriert ist, dass er ein erstes Steuersignal und ein zweites Steuersignal empfängt, wobei, wenn das erste Steuersignal empfangen wird, der Schaltkreis derart konfiguriert ist, dass er die ersten und vierten leitenden Schichten (426, 461) im Wesentlichen äquipotential verbindet und wobei, wenn das zweite Steuersignal empfangen wird, der Schaltkreis derart konfiguriert ist, dass er einen Spannungsabfall aufweist.

10. Die Anzeigevorrichtung nach Anspruch 9, wobei die erste leitende Schicht (426) eine mit Fremdatomen dotierte Polysiliziumschicht umfasst.

11. Die Anzeigevorrichtung nach Anspruch 9, wobei mindestens eine der zweiten und dritten leitenden Schichten (445, 447) eine Metallelektrodenschicht umfasst.

12. Die Anzeigevorrichtung nach Anspruch 9, wobei der Schaltkreis einen Transistor (M4) umfasst, der ein Gate, eine Source und einen Drain umfasst, wobei das Gate derart konfiguriert ist, dass es die ersten und zweiten Steuersignale empfängt, wobei die Source elektrisch mit der vierten leitenden Schicht (461) verbunden ist und wobei das Drain elektrisch mit der ersten leitenden Schicht (426) verbunden ist und/oder wobei, wenn das zweite Steuersignal empfangen wird, die erste leitende Schicht (426) elektrisch mit einer von der vierten leitenden Schicht (426) verschiedenen Elektrode verbunden ist.

13. Die Anzeigevorrichtung nach Anspruch 9, wobei die ersten und dritten leitenden Schichten (426, 447) einen Kondensator umfassen und/oder wobei die dritten und vierten leitenden Schichten (447, 461) einen Kondensator umfassen und/oder wobei erste und zweite leitende Schichten (426, 445) einen Kondensator umfassen.

Revendications

1. Circuit de condensateur destiné à être utilisé dans un circuit de commande d'affichage, le condensateur comprenant :

une première couche conductrice (426) formée dans un corps unique ;

une première couche isolante (430) formée sur la première couche conductrice (426) ;

une deuxième couche conductrice (445) et une troisième couche conductrice (447) formées séparément sur la première couche isolante (430) ;

une deuxième couche isolante (450) formée sur la deuxième couche conductrice (445) et la troisième couche conductrice (447), et

une quatrième couche conductrice (461) formée sur la deuxième couche isolante (450) et électriquement connectée à la deuxième couche conductrice (445),

caractérisé en ce que la première couche conductrice (426) est électriquement connectée à la quatrième couche conductrice (461) par l'intermédiaire d'un premier commutateur (M4) apte à être rendu passant pendant une première période et en ce qu'un deuxième potentiel (V_Data) est appliqué à la première couche conductrice (426) par l'intermédiaire d'un deuxième commutateur (M5) apte à être rendu passant pendant une deuxième période.

2. Condensateur selon la revendication 1, dans lequel la quatrième couche conductrice (461) est recouverte d'au moins une partie de la troisième couche conductrice (447).

3. Condensateur selon la revendication 1, dans lequel la première couche conductrice (426) est une couche de polysilicium dopée par une ou plusieurs impuretés ; la deuxième couche conductrice (445) et la troisième couche conductrice (447) constituent une première couche métallique, et la quatrième couche conductrice (461) est une deuxième couche métallique formée sur la deuxième couche isolante (450) et électriquement connectée à la deuxième couche conductrice (445).

4. Circuit de condensateur selon la revendication 1, dans lequel la première couche conductrice (426) et la deuxième couche conductrice (445) comprennent un condensateur et/ou dans lequel la deuxième couche conductrice (445) et la quatrième couche conductrice (461) comprennent un condensateur et/ou dans lequel la première couche conductrice (426) et la troisième couche conductrice (447) comprennent un condensateur et/ou dans lequel la troisième conductrice (447) est située à un niveau se trouvant entre les première et quatrième couches conductrices (426, 461) et/ou dans lequel la troisième couche conductrice (447) est située sensiblement au même niveau que la deuxième couche conductrice (445).

5. Circuit d'attaque d'affichage comprenant :

un premier condensateur (Cvth) comprenant une première électrode (426) et une quatrième électrode (461), la quatrième électrode (461) étant électriquement connectée à une première tension (VDD) ;

un deuxième condensateur (Cst) comprenant la première électrode (426) et une deuxième électrode (445) ;

caractérisé par un premier commutateur (M4) interconnectant les première et quatrième électrodes (426, 461), dans lequel, lorsqu'il est rendu passant, le premier commutateur (M4) est configuré pour connecter de façon équipotentielle les première et quatrième électrodes (426, 461), connectant ainsi la première tension (VDD) à la première électrode (426) ; et un deuxième commutateur (M5) interconnectant la première électrode (426) à une cinquième électrode, la cinquième électrode étant électriquement connectée à une deuxième tension (V_data), dans lequel, lorsqu'il est rendu passant, le deuxième commutateur (M5) est configuré pour connecter de façon équipotentielle la première électrode (426) à la cinquième électrode, connectant ainsi la deuxième tension (V_data) à la première électrode (426).

6. Circuit d'attaque d'affichage selon la revendication 5, dans lequel la première électrode (426) comprend une couche de polysilicium.

7. Circuit d'attaque d'affichage selon la revendication 5, dans lequel le premier condensateur (Cvth) comprend en outre une troisième électrode (447) électriquement isolée à la fois des première et quatrième électrodes (426, 461), dans lequel les première et troisième électrodes (426, 447) comprennent un premier sous-condensateur (Cvth1), et dans lequel les quatrième et troisième électrodes (461, 447) comprennent un deuxième sous-condensateur (Cvth2).

8. Circuit d'attaque d'affichage selon la revendication 5, dans lequel le deuxième condensateur (Cst) est configuré pour être chargé avec une tension qui est une différence entre la première tension (VDD) et la deuxième tension (V_data) pendant que le deuxième commutateur (M5) est rendu passant.

9. Dispositif d'affichage comprenant une matrice constituée d'une pluralité d'unités d'affichage (110), au moins l'une des unités d'affichage (110) comprenant :

une première couche conductrice (426) ;

une quatrième couche conductrice (461) sur la première couche conductrice (426) ;

une troisième couche conductrice (447) située entre les première et quatrième couches conductrices (426, 461), la troisième couche conductrice (447) étant électriquement isolée à la fois des première et quatrième couches conductrices (426, 461) ; et

une deuxième couche conductrice (445) située sur la première couche conductrice (426), la deuxième couche conductrice (445) étant sensiblement à un niveau équipotentiel par rapport à la troisième couche conductrice (447),

caractérisé en ce que l'affichage comprend en outre un circuit interconnectant les première et quatrième couches conductrices (426, 461), dans lequel le circuit est configuré pour recevoir un premier signal de commande et un deuxième signal de commande, dans lequel lorsque le premier signal de commande est reçu, le circuit est configuré pour connecter de façon sensiblement équipotentielle les première et quatrième couches conductrices (426, 461), et dans lequel, lorsque le deuxième signal de commande est reçu, le circuit est configuré pour qu'il se produise dans celui-ci une chute de tension.

10. Dispositif d'affichage selon la revendication 9, dans lequel la première couche conductrice (426) comprend une couche de polysilicium dopée par une impureté.

11. Dispositif d'affichage selon la revendication 9, dans lequel au moins l'une des deuxième et troisième couches conductrices (445, 447) comprend une couche d'électrode métallique.

12. Dispositif d'affichage selon la revendication 9, dans lequel le circuit comprend un transistor (M4) comprenant une grille, une source et un drain, dans lequel la grille est configurée pour recevoir les premier et deuxième signaux de commande, dans lequel la source est électriquement connectée à la quatrième couche conductrice (461), et dans lequel le drain est électriquement connecté à la première couche conductrice (426) et/ou dans lequel, lorsque le deuxième signal de commande est reçu, la première couche conductrice (426) est électriquement connectée à une électrode autre que la quatrième couche conductrice (426).

13. Dispositif d'affichage selon la revendication 9, dans lequel les première et troisième couches conductrices (426, 447) comprennent un condensateur et/ou dans lequel les troisième et quatrième couches conductrices (447, 461) comprennent un condensateur et/ou dans lequel les première et deuxième couches conductrices (426, 445) comprennent un condensateur.

Drawing