[0001] The present invention relates to the technical sector of switched capacitance circuits.
More particularly, the present invention concerns a switched capacitance circuit and
an analog/digital converter comprising said circuit.
[0003] As is well known, switched capacitance circuits utilize switches, typically MOS (Metal
Oxide Semiconductor) transistors, capacitors and operational amplifiers to perform
some analog functions that are normally realized by means of resistances, capacitors
and operational amplifiers.
[0004] Switched capacitance circuit techniques, developed principally for the purpose of
rendering possible the simultaneous integration of analog and digital functions in
the same integrated circuit, found their most extensive application in the realization
of filters and in the realization of circuits for sampling signals and/or converting
data.
[0005] In particular, applications relating to signal sampling and data conversion make
extensive use of switched capacitance circuits that include a switched capacitance
section for sampling (i.e. charging onto the capacitances) an input signal and producing
a sampled signal on an output terminal and a second section that includes an operational
stage, a comparator stage for example, provided with an input terminal connected to
the output terminal of the switched capacitance section for receiving the signal that
the section has sampled.
[0006] Known applications of this type are the switched capacitance analog/digital converters
like those that, for example, function in accordance with SAR (Successive Approximation
Register) technique, sometimes also referred to by the expression "charge redistribution
converters".
[0007] Figure 1 illustrates the simplified schematic layout of a portion of a differential
analog/digital converter of the SAR type forming part of the prior art.
[0008] The shown converter portion includes switched capacitance section SC capable of receiving
a differential input signal V
INP, V
INM comprising a first V
INP and a second V
INM signal component. The switched capacitance section SC is also such as to receive
a reference signal V
REFP, V
REFM that is likewise differential.
[0009] The switched capacitance section SC includes a first array AR of capacitors Ca, Cb,
Cc having a first terminal connected to a first common node NS and a second terminal
connected to a respective switch Swa, Swb, Swc.
[0010] The switched capacitance section SC further includes a second array AR' of capacitors
Ca', Cb', Cc' having a first terminal connected to a second common node NS' and a
second terminal connected to a respective switch Swa', Swb', Swc'.
[0011] Furthermore, the converter portion shown in the figure is also provided with an operational
stage, in particular a voltage comparator CMP that, by means of the switches Sw1 and
Sw1', can be closed-loop reset.
[0012] For the sake of simplicity, the substantially logical part of the analog/digital
converter provided for controlling the various switches and functioning in accordance
with SAR-type conversion technique has not been shown in Figure 1.
[0013] A delicate phase in the conversion of the analog input signal V
INP, V
INM into a digital signal is (represented by) the sampling phase of that signal. During
this phase the first capacitor array AR has the task of sampling the first component
V
INP of the differential input signal, while the capacitor array AR' has the task of sampling
the second component V
INM of the differential input signal.
[0014] In accordance with the layout of Figure 1, prior art is well familiar with and makes
extensive use of a technique intended to closed-loop reset the comparator CMP by means
of switches Sw1, Sw1' (during the sampling phase) in order to force the nodes NS,
NS' to a low impedance at a respective voltage value optimal for the operation of
the comparator CMP.
[0015] For example, a switched capacitance circuit including a closed-loop resettable comparator
during the sampling phase of the input signal of a type similar to the one cited above
is described in greater detail in the European Patent Application published under
the number
EP 1039642.
[0016] It has been observed that the duration of the transient necessary for charging the
capacitances of the switched capacitance section SC becomes particularly critical
in applications that call for a high conversion frequency. The duration of this transient
is significantly influenced by the impedance seen at the summation nodes NS, NS' during
the sampling phase. In fact, this impedance, together with the values of the capacitances
of the switched capacitance section SC, influences the time constant of the charging
transient in a decisive manner. When the duration of this transient has to be reduced,
it is typically not possible to act on the capacitances of the switched capacitance
section because, as is well known to persons skilled in the art, the values of these
capacitances are predetermined, since they are essentially imposed by the resolution
of the converter.
[0017] With a view to increasing the speed at which the input voltage can be charged onto
the capacitors of a switched capacitance circuit that includes a closed loop resettable
comparator of the type described above, a possible solution would be constituted by
redesigning the comparator CMP in such a manner as to increase the current that the
comparator is capable of providing to the summation nodes NS, NS' (for charging the
capacitors of the switched capacitance section SC).
[0018] It has been observed that this solution is associated with some drawbacks. In particular,
the power consumption of the comparator CMP becomes significantly greater when this
current is increased. This is due to the fact that all the generators within the comparator
have to provide a greater current for the purpose of continuing to assure the biasing
and frequency response performances necessary for settling the comparator.
[0019] Furthermore, maintenance of the biasing performances (which include maintenance of
the common mode voltage of the comparator at the value that makes it possible to optimize
the comparator performances) calls for an increase of the aspect ratio W/L of the
MOS transistors within the comparator CMP and this determines a considerable increase
of the area occupied by the comparator.
[0020] Though here described with particular reference to an analog/digital converter, these
problems are nevertheless quite generally associated with circuits that provide switched
capacitances upstream of a converter stage or, more generally, an operational stage.
[0021] It is therefore
an object of the present invention to provide a circuit that will make it possible to
obviate the drawbacks and problems of the known technique described above and, more
particularly, realize a switched capacitance circuit in which the best performances
in terms of input signal sampling speed do not imply an excessive increase of the
power consumption and/or a significant increment of the area occupied by the circuit.
[0022] This object is attained by means of a switched capacitance circuit as described in
the first claim attached hereto. Preferred embodiments of the switched capacitance
circuit in accordance with the invention are defined by the dependent Claims 2-11.
[0023] A further object of the present invention is constituted also by an analog/digital
converter as described in Claims 12 and 13 hereinbelow.
[0024] Further characteristics and advantages of the invention will be more readily understood
from the following detailed description of a preferred embodiment thereof, which is
given by way of example and is therefore not to be understood as being limitative
in any way, the description making reference to the attached drawings, of which:
- Figure 1 shows the schematic layout of a portion of an analog/digital converter of
the known type;
- Figure 2 shows the simplified schematic layout of a switched capacitance circuit in
accordance with the present invention; and
- Figure 3 shows a portion of the schematic circuit layout of Figure 2 in greater detail.
[0025] Figure 2 shows a simplified schematic circuit layout of a particularly preferred
embodiment of a switched capacitance circuit 2 in accordance with the present invention.
The switched capacitance circuit 2 includes a switched capacitance section SC, an
operational stage CMP, and a control section CNTRL. In this example the operational
stage CMP is a voltage comparator comprising a non-inverting input IN, an inverting
input terminal IN' and an output terminal T_OUT.
[0026] In the example of Figure 2, the switched capacitance circuit 2 is a three-bit analog/digital
converter capable of converting an analog differential input signal V
INP, V
INM into a series of three-bit digital samples out_CODE of that signal. The teachings
of the present invention may however be extended without difficulty to analog/digital
converters having a greater resolution, for example, ten-bit converters.
[0027] Preferably, the analog/digital converter will be a converter of the SAR type and
of the "fully differential" type and the analog input signal V
INP, V
INM will be a differential voltage that includes a first component V
INP and a second component V
INM
[0028] Nevertheless, the consideration set out in the present description can be extended
without difficulty to switched capacitance circuits of a different type, for example,
also analog/digital converters that utilize techniques other than the SAR technique
or, like the converter described in the aforementioned
European Patent EP 1039642 have a "pseudo-differential" structure.
[0029] In the example of Figure 2, the switched capacitance section SC is such as to be
capable of receiving the differential input voltage V
INP, V
INM and a differential reference voltage V
REFP, V
REFM comprising two components, respectively V
REFP, V
REFM.
[0030] The switched capacitance section includes a first group (or array) AR of capacitors
Ca, Cb, Cc and, preferably, a second group (or array) AR' of capacitors Ca', Cb',
Cc'. The switched capacitance section SC is also provided with a respective group
(or array) of switches, respectively Swa, Swb, Swc and Swa', Swb', Swc' for each group
of capacitors.
[0031] The capacitors Ca, Cb, Cc of the first array AR are respectively provided with a
first terminal connected to a first common node NS, or first summation node. The summation
node NS is connected to the non-inverting input terminal IN of the comparator CMP.
The capacitors Ca, Cb, Cc of the first array AR are respectively provided with a second
terminal connected to a respective switch Swa, Swb, Swc.
[0032] Similarly, the capacitors Ca', Cb', Cc' of the second array AR' are respectively
provided with a first terminal connected to a second common node NS', or second summation
node. This node is connected to the inverting input terminal IN' of the comparator
CMP. The capacitors Ca', Cb', Cc' of the second array AR' are respectively provided
with a second terminal connected to a respective switch Swa', Swb', Swc'.
[0033] Two further switches Sw1 and Sw1' are provided for closed-loop resetting the comparator
CMP, when the differential voltage V
INP, V
INM is charged onto the capacitors of the two arrays AR, AR', i.e. during the sampling
phase of the differential input voltage V
INP, V
INM. This makes it possible to force the two summation nodes NS, NS' to a low impedance
at a common mode voltage V
CM, V
CM' that depends on the structure of the comparator CMP and the operating conditions
and, preferably, optimal for the biasing and the functioning of the comparator CMP.
[0034] It should be noted that in practice the switches indicated in the circuit of Figure
2 comprise electrically controllable electronic connection/disconnection devices,
for example, MOS transistors or combinations of MOS transistors.
[0035] The comparator CMP is such as to provide at its output terminal T_OUT a digital comparison
signal out_CMP that assumes either a first or a second value on the basis of the result
of the comparison between the signals present, respectively, at the non-inverting
input IN and the inverting input IN'.
[0036] The control section CNTRL is provided with an input for receiving the digital comparison
signal out_CMP and further includes an input for receiving a timing signal clk.
[0037] The control section CNTRL includes a logic control unit LU, a register REG and a
register reading unit RU.
[0038] In greater detail, the logic control unit LU is such as to receive the digital comparison
signal out_CMP and to output signals capable of controlling the switches Swa, Swb,
Swc and Swa', Swb', Swc' of the two arrays and also the switches Sw1 and Sw1' of the
comparator CMP. The control of these switches is effected in a accordance with a predetermined
algorithm, in this particular example of the "successive approximation" type, i.e.
of the SAR type.
[0039] Advantageously, the logic section LU will also be such as to output an enabling signal
PRECH to enable/disable an auxiliary circuit that will subsequently be described in
greater detail. Preferably, the signal PRECH will be a digital signal that can assume
a first level such as to enable the auxiliary circuit, for example a "high" logic
level, and a second level such as to disable the auxiliary circuit, for example a
"low" logic level.
[0040] The logic control unit LU is connected to the register REG that makes it possible
to memorize the positions of the switches of the switched capacitance section SC.
[0041] The register reading unit RU outputs a digital signal out_CODE that corresponds to
a digitalized version of the analog signal that is to be converted.
[0042] The switched capacitance circuit 2 shown in Figure 2 corresponds to a configuration
of the circuit during the time interval reserved for sampling the differential input
signal V
INP, V
INM. Figure 2 in practice therefore represents the configuration assumed by the circuit
2 during a sampling time interval T
SAMPLE. During this interval the first component V
INP will be applied to all the capacitors of the first array AR and the second component
V
INM will be applied to all the capacitors of the second array AR'.
[0043] It should be noted that in a differential analog/digital converter like the one shown
in Figure 2 the switches connected to corresponding capacitors corresponding of two
arrays AR, AR' are controlled simultaneously and in such a manner that different components
of the input and reference voltages are applied to the corresponding capacitors of
the two arrays. For example, if the first component V
INP of the differential input voltage is applied to the capacitor Ca, the second component
V
INM of the differential input voltage will be applied to the capacitor Ca'.
[0044] In the configuration of Figure 2, the switches Sw1 and Sw1' are in a position such
as to provide a closed loop reset of the comparator CMP.
[0045] Figure 3 shows a portion of the circuit of Figure 2 in greater detail. More precisely,
what is principally represented in Figure 3 is the portion of the circuit that in
Figure 2 is comprised within the brokenline rectangle indicated by Q1. In practice,
therefore, Figure 3 shows in greater detail the schematic circuit layout of the comparator
CMP of Figure 2, inclusive of the part for providing a closed-loop reset of the comparator
CMP. For the sake of simplicity, on the other hand, Figure 3 shows less detail of
the switched capacitance section SC, which in Figure 3 is represented in the form
of the block SC, and, again for the sake of simplicity, the control CNTRL is omitted.
Equal or similar elements in Figures 2 and 3 are indicated by the same reference numbers.
[0046] In accordance with what is shown in Figure 3, the comparator CMP will preferably,
but not limitatively, be a multistage comparator including: a "folded cascode" operational
differential input stage FC_1, an intermediate folded cascode operational stage that
is connected in cascade with the operational input stage FC_1.
[0047] Furthermore, the comparator CMP will preferably include a third stage FC_OUT that
makes it possible to convert the differential output of the intermediate stage FC_2
into a binary digital signal out_CMP. In the example of Figure 3, the three operational
stages FC_1, FC_2 and FC_0 are DC decoupled from each other by means of decoupling
capacitances CD, CD' and CD1, CD1'.
[0048] The folded cascade stages FC_1, FC_2 are known to persons skilled in the art of the
sector even in numerous realization variants and will not therefore be here described
in greater detail.
[0049] Each of the stages FC_1, FC_2 is provided with biasing current generators I
1, I
2, I
3 and MOS load transistors ML1, ML2. The MOS load transistors ML1, ML2 are connected
in a diode configuration and, more particularly, each one of these transistors is
provided with a control terminal connected to a first conduction terminal and is provided
with a second conduction terminal connected to ground.
[0050] In the circuit shown in Figure 3, each of the differential stages FC_1, FC_2 is provided
with two switches, respectively, SW1, SW1' and SW2, SW2'. In practice the switches
SW1 and SW1' of Figure 3 coincide with the switches indicated in Figure 2 by means
of the same reference symbols.
[0051] The configuration shown in Figure 3 represents the various stages of the comparator
CMP in the closed-loop reset configuration. Given the closed state of the switches
SW1, SW1' and SW2, SW2', each of the differential stages FC_1, FC_2 therefore has
its input terminals, which are respectively non-inverting and inverting, short-circuited
to its output terminals, which are respectively inverting and non-inverting. In the
example of Figure 3, more particularly, the first operational stage FC_1 includes
two input terminals IN and IN' (in this example coincident with the input terminals
of the comparator CMP) and two output terminals Out1 and Out1'. When in the closed-loop
reset configuration as shown in Figure 3, each of the input terminals IN, IN' is short-circuited
to a respective output terminal Out1, Out1' through the switches SW1 and SW1'.
[0052] Similarly, the second operational stage F2 of the comparator CMP includes two input
terminals IN2 and IN2' and two output terminals Out2 and Out2'. When in the closed-loop
reset configuration as shown in Figure 3, each of the input terminals IN2, IN2' is
short-circuited to a respective output terminal Out2, Out2' through the switches SW2
and SW2'. It should be noted that the nodes NS and NS' could be forced to a low impedance
by doing no more than closed loop resetting the first stage FC_1 of the comparator
CMP. Nevertheless, it is advisable to reset also the second stage FC_2 of the comparator
CMP, because this will make it possible to cause the inputs IN, IN' of the comparator
CMP to memorize the offset of the comparator. In practice, therefore, one could make
provision for the signals supplied by the control section CNTRL to control the switches
Sw1, Sw1' to simultaneously control also the switches Sw2, Sw2'.
[0053] As can be seen in Figure 3, the switched capacitance circuit further includes - and
advantageously so - an auxiliary circuit ANC connected either directly or indirectly
to each common node NS, NS' of the switched capacitance section SC. Preferably, the
auxiliary circuit ANC will include, associated with each common node NS, NS' of the
switched capacitance section SC, an auxiliary stage A, A' that is either directly
or indirectly connected with it.
[0054] In the example of Figure 3, which corresponds to a particularly preferred embodiment,
each of the auxiliary stages A, A' includes an output terminal Y, Y' that can be connected
through the switch Sw1, Sw1' to the respective common node NS, NS' of the switched
capacitance section SC.
[0055] In greater detail, the output terminals Y, Y' of the auxiliary stages A, A' are connected
to a respective output terminal Out1, Out1' of the first operational stage FC_1 of
the comparator CMP, so that they will be directly connected to the respective common
nodes NS, NS' of the switched capacitance section SC when the comparator CMP is in
the closed-loop reset configuration. This particularly preferred embodiment has the
advantage of leaving the summation nodes NS, NS' associated only with the diffusions
of the switches Sw1, Sw1' when the switches Sw1, Sw1' are in the open state.
[0056] Advantageously, each auxiliary stage A, A' will be such as to supply to the common
node NS, NS' associated with it a current useful for charging the array of capacitances
AR, AR' connected to said common node NS, NS'.
[0057] In the particular example described with reference to Figures 2 and 3, the auxiliary
circuit ANC has been represented, though not limitatively, as included in the comparator
CMP. Alternatively, the auxiliary circuit ANC may be indifferently realized as being
either partially included in the comparator CMP or even external to it.
[0058] In a particularly preferred embodiment, each of the auxiliary stages A, A' can be
activated/deactivated by the enabling signal PRECH to inject into the common node
NS, NS' associated with it a current capable of increasing the current supplied to
said node NS, NS' during the sampling interval of differential input signal V
INP, V
INM, this for the purpose of obtaining a more rapid charging of the capacitor arrays
AR, AR'.
[0059] In a particularly preferred embodiment, the enabling signal PRECH is such as to enable
the auxiliary stages A, A' for the entire duration of the time interval equal to a
predetermined fraction of the sampling interval T
SAMPLE. More preferably, said predetermined fraction will include an initial portion of
the sampling interval T
SAMPLE.
[0060] In the particular example described with reference to Figure 3, each of the auxiliary
stages A, A' will include a respective current generator I
4, I
4' connected in series by means of at least a first electronic switch M1, M1' to a load
element M4, M4'.
[0061] In a particular preferred embodiment, the current generator I
4, I
4' of each auxiliary stage A, A' will be connected in series with a first conduction
terminal d1, d1' of the first electronic switch M1, M1'.
[0062] The first electronic switch M1, M1' further includes a control terminal g1, g1' for
being controlled by means of a control signal
PRECH. More preferably, the first electronic switch M1, M1' will include a transistor of
the P-MOS type and the control signal
PRECH is the negated signal of the enabling signal PRECH.
[0063] Preferably, each auxiliary stage A, A' will include a second electronic switch M2,
M2' connected in series between the first electronic switch M1, M1' and the load element
M4, M4'. In a particularly preferred embodiment, the second electronic switch M2,
M2' will be a transistor of the N-MOS type controllable by means of the enabling signal
PRECH.
[0064] Preferably, the load element M4, M4' will include a load transistor M4, M4' of the
N-MOS type that can be controlled by means of a third electronic switch M3, M3' included
in each auxiliary stage A, A' and which, in the preferred embodiment of Figure 3,
is a transistor of the N-MOS type having a first conduction terminal s3, s3' connected
to a control terminal g4, g4' of the load transistor M4, M4' and a second conduction
terminal d3, d3' connected to a common node Y, Y' (in this particular example coincident
with the output terminal Y, Y' of the auxiliary stage A, A') to a conduction terminal
d2, d2' of the transistor M2, M2' and to conduction terminal s1, s1' of the transistor
M1, M1'.
[0065] Preferably, the transistor M3, M3' will include a control terminal g3, g3' for being
controlled by the enabling signal PRECH.
[0066] In a particularly advantageous embodiment, the auxiliary circuit ANC is dimensioned
in such a manner that:
- the MOS load transistors M4, M4' of the auxiliary stages A, A' are a replica of, respectively,
the load diodes ML2, ML1 of the comparator CMP and are characterized by having an
aspect ratio W/L that is N times greater than that of the diodes (where N is a real
number greater than 1);
- the current generators I4, I4' of the auxiliary circuits A, A' are dimensioned in
such a manner as to generate a current that has an intensity equal to N times the
intensity of the current IL that is supplied by the comparator CMP and flows in the load diodes ML1, ML2 of the
comparator CMP in the absence of the auxiliary circuit ANC (or whenever this circuit
is disabled) and in closed-loop rest configuration of the comparator CMP.
[0067] Since in the circuit of Figure 3 this current I
L is given by:

we shall therefore have:

[0068] The particular dimensioning that has just been described makes it possible, when
the auxiliary circuit is enabled by the signal PRECH, for the common nodes NS and
NS' to be advantageously forced to a voltage V
A, V
A' having a value approximately equal to the common mode voltage V
CM, V
CM' to which the nodes NS, NS' of the comparator CMP would be forced if the auxiliary
circuit ANC were disabled or lacking.
[0069] There will now be described the operation of the switched capacitance circuit 2,
which - as already explained - in the particular example illustrated in Figures 2
and 3 constitutes an analog/digital converter of the SAR type, i.e. a successive approximations
converter.
[0070] For the sake of simplicity, from this description there will be omitted the description
of the detailed functioning of the analog/digital converter during the various attempts
(i.e. the successive approximation steps), because this forms part of the prior art
and is therefore well known to a person skilled in the art.
[0071] On the other hand, the description will dwell in a more detailed manner on the functioning
of the converter of Figures 2 and 3 during the phases of closed-loop resetting of
the converter CMP and sampling the differential input voltage, which are propaedeutic
for the subsequent conversion of this voltage into a digital code OUT_CODE.
[0072] In particular, it is proposed to explain the operation of the converter within the
limits of a single sampling interval T
SAMPLE of the differential input voltage.
[0073] When the differential input voltage is to be sampled, the control section CNTRL and,
more particularly, the logic unit LU carry out the following operations:
- generating control signals for the switches Swa, Swb Swc associated with the first
array AR of capacitors Ca, Cb, Cc to bring said switches Swa, Swb, Swc into a configuration
such as to connect the corresponding capacitors to the first component VINP of the differential input voltage;
- generating control signals for the switches Swa', Swb' Swc' associated with the second
array AR' of capacitors Ca', Cb', Cc' to bring said switches Swa', Swb', Swc' into
a configuration such as to connect the corresponding capacitors to the second component
VINM of the differential input voltage;
- generating control signals for the switches Sw1, Sw1' of the comparator CMP for the
purpose of closed loop resetting the comparator CMP;
- generating an enabling signal PRECH having a level such as to enable the auxiliary
circuit ANC (in the particular example here described, the signal PRECH will assume
a "high" logic level such as to bring the MOS transistors M2, M3 and M2', M3' into
conduction and its negated signal will assume a "low" logic level such as to bring
the MOS transistors M1 and M1' into conduction).
[0074] In a particularly preferred embodiment, all the aforesaid operations are carried
out in such a manner as to be substantially simultaneous with each other and synchronized
with the beginning of the sampling interval T
SAMPLE.
[0075] Following the enabling effected by means of the signal PRECH, the first auxiliary
stage A will force the common node NS to a voltage V
A and the second auxiliary stage A' will force the common node NS' to a voltage V
A'. The value of the voltages V
A and V
A' is determined, respectively, by the voltage drop across the load transistors M4
and M4' produced by the currents 14 and I4'.
[0076] Each of the capacitors of the first array AR will therefore be affected by a charging
transient such as to establish a voltage difference V
INP-V
A between its plates. Similarly, each of the capacitors of the second array AR' will
be affected by a charging transient such as to establish a voltage difference V
INM-V
A' between its plates.
[0077] Advantageously, during the charging transient of the capacitors the auxiliary circuit
enabled by the signal PRECH will supply to the common nodes NS, NS' a current about
N times greater than the current that the comparator CMP would provide for them if
the auxiliary circuit ANC were lacking (or in a state of disabilitatation). Consequently,
the fact that the enabling of the auxiliary circuit ANC supplies a greater current
to the common nodes NS, NS' makes it possible, and advantageously so, to reduce the
duration of the charging transient of the capacitors of the switched capacitance section
SC.
[0078] The reduction of the transient duration can also be explained in a manner that is
alternative but equivalent to the one given above by reasoning in terms of the impedance
of the common nodes NS, NS' rather than in terms of current.
[0079] Indeed, when the auxiliary circuit ANC is enabled and the comparator CMP is in the
closed-loop reset configuration, the impedance at the nodes NS and NS' is reduced
by a factor N as compared with the impedance to which these nodes can be forced by
means of the mere closed loop resetting of the comparator CMP (that is to say, in
a condition in which the auxiliary circuit is either disabled or lacking). This is
due to the fact that the load transistors M4 and M4' of the auxiliary circuit ANC
in the preferred embodiment of Figure 3 have, respectively, an aspect ratio W/L that
is about N times greater than the aspect ratio of the load diodes ML2 and ML1 of the
comparator CMP.
[0080] It should be noted that a reduction of the impedance of the common nodes NS' NS'
implies a corresponding and almost linear reduction of the time constant of the charging
transient of the capacitors included in the switched capacitance section SC.
[0081] It should also be noted that the increase of the current supplied to the summation
nodes NS, NS' (or, similarly, the reduction of the impedance existing at the summation
nodes NS, NS') is obtained by maintaining the voltage of the summation nodes NS, NS'
approximately unchanged.
[0082] Coming back to the description of the functioning of the circuit of Figure 3, the
control section CNTRL in a particularly preferred embodiment, following the lapse
of a predetermined interval (preferably having the value of an integral multiple of
cycles of the clock signal clk) starting at the instant when the auxiliary circuit
ANC becomes enabled, disables this circuit by means of the signal PRECH, thus leaving
the comparator CMP alone in completing the charging of the capacitor arrays AR, AR'
of the switched capacitance section SC during the remaining and final part of the
sampling interval T
SAMPLE.
[0083] Advantageously, the duration of the enabling interval of the auxiliary circuit ANC
will be selected in such a manner that the comparator CMP has at its disposal a residual
fraction of the sampling interval T
SAMPLE sufficiently long to bring the common nodes NS and NS' back from respectively, the
voltages V
A and V
A' (forced by the auxiliary circuit ANC) to their intrinsic common mode voltages V
CM and V
CM'. In fact, this condition represents the best situation for guaranteeing the greatest
accuracy of the subsequent phase of comparing the voltages at the inputs IN and IN'
of the comparator CMP. In fact, it should be observed that, also if the manufacturing
process of the comparator CMP and the auxiliary circuit ANC is a very accurate process,
a certain, albeit minimal, mismatching will be statistically possible between the
design and the effective realization, so that it is therefore probable that the voltages
V
A and V
A' will have values that do not exactly coincide with the common mode voltages V
CM and V
CM' of the comparator CMP.
[0084] Once such necessary residual interval has been estimated statistically and in a conservative
manner, the factor N can be determined as the smallest number capable of assuring
that the first part of the transient (i.e. the one in which the auxiliary circuit
ANC is enabled) will be sufficiently fast to arrive at steady conditions in such a
manner as to assure that the second part of the transient will become correctly exhausted.
[0085] On the basis of what has been described above, it should be noted that the role of
the auxiliary circuit ANC is that of pre-charging the switched capacitance section
SC in such a manner that, following said pre-charging, the remaining part of the charging
can be correctly carried out by the comparator CMP within the sampling interval T
SAMPLE.
[0086] It should be noted that, advantageously, the auxiliary circuit (or pre-charging circuit)
ANC contributes to the power consumption of the converter only for a very limited
period of time and, consequently, adds only a negligible power consumption because
this additional consumption is averaged over the entire conversion time.
[0087] Advantageously, the addition of the auxiliary circuit ANC causes only a very modest
increase of the area occupied by the circuit. In fact, only the load transistors M4,
M4' have an aspect ratio (W/L) N times greater than the aspect ratio of the load diodes
ML2, ML1 of the comparator and only the two current generators 14 and 14' have an
aspect ratio W/L substantially proportional to N. It is not therefore necessary to
increase the dimensions of all the MOS transistors of the comparator.
[0088] Furthermore, since the comparator CMP has sufficient time in the final part of the
sampling interval to bring the nodes NS and NS' back to their common mode voltage
by its own unassisted action, it is not necessary for the nodes NS and NS' to be forced
during the habilitation of the auxiliary circuit ANC to a voltage exactly equal to
the common mode voltage imposed by the comparator. This implies that the MOS load
transistors M4, M4', which ideally ought to be a replica of the load diodes ML1, ML2,
may also be realized with a certain degree of imprecision, that is to say, a certain
mismatching, and therefore do not call for an excessive area occupation also on account
of the high factors N (which, for example, may be equal to 20).
[0089] Advantageously, the use of switches appropriately positioned in the auxiliary circuit
ANC, for example as shown in Figure 3, renders the influence of said auxiliary circuit
ANC altogether negligible during the normal operation of the converter.
[0090] In fact, it has already been said that, preferably, the MOS load transistors M4 and
M4' of the auxiliary circuit ANC will have an aspect ratio W/L N times greater than,
respectively, the aspect ratios of the load diodes ML2, ML1 of the first stage FC_1
of the comparator CMP. This implies that when the N factors have high values, the
MOS load transistor M4 and M4' of the auxiliary circuit ANC may occupy a non-negligible
area and therefore have high drain and gate capacitances. Advantageously, thanks to
the MOS transistors M2, M2' and M3, M3', the common nodes NS, NS' are prevented from
seeing the drain and gate capacities of the MOS transistors M4 and M4'.
[0091] Advantageously, the opening of the electronic switches comprising the MOS transistors
M1 and M1' also makes it possible to avoid that the current generators 14 and 14'
of the auxiliary circuit ANC keep on charging the common nodes NS, NS' (or, in the
particular example of Figure 3, the outputs Out, Out' of the first operational stage
FC_1) when this is not necessary and also makes it possible to decouple from the common
nodes NS and NS' the drain capacitances of the current generators I4 and I4', which
normally have high values. In fact, it may well be convenient to dimension these generators
with a large area in order to reduce the mirroring error.
[0092] On the basis of what has been explained hereinabove, it is preferable to dimension
the MOS transistors M1, M1', M2, M2' and M3, M3' with an aspect ratio W/L and an area
W*L such that the transistors will prove to be sufficiently conductive when the auxiliary
circuit ANC is enabled, though without thereby increasing in a significant manner
the capacitance associated with the common nodes NS and NS' when the auxiliary circuit
is disabled.
1. A switched capacitance circuit (2) including:
- a switched capacitance section (SC), adapted to be charged, for sampling an input
signal (VINP, VINM), during a sampling phase, said section comprising at least one group (AR, AR') of
capacitors (Ca, Cb, Cc, Ca', Cb', Cc') each of which has a terminal connected to a
common node (NS, NS');
- at least an operational stage (CMP) including at least one input terminal (IN, IN')
connected to said common node (NS, NS'), the operational stage (CMP) being adapted
to provide during the sampling phase a current to said common node (NS, NS') for charging
said group (AR, AR') of capacitors;
- an auxiliary circuit (ANC) connected to said common node (NS, NS') and capable of
being activated/deactivated by an enabling signal (PRECH) for injecting a further
current into said common node (NS, NS') and for increasing the current provided to
said common node (NS, NS') during at least one time interval equal to a fraction of
said sampling phase, said fraction including an initial portion of said sampling phase;
characterized in that
said enabling signal (PRECH) is such as to deactivate said auxiliary circuit (ANC)
before the end of said sampling phase and at the end of said fraction, in order to
leave said operational stage (CMP) alone in completing the charging of said group
of capacitors during a remaining and final part of said sampling phase.
2. A switched capacitance circuit (2) in accordance with Claim 1, wherein, when said
auxiliary circuit is activated, said common node (NS, NS'):
- presents an impedance substantially reduced as compared with the impedance assumed
by said node (NS, NS') when the auxiliary circuit (ANC) is deactivated; and
- is forced to a voltage having a value approximately equal to the voltage to which
said node (NS, NS') is forced when the auxiliary circuit (ANC) is deactivated.
3. A switched capacitance circuit (2) in accordance with Claim 1, wherein said auxiliary
circuit (ANC) includes at least one auxiliary stage (A, A') comprising a current generator
(I4, I4') and a load element (M4, M4') in series with said current generator (14,
14').
4. A switched capacitance circuit (2) in accordance with Claim 3, wherein said auxiliary
circuit (ANC) includes a first electronic switch (M1, M1') connected in series between
said current generator (I4, I4') and said load element (M4, M4'), including a control
terminal (g1, g1') for being controlled by said enabling signal.
5. A switched capacitance circuit (2) in accordance with Claim 4, wherein said auxiliary
circuit (ANC) further includes a second electronic switch (M2, M2') connected in series
between said first switch (M1, M1') and said load element (M4, M4'), including a control
terminal (g2, g2') for being controlled by said enabling signal (PRECH).
6. A switched capacitance circuit (2) in accordance with Claim 1, wherein said operational
stage (CMP) is a voltage comparator that may assume a closed-loop reset configuration,
and wherein said comparator (CMP) is in said closed-loop reset configuration during
the whole duration said sampling phase, said sampling phase being followed by a comparison
phase.
7. A switched capacitance circuit (2) in accordance with Claim 6, wherein said comparator
(CMP) includes at least a first stage (FC_1) including an output terminal (Out, Out')
connected to an output terminal (Y, Y') of said auxiliary circuit (ANC), the auxiliary
circuit (ANC being directly connected to said common node (NS, NS') when the comparator
(CMP) is in said closed-loop reset configuration.
8. A switched capacitance circuit (2) in accordance with Claim 7, wherein:
- said input signal is a differential signal;
- said at least one group of capacitors (Ca, Cb, Cc, Ca', Cb', Cc') includes a first
group of capacitors (Ca, Cb, Cc) having a respective terminal connected to a first
common node (NS) and includes a second group of capacitors (Ca', Cb', Cc') having
a respective terminal connected to a second common node (NS');
- said comparator (CMP) is a differential comparator including a first (IN) and a
second (IN') input terminal connected, respectively, to said first (NS) and said second
(NS') common node;
and wherein said auxiliary circuit includes a first (A) and a second (A') auxiliary
stage connected, respectively, to said first (NS) and said second (NS') common node.
9. A switched capacitance circuit (2) in accordance with Claim 8, wherein said comparator
(CMP) includes a first (ML2) and a second (ML1) load diode, wherein said first (A)
and second (A') auxiliary stage comprise, respectively, a first (M4) and a second
(M4') load element having a respective aspect ratio approximately N times greater
than the one of said first and said second load diode, where N is number greater than
1.
10. A switched capacitance circuit (2) in accordance with Claim 8 or Claim 9, wherein
said comparator (CMP) includes biasing generators for supplying said current to said
first (NS) and second (NS') common node and wherein said first (A) and said second
(A') auxiliary stages include a respective current generator (I4, I4') for supplying to said first (NS) and said second (NS') common node a respective
current N times greater than said current provided by the comparator (CMP), the first
and the second auxiliary stage supplying said respective current to said common nodes
(NS, NS') when said auxiliary circuit is enabled.
11. A switched capacitance circuit (2) in accordance with Claim 7, wherein said fraction
of sampling phase has a duration selected in such a manner that said comparator (CMP)
has at its disposal a residual fraction of said sampling phase sufficiently long to
bring said first and second common nodes (NS, NS') back from voltages (VA, VA') forced by said auxiliary circuits to their intrinsic common mode voltages (VCM, VCM') .
12. An analog/digital converter characterized in that it includes a switched capacitance circuit (2) in accordance with any one of the
previous claims.
13. An analog/digital converter in accordance with Claim 12, further including a control
section (CNTRL) capable of generating signals for controlling said switched capacitance
section (SC) in accordance with a conversion technique of the successive approximation
type (SAR).
1. Schaltkreis (2) mit getakteten Kapazitäten, Folgendes umfassend:
- einen Abschnitt (SC) mit getakteten Kapazitäten, der dazu angepasst ist, geladen
zu werden, um ein Eingangssignal (VINP, VINM) während einer Abtastphase abzutasten, wobei der Abschnitt mindestens eine Gruppe
(AR, AR') von Kondensatoren (Ca, Cb, Cc, Ca', Cb', Cc') umfasst, wovon jeder einen
an einen gemeinsamen Knoten (NS, NS') angeschlossenen Anschluss besitzt;
- mindestens eine Betriebsstufe (CMP), die mindestens einen Eingangsanschluss (IN,
IN') umfasst, die an den gemeinsamen Knoten (NS, NS') angeschlossen ist, wobei die
Betriebsstufe (CMP) dazu angepasst ist, während der Abtastphase dem gemeinsamen Knoten
(NS, NS') einen Strom bereitzustellen, um die Gruppe (AR, AR') von Kondensatoren zu
laden;
- einen Hilfsschaltkreis (ANC), der an den gemeinsamen Knoten (NS, NS') angeschlossen
und in der Lage ist, durch ein Freigabesignal (PRECH) aktiviert/deaktiviert zu werden,
um einen weiteren Strom in den gemeinsamen Knoten (NS, NS') einzuleiten, und um den
dem gemeinsamen Knoten (NS, NS') bereitgestellten Strom während mindestens eines Zeitintervalls
zu erhöhen, das gleich einem Bruchteil der Abtastphase ist, wobei der Bruchteil einen
Anfangsabschnitt der Abtastphase umfasst;
dadurch gekennzeichnet, dass
das Freigabesignal (PRECH) dergestalt ist, dass der Hilfsschaltkreis (ANC) vor dem
Ende der Abtastphase und am Ende des Bruchteils deaktiviert wird, um die Betriebsstufe
(CMP) beim Abschließen des Ladens der Gruppe von Kondensatoren während eines restlichen
und finalen Teils der Abtastphase sich selbst zu überlassen.
2. Schaltkreis (2) mit getakteten Kapazitäten, nach Anspruch 1, wobei, wenn der Hilfsschaltkreis
aktiviert ist, der gemeinsame Knoten (NS, NS'):
- eine I mpedanz aufweist, die im Vergleich zur I mpedanz, die der Knoten (NS, NS')
annimmt, wenn der Hilfsschaltkreis (ANC) deaktiviert ist, wesentlich reduziert ist;
und
- zu einer Spannung mit einem Wert gezwungen wird, die ungefähr gleich der Spannung
ist, zu welcher der Knoten (NS, NS') gezwungen ist, wenn der Hilfsschaltkreis (ANC)
deaktiviert ist.
3. Schaltkreis (2) mit getakteten Kapazitäten, nach Anspruch 1, wobei der Hilfsschaltkreis
(ANC) mindestens eine Hilfsstufe (A, A') umfasst, die einen Stromgenerator (14, 14')
und ein Lastelement (M4, M4') in Reihe mit dem Stromgenerator (14, 14') umfasst.
4. Schaltkreis (2) mit getakteten Kapazitäten, nach Anspruch 3, wobei der Hilfsschaltkreis
(ANC) einen zwischen dem Stromgenerator (14, 14') und dem Lastelement (M4, M4') in
Reihe geschalteten ersten Elektronikschalter (M1, M1') umfasst, der einen Steueranschluss
(g1, g1') umfasst, um durch das Freigabesignal gesteuert zu werden.
5. Schaltkreis (2) mit getakteten Kapazitäten, nach Anspruch 4, wobei der Hilfsschaltkreis
(ANC) darüber hinaus einen zwischen dem ersten Schalter (M1, M1') und dem Lastelement
(M4, M4') in Reihe geschalteten zweiten Elektronikschalter (M2, M2') umfasst, der
einen Steueranschluss (g2, g2') umfasst, um durch das Freigabesignale (PRECH) gesteuert
zu werden.
6. Schaltkreis (2) mit getakteten Kapazitäten, nach Anspruch 1, wobei es sich bei der
Betriebsstufe (CMP) um einen Spannungskomparator handelt, der eine geschlossene Regelkreislaufrücksetzkonfiguration
annehmen kann, und wobei sich der Komparator (CMP) während der gesamten Dauer der
Abtastphase in der geschlossenen Regelkreislaufrücksetzkonfiguration befindet, wobei
auf die Abtastphase eine Vergleichsphase folgt.
7. Schaltkreis (2) mit getakteten Kapazitäten, nach Anspruch 6, wobei der Komparator
(CMP) mindestens eine erste Stufe (FC_1) umfasst, die einen an einen Ausgangsanschluss
(Y, Y') des Hilfsschaltkreises (ANC) angeschlossenen Ausgangsanschluss (Out, Out')
umfasst, wobei der Hilfsschaltkreis (ANC) direkt an den gemeinsamen Knoten (NS, NS')
angeschlossen ist, wenn sich der Komparator (CMP) in der geschlossenen Regelkreislaufrücksetzkonfiguration
befindet.
8. Schaltkreis (2) mit getakteten Kapazitäten, nach Anspruch 7, wobei:
- das Eingangssignal ein Differenzsignal ist;
- die mindestens eine Gruppe von Kondensatoren (Ca, Cb, Cc, Ca', Cb', Cc') eine erste
Gruppe von Kondensatoren (Ca, Cb, Cc) mit einem jeweiligen, an einen ersten gemeinsamen
Knoten (NS) angeschlossenen Anschluss und eine zweite Gruppe von Kondensatoren (Ca',
Cb', Cc') mit einem jeweiligen, an einen zweiten gemeinsamen Knoten (NS') angeschlossenen
Anschluss umfasst;
- wobei der Komparator (CMP) ein Differenzkomparator ist, der einen ersten (IN) und
einen zweiten (IN') Eingangsanschluss umfasst, die an den ersten (NS) bzw. den zweiten
(NS') gemeinsamen Knoten angeschlossen sind;
und wobei der Hilfsschaltkreis eine erste (A) und eine zweite (A') Hilfsstufe umfasst,
die an den ersten (NS) bzw. den zweiten (NS') gemeinsamen Knoten angeschlossen sind.
9. Schaltkreis (2) mit getakteten Kapazitäten, nach Anspruch 8, wobei der Komparator
(CMP) eine erste (ML2) und eine zweite (ML1) Lastdiode umfasst, wobei die erste (A)
und zweite (A') Hilfsstufe ein erstes (M4) bzw. ein zweites (M4') Lastelement mit
einem jeweiligen Seitenverhältnis umfassen, das ungefähr um das N-Fache größer ist
als dasjenige der ersten und zweiten Lastdiode, wobei N eine Zahl größer als 1 ist.
10. Schaltkreis (2) mit getakteten Kapazitäten, nach Anspruch 8 oder Anspruch 9, wobei
der Komparator (CMP) Vorspannungsgeneratoren umfasst, um dem ersten (NS) und zweiten
(NS') gemeinsamen Knoten den Strom zu liefern, und wobei die erste (A) und zweite
(A') Hilfsstufe einen jeweiligen Stromgenerator (I4, I4') umfassen, um dem ersten (NS) und dem zweiten (NS') gemeinsamen Knoten einen jeweiligen
Strom zu liefern, der um das N-Fache höher ist als der durch den Komparator (CMP)
bereitgestellte Strom, wobei die erste und die zweite Hilfsstufe den gemeinsamen Knoten
(NS, NS') den jeweiligen Strom liefern, wenn der Hilfsschaltkreis freigegeben ist.
11. Schaltkreis (2) mit getakteten Kapazitäten, nach Anspruch 7, wobei der Bruchteil der
Abtastphase eine Dauer hat, die so ausgewählt ist, dass der Komparator (CMP) einen
Restbruchteil der Abtastphase zu seiner Verfügung hat, die ausreichend lang ist, um
den ersten und zweiten gemeinsamen Knoten (NS, NS') von den durch die Hilfsschaltkreise
aufgezwungenen Spannungen (VA, Va') zurück auf ihre eigenen Gleichtaktspannungen (VCM, Vcm') zu bringen.
12. Analog/Digital-Wandler, dadurch gekennzeichnet, dass er einen Schaltkreis (2) nach einem der vorhergehenden Ansprüche mit getakteten Kapazitäten
umfasst.
13. Analog/Digital-Wandler nach Anspruch 12, darüber hinaus einen Steuerabschnitt (CNTRL)
umfassend, der in der Lage ist, Signale zu generieren, um den Abschnitt (SC) mit getakteten
Kapazitäten gemäß eines Umwandlungsverfahrens des Typs sukzessive Approximation (SAR)
zu steuern.
1. Circuit à capacités commutées (2) comportant :
une section de capacités commutées (SC), adaptée pour être chargée, pour échantillonner
un signal d'entrée (VINP, VINM), au cours d'une phase d'échantillonnage, ladite section comprenant au moins un groupe
(AR, AR') de condensateurs (Ca, Cb, Cc, Ca', Cb', Cc') dont chacun comporte une borne
connectée à un noeud commun (NS, NS') ;
au moins un étage opérationnel (CMP) comportant au moins une borne d'entrée (IN, IN')
connectée audit noeud commun (NS, NS'), l'étage opérationnel (CMP) étant adapté pour
fournir au cours de la phase d'échantillonnage un courant audit noeud commun (NS,
NS') pour charger ledit groupe (AR, AR') de condensateurs ;
un circuit auxiliaire (ANC) connecté audit noeud commun (NS, NS') et capable d'être
activé/désactivé par un signal d'activation (PRECH) pour l'injection d'un courant
supplémentaire dans ledit noeud commun (NS, NS') et pour l'augmentation du courant
fourni audit noeud commun (NS, NS') pendant au moins un intervalle de temps égal à
une fraction de ladite phase d'échantillonnage, ladite fraction comportant une partie
initiale de ladite phase d'échantillannage ;
caractérisé en ce que
ledit signal d'activation (PRECH) est destiné à désactiver ledit circuit auxiliaire
(ANC) avant la fin de ladite phase d'échantillonnage et à la fin de ladite fraction,
afin de laisser ledit étage opérationnel (CMP) compléter, seul, l'opération de charge
dudit groupe de condensateurs au cours d'une partie restante et finale de ladite phase
d'échantillonnage.
2. Circuit à capacités commutées (2) selon la revendication 1, dans lequel, lorsque ledit
circuit auxiliaire est activé, ledit noeud commun (NS, NS') :
présente une impédance sensiblement réduite par rapport à l'impédance prise par ledit
noeud (NS, NS') lorsque le circuit auxiliaire (ANC) est désactivé ; et
est forcé à une tension ayant une valeur approximativement égale à la tension à laquelle
ledit noeud (NS, NS') est forcé lorsque le circuit auxiliaire (ANC) est désactivé.
3. Circuit à capacités commutées (2) selon la revendication 1, dans lequel ledit circuit
auxiliaire (ANC) comporte au moins un étage auxiliaire (A, A') comprenant un générateur
de courant (14, 14') et un élément de charge (M4, M4') en série avec ledit générateur
de courant (14, 14').
4. Circuit à capacités commutées (2) selon la revendication 3, dans lequel ledit circuit
auxiliaire (ANC) comporte un premier commutateur électronique (M1, M1') connecté en
série entre ledit générateur de courant (14, 14') et ledit élément de charge (M4,
M4'), comportant une borne de commande (g1, g1') destinée à être commandée par ledit
signal d'activation.
5. Circuit à capacités commutées (2) selon la revendication 4, dans lequel ledit circuit
auxiliaire (ANC) comporte en outre un deuxième commutateur électronique (M2, M2')
connecté en série entre ledit premier commutateur (M1, M1') et ledit élément de charge
(M4, M4'), comportant une borne de commande (g2, g2') destinée à être commandée par
ledit signal d'activation (PRECH).
6. Circuit à capacités commutées (2) selon la revendication 1, dans lequel ledit étage
opérationnel (CMP) est un comparateur de tension qui peut prendre une configuration
de réinitialisation en boucle fermée, et dans lequel ledit comparateur (CMP) est dans
ladite configuration de réinitialisation en boucle fermée pendant toute la durée de
ladite phase d'échantillonnage, ladite phase d'échantillonnage étant suivie d'une
phase de comparaison.
7. Circuit à capacités commutées (2) selon la revendication 6, dans lequel ledit comparateur
(CMP) comporte au moins un premier étage (FC_1) comportant une borne de sortie (Out,
Out') connectée à une borne de sortie (Y, Y') dudit circuit auxiliaire (ANC), le circuit
auxiliaire (ANC) étant directement connecté au noeud commun (NS, NS') lorsque le comparateur
(CMP) est dans ladite configuration de réinitialisation en boucle fermée.
8. Circuit à capacités commutées (2) selon la revendication 7, dans lequel :
ledit signal d'entrée est un signal différentiel ;
ledit au moins un groupe de condensateurs (Ca, Cb, Cc, Ca', Cb', Cc') comporte un
premier groupe de condensateurs (Ca, Cb, Cc) ayant une borne respective connectée
à un premier noeud commun (NS) et comporte un deuxième groupe de condensateurs (Ca',
Cb', Cc') ayant une borne respective connectée à un deuxième noeud commun (NS') ;
ledit comparateur (CMP) est un comparateur différentiel comportant des première (IN)
et deuxième (IN') bornes d'entrée connectées, respectivement, auxdits premier (NS)
et deuxième (NS') noeuds communs ;
et dans lequel ledit circuit auxiliaire comporte des premier (A) et deuxième (A')
étages auxiliaires connectés, respectivement, auxdits premier (NS) et deuxième (NS')
noeuds communs.
9. Circuit à capacités commutées (2) selon la revendication 8, dans lequel ledit comparateur
(CMP) comporte des première (ML2) et deuxième (ML1) diodes de charge, où lesdits premier
(A) et deuxième (A') étages auxiliaires comprennent, respectivement, des premier (M4)
et deuxième (M4') éléments de charge ayant un rapport largeur/longueur respectif à
peu près N fois plus grand que celui desdites première et deuxième diodes de charge,
où N est un nombre supérieur à 1.
10. Circuit à capacités commutées (2) selon la revendication 8 ou la revendication 9,
dans lequel ledit comparateur (CMP) comporte des générateurs de polarisation permettant
de fournir ledit courant auxdits premier (NS) et deuxième (NS') noeuds communs et
dans lequel lesdits premier (A) et deuxième (A') étages auxiliaires comportent un
générateur de courant respectif (I4, I4') permettant de fournir auxdits premier (NS)
et deuxième (NS') noeuds communs un courant respectif N fois plus grand que ledit
courant fourni par le comparateur (CMP), les premier et deuxième étages auxiliaires
fournissant ledit courant respectif auxdits noeuds communs (NS, NS') lorsque ledit
circuit auxiliaire est activé.
11. Circuit à capacités commutées (2) selon la revendication 7, dans lequel ladite fraction
de phase d'échantillonnage a une durée sélectionnée de sorte que ledit comparateur
(CMP) ait à sa disposition une fraction résiduelle de ladite phase d'échantillonnage
suffisamment longue pour ramener lesdits premier et deuxième noeuds communs (NS, NS')
à partir de tensions (VA, VA') imposées par lesdits circuits auxiliaires à leurs tensions de mode commun intrinsèques
(VCM, VCM').
12. Convertisseur analogique/numérique caractérisé en ce qu'il comporte un circuit à capacités commutées (2) selon l'une quelconque des revendications
précédentes.
13. Convertisseur analogique/numérique selon la revendication 12, comportant en outre
une section de commande (CNTRL) capable de générer des signaux pour commander ladite
section de capacités commutées (SC) selon une technique de conversion du type par
approximations successives (SAR).