NEURAL NETWORK UNIT WITH NEURAL MEMORY AND ARRAY OF NEURAL PROCESSING UNITS THAT COLLECTIVELY SHIFT ROW OF DATA RECEIVED FROM NEURAL MEMORY

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EP 3 154 001 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	16.08.2017 Bulletin 2017/33

(43)	Date of publication A2:
	12.04.2017 Bulletin 2017/15

(21)	Application number: 16192953.4

(22)	Date of filing: 07.10.2016

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International Patent Classification (IPC):

G06N 3/063^(2006.01)

G06F 9/00^(2006.01)

(84)	Designated Contracting States:
	AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
	Designated Extension States:
	BA ME
	Designated Validation States:
	MA MD

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Priority:

08.10.2015 US 201562239254 P
02.12.2015 US 201562262104 P
24.02.2016 US 201662299191 P
05.04.2016 US 201615090665
05.04.2016 US 201615090666
05.04.2016 US 201615090669
05.04.2016 US 201615090672
05.04.2016 US 201615090678
05.04.2016 US 201615090691
05.04.2016 US 201615090696
05.04.2016 US 201615090708
05.04.2016 US 201615090712
05.04.2016 US 201615090722
05.04.2016 US 201615090794
05.04.2016 US 201615090798
05.04.2016 US 201615090823

(71)	Applicant: VIA Alliance Semiconductor Co., Ltd.
	Shanghai 201203 (CN)

(72)	Inventors:
	HENRY, G Glenn Austin, TX Texas 78746 (US) PARKS, Terry Austin, TX Texas 78737 (US)

(74)	Representative: Rees, Simon John Lewis
	Haseltine Lake LLP Redcliff Quay 120 Redcliff Street Bristol BS1 6HU Bristol BS1 6HU (GB)

(54)	NEURAL NETWORK UNIT WITH NEURAL MEMORY AND ARRAY OF NEURAL PROCESSING UNITS THAT COLLECTIVELY SHIFT ROW OF DATA RECEIVED FROM NEURAL MEMORY

(57) An array of N processing units (PU) each has: an accumulator; an arithmetic unit performs an operation on first, second and third inputs to generate a result to store in the accumulator, the first input receives the accumulator output; a weight input is received by the second input to the arithmetic unit; a multiplexed register has first and second data inputs, an output received by the third input to the arithmetic unit, and a control input that controls the data input selection. The multiplexed register output is also received by an adjacent PU's multiplexed register second data input. The N PU's multiplexed registers collectively operate as an N-word rotater when the control input specifies the second data input. Respective first/second memories hold W/D rows of N weight/data words and provide the N weight/data words to the corresponding weight/ multiplexed register first data inputs of the N PUs.

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