FIELD OF THE INVENTION
[0001] The field of the invention relates generally to a method for producing atomically
thick sheets of graphene on a substrate, such as a semiconductor substrate, and more
specifically to a method for producing layers of atomically thick sheets of graphene
on a cobalt layer, which is in contact with the semiconductor substrate.
BACKGROUND OF THE INVENTION
[0002] A single atom thick graphene is the youngest allotrope of carbon and in the last
decade it has become one of the most researched material in the scientific community
because of its excellent optical, mechanical, and electrical properties. Graphene
is the hexagonal arrangement of carbon atoms forming a one-atom thick planar sheet
of sp
2 hybridized (double bonded) carbon atoms arranged in a honeycomb lattice. Graphene
is a promising electronic material. It has the potential to significantly impact the
semiconductor industry due to its superior electrical, thermal, mechanical, and optical
properties while at the same time offering compatibility with existing semiconductor
processing techniques. Graphene has shown extraordinary applications, including single
molecule detection, ultrafast FETs, hydrogen visualization-template for TEM, and tunable
spintronic devices. Furthermore, it exhibits high thermal conductivity (25 x silicon),
high mechanical strength (strongest nanomaterial), high optical transparency (80%),
carrier controlled interband/optical-transition, and flexible structure. Electronically,
graphene is a semi-metal with zero band-gap owing to the conduction band touching
the valence band at two points (K and K') in the Brillouin zone. Graphene's high density
of π-electrons from the sp
2 carbon atoms and carrier-confinement in an open crystallographic structure imparts
it with the highest mobility measured to date.
[0003] In order to realize these benefits in volume manufacturing, paths to integrating
graphene on large diameter semiconductor, e.g., silicon, substrates are necessary.
Current processes require graphene to be transferred from a metal base to the desired
substrate. This transfer process of an atomically-thick sheet is challenging and leads
to low yield and a significant density of folds and tears.
[0004] Since the successful isolation, identification, and characterization of graphene
by A. Geim and K. Novoselov in 2004, the most common method for producing flakes of
graphene has been by tape exfoliation from graphite and transfer to an oxidized silicon
wafer. The transfer process for graphene from a metal (a) is not feasible for large
scale synthesis due to inconsistent coverage, (b) leaves transfer polymer residue
on graphene (PMMA, PDMS, thermal-adhesive-tape) increasing carrier-scattering, and
(c) produces folds, wrinkles, and tears. Therefore, transfer of graphene is not feasible
for industrial processing. Clearly, the scotch-tape method is not scalable for semiconductor
industry. As a result of these deficiencies, this method produces small, irregularly
shaped flakes of graphene and is not suitable for scaling to large diameter integration
with silicon. See
A. K. Geim and K.S. Novoselov, "The Rise of Graphene" Nature Materials 6 (2007) 183-191.
[0005] Research into producing wafer level graphene and large area sheets of graphene has
produced the development of two main options.
[0006] First, W. deHeer's group at Georgia Institute of Technology has demonstrated the
formation of graphene layers on SiC wafer by silicon sublimation and out-diffusion
at very high temperature. The disadvantage of this technique is the high cost of SiC
wafers, the smaller diameter SiC wafers, and the absence of integration scale possible
on silicon wafers. Some groups are working on depositing SiC on Silicon and attempting
to form graphene on the deposited SiC layer. See
P. First, W. deHeer et al, "Epitaxial Graphenes on Silicon Carbide" MRS Bulletin 35,
296-305 (2010).
[0007] Groups in Korea and the University of Texas system have demonstrated graphene formation
on metal foils such as Cu and Ni. See
S. Bae et al, "Roll-to Roll Production of 30 inch Graphene Films for Transparent Electrodes"
Nature Nanotechnology 5, 574-578 (2010) and
X. Li et al, ECS Transactions, "Synthesis, Characterization, and Properties of Large-Area
Graphene Films" 19 (5), 41-52 (2005). Using a carbon source such as methane mixed with hydrogen at temperatures in the
700-1000°C range in a CVD chamber at pressure such as 500 millitorr, carbon is absorbed
into the metal film and upon cooling segregates or precipitates to the surface of
the metal foil forming single or multi-layer graphene depending on the process conditions
and the metal foil. The graphene layer then has to be transferred to oxidized silicon.
The transfer process generally uses a material like PMMA on graphene followed by dissolution
of the metal foil, then graphene is interfaced to the silicon dioxide layer, and finally
the PMMA is removed leaving graphene on SiO
2 on Silicon. Although the graphene formation on metal foils enables large sheets of
graphene to be produced, the process for transferring large area graphene sheets to
large diameter silicon substrates for electronic device fabrication is challenging.
Issues such as film stress, chemical residues, bonding defects, and wrinkles in the
graphene film are likely to be significant challenges for a manufacturable process.
[0009] M.E. Ramon et al. describe a synthesis of large-area, high mobility graphene by CVD
of acetylene on cobalt films in
ACS Nano, vol. 5, p. 7198 to 7204 (September 2011). According to this publication, graphene is grown on annealed Co films in a rapid
thermal chemical vapor deposition (RTCVD) furnace at ∼800°C, using acetylene as the
carbon source.
BRIEF DESCRIPTION OF THE INVENTION
[0010] Briefly, the present invention is directed to a method of forming a multilayer structure
as defined in claim 1, the method comprising: epitaxially depositing a graphene layer
on a layer comprising cobalt, wherein the layer comprising cobalt is in contact with
a dielectric layer, and further wherein the dielectric layer is in contact with a
front wafer surface of a semiconductor wafer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011]
FIGS. 1A through 1D depict the process flow according to an embodiment of the present
invention.
FIGS. 2A through 2D are X-ray diffraction spectra of deposited cobalt layers. FIG.
2A is the spectra after E-beam evaporation. FIG. 2B is the spectra after heating to
1000°C. FIG. 2C is the spectra after heating to 1000°C and annealing for 10 min. FIG.
2D is the spectra after graphene growth.
FIG. 3 is Raman spectroscopic analysis of single-layer graphene on Co surfaces. The
spectrum shows graphene's characteristic G and 2D-bands with ratio of 7.5 with no
D-band.
DETAILED DESCRIPTION OF THE EMBODIMENT(S) OF THE INVENTION
[0012] The present invention is directed to a method for forming graphene directly on a
semiconductor substrate which is a silicon wafer which comprises a dielectric layer.
By direct, it is meant that the graphene is formed on the substrate without layer
transfer. A layer comprising cobalt is deposited on the front surface of the wafer,
which comprises a dielectric layer. Thereafter, a layer of graphene is formed on the
layer comprising cobalt. The result is a multilayer article comprising a semiconductor
substrate, a layer comprising cobalt, and a layer of graphene. Advantageously, the
method of the present invention enables coating at least a portion of a large diameter
semiconductor wafer, i.e. a silicon wafer coated with silicon dioxide, with at least
a layer of graphene.
[0013] This invention relies on the high-quality, defect-free, single-layer graphene with
maximum coverage on thin films of cobalt (Co) on SiO
2/Si substrate
via high temperature, and low-pressure chemical vapor deposition of a carbon-containing
gas on the cobalt surface. The graphene formation on Co is precipitation-based due
to high carbon solubility (0.9 wt%) in Co at high temperature (1320°C). Since the
grain size of Co is increased, during the high temperature growth, surface nucleation
of graphene is dominant and the graphene is able to grow in large single crystal (several
micrometers). Furthermore, since the cooling stage is fast, the precipitation of carbon
radical forms single-layer on the surface of the Cobalt. Due to the strong adhesion
of graphene and cobalt, the growth is preferably epitaxial.
I. Substrates for Layer Deposition
[0014] According to the method of the present invention, the graphene layer or layers is/are
formed directly on a semiconductor substrate, i.e., without a layer transfer step.
With reference now to FIG. 1A, a semiconductor substrate
10 may comprise two major, generally parallel surfaces, one of which is a front surface
of the substrate and the other of which is a back surface of the substrate. A circumferential
edge joins the front and back surfaces, and a central plane lies between the front
and back surfaces. The substrate
10 comprises a bulk region between the front and back surfaces. Prior to any operation
as described herein, the front surface and the back surface of the substrate
10 may be substantially identical. A surface is referred to as a "front surface" or
a "back surface" merely for convenience and generally to distinguish the surface upon
which the operations of method of the present invention are performed. In the present
invention, the operations of the invention are performed on the front surface of the
semiconductor substrate
10. In some embodiments of the present invention, the operations of the present invention
are performed on both the front surface and the back surface of the semiconductor
substrate
10.
[0015] In general, the semiconductor wafer has a diameter of at least 20 mm, more typically
between 20 mm and 500 mm. In some embodiments, the diameter is at least 20 mm, at
least 45 mm, at least 90 mm, at least 100 mm, at least 150 mm, at least 200 mm, at
least 250 mm, at least 300 mm, at least 350 mm, or even at least 450 mm. The semiconductor
wafer may have a thickness between 100 micrometers and 5000 micrometers, such as between
100 micrometers and 1500 micrometers, suitably within the range of 500 micrometers
to 1000 micrometers.
[0016] In particularly preferred embodiments, the semiconductor wafer comprises a wafer
sliced from a single crystal silicon wafer which has been sliced from a single crystal
ingot grown in accordance with conventional Czochralski crystal growing methods. Such
methods, as well as standard silicon slicing, lapping, etching, and polishing techniques
are disclosed, for example, in
F. Shimura, Semiconductor Silicon Crystal Technology, Academic Press, 1989, and
Silicon Chemical Etching, (J. Grabmaier ed.) Springer-Verlag, N.Y., 1982. In some preferred embodiments, the semiconductor silicon substrate is a polished
silicon wafer grown by the CZ method. The silicon substrate may have any crystal orientation,
e.g., (100), (110), and (111).
[0017] Silicon wafer resistivity is not critical to forming a graphene layer on the substrate.
However, resistivity may vary depending upon end use requirements. In view thereof,
the wafer may be heavily doped, may be semi-insulating, or may have a doping profile
somewhere between. The resistivity may therefore vary from milliohm or less to megaohm
or more. In some embodiments, the single crystal semiconductor wafer comprises a p-type
or an n-type dopant. Suitable dopants include boron (p type), gallium (p type), phosphorus
(n type), antimony (n type), and arsenic (n type). The dopant concentration is selected
based on the desired resistivity of the wafer. In some embodiments, the wafer types
may have resistivity so that they can be characterized as any of N++ type, N+ type,
N type, N- type, and N--type. Typical N+ resistivity ranges are as low as 10 milliohm-cm
for Sb doping, N++ as low as 2 milliohm-cm for As doping, and N+++ as low as 1 milliohm-cm
for P doping. Specification ranges are usually 2-3X for max/min due to segregation
in crystal growth. In some embodiments, the wafer types may have resistivity so that
they can be characterized as any of P++ type, P+ type, P type, P- type, and P--type.
Typical P+ resistivity range is as low as 10 milliohm-cm and P++ as low as 5 milliohm-cm.
Specification ranges are usually 1.5-2X for max/min due to segregation in crystal
growth. The resistivity of the wafer may therefore vary from 0.1 milliohm-cm to 10
kiloohm-cm. In some embodiments, the resistivity may range from 0.1 milliohm-cm to
1 kiloohm-cm, such as from 0.1 milliohm-cm to 100 ohm-cm, such as from 0.1 milliohm-cm
to 10 ohm-cm, or from 0.1 milliohm-cm to 1 ohm-cm. Substrate are also available in
lightly doped form, such as nominal values of 1 ohm-cm or 10 ohm-cm or 100 ohm-cm,
in both N-type (Phos) and P-type (Boron). Choice of substrate resistivity depends
on application (for example, if substrate is used as backgate then lower resistivity
is preferred) but should not impact growth of the graphene layer.
[0018] With reference now to FIG. 1B, one or more of the major surfaces of the semiconductor
substrate
10 is modified with a dielectric layer
20. The dielectric layer is a silicon dioxide layer.. In preferred embodiments wherein
the semiconductor substrate
10 comprises a silicon wafer, the front surface of the silicon wafer is preferably oxidized
such that the front surface layer of the silicon wafer comprises a silicon dioxide
(SiO
2) dielectric layer
20 having a thickness between 10 nm and 1000 nm, between 30 nm and 1000 nm, between
50 nm and 500 nm, preferably between 50 nm and 300 nm, such as between 90 nm and 300
nanometers thick, or between 90 nm and 200 nanometers thick. Deposition of the dielectric
layer may be accomplished by means known in the art, such as thermal oxidation (in
which some portion of the deposited semiconductor material film will be consumed)
and/or CVD oxide deposition. In some embodiments, the wafer may be thermally oxidized
(in which some portion of the deposited semiconductor material film will be consumed)
or the film may be grown by CVD oxide deposition. In some embodiments, the wafer may
be thermally oxidized in a furnace such as an ASM A400. The front surface of the silicon
wafer may be thermally oxidized via wet or dry oxidation, as is known in the art.
Oxidation generally occurs at temperatures between 800°C and 1200°C using water vapor
and/or oxygen. The oxidizing ambient atmosphere can be a mixture of inert gas, such
as Ar or N
2, and O
2. The oxygen content may vary from 1 to 10 percent, or higher. In some embodiments,
the oxidizing ambient atmosphere may be up to 100% (a "dry oxidation"). In some embodiments,
the ambient atmosphere may comprise a mixture of inert gas, such as Ar or N
2, and oxidizing gases, such as O
2 and water vapor (a "wet oxidation"). In an exemplary embodiment, semiconductor wafers
may be loaded into a vertical furnace, such as an A400. The temperature is ramped
to the oxidizing temperature with a mixture of N
2 and O
2. After the desired oxide thickness has been obtained, the O
2 is turned off and the furnace temperature is reduced and wafers are unloaded from
the furnace.
[0019] In some embodiments, the semiconductor substrate
10 may comprise a dielectric layer
20 comprising silicon nitride. In some embodiments, the semiconductor substrate
10 comprises a silicon wafer, the front surface layer of which is oxidized as described
above, which is followed by deposition of a silicon nitride layer. A silicon nitride
layer may be deposited on the silicon oxide layer since silicon nitride advantageously
forms a barrier layer to reduce diffusion of metal atoms, e.g., nickel, into the silicon
oxide layer. In some embodiments, the silicon nitride layer may range in thickness
between 10 nm and 1000 nm, between 30 nm and 1000 nm, or from 50 nanometers to 1000
nanometers. In some embodiments, the silicon nitride layer may range in thickness
from 50 nanometers to 500 nanometers. In some embodiments, the silicon nitride layer
may range in thickness from 70 nanometers to 250 nanometers. The thickness of the
silicon nitride layer is determined in view of the trade-off between device performance,
such that thinner layers are preferred, and an effective barrier to prevent in-diffusion
of impurities into the semiconductor substrate, such that thicker layers are preferred.
Silicon nitride may be deposited on the surface of the silicon oxide layer by contacting
the substrate with an atmosphere of nitrogen at elevated temperature. For example,
the semiconductor may be exposed to nitrogen gas or ammonia at temperatures ranging
from 700°C to 1300°C. In some embodiments, silicon nitride is formed by chemical vapor
deposition at 800°C. In order to incorporate nitrogen and oxygen to deposit silicon
oxynitride, the atmosphere may comprise a combination of oxygen and nitrogen, and
the temperature may be increased to a temperature between 1100°C and 1400°C. An alternative
nitrogen source is ammonia.
[0020] In some embodiments, the semiconductor substrate
10 comprising the dielectric layer
20 is cleaned prior to deposition of the layer comprising cobalt, for example to remove
organic matter or other impurities. A suitable cleaning solution is the piranha solution,
which comprises H
2SO
4 (concentrated) and H
2O
2 (30% solution), typically in a 3:1 ratio, but other ratios, such as 4:1 or 7:1 are
suitable. Cleaning duration is suitably between 15 minutes and 2 hours.
II. Deposition of Layer comprising Cobalt
[0021] With reference to FIG. 1C, according to the method of the present invention, the
major surface of the semiconductor substrate
10, i.e., a silicon wafer comprising a dielectric layer
20, i.e., a silicon oxide layer and optionally a silicon nitride layer and/or a silicon
oxynitride layer, is coated with a layer comprising cobalt
30. In some embodiments, the layer comprising cobalt
30 may be deposited over the entire major surface of the semiconductor substrate
10 comprising a dielectric layer
20. In some embodiments, the layer comprising cobalt
30 may be deposited over a portion of the semiconductor substrate
10 comprising a dielectric layer
20, such as at least 10% of the total area of the major surface, or at least 25% of
the total area, or at least 50% of the total area, or at least 75% of the total area.
In some embodiments, the layer comprising cobalt
30 may be deposited over the entire major surface of the semiconductor substrate
10 comprising a dielectric layer
20 and thereafter metal may be removed selectively, using conventional lithography techniques,
to thereby leave a desired pattern of metal deposition on the major surface of the
substrate. The front surface layer of the semiconductor substrate
10 comprising a dielectric layer
20 is coated with a layer comprising cobalt
30. In some embodiments, the semiconductor substrate
10 comprises a silicon wafer having a silicon dioxide front surface layer, and the layer
comprising cobalt
30 is deposited onto the silicon dioxide front surface layer. The silicon dioxide layer
may be completely coated with cobalt, partially coated with cobalt, or coated with
a cobalt pattern by lithography. In some embodiments, the semiconductor substrate
10 comprises a silicon wafer having a silicon dioxide layer and a silicon nitride front
surface layer, and the layer comprising cobalt
30 is deposited onto the silicon nitride front surface layer. The silicon nitride layer
may be completely coated with cobalt, partially coated with cobalt, or coated with
a cobalt pattern by lithography. For the sake of convenience, the surfaces of the
layer comprising cobalt
30 may be referred to as a "front cobalt layer surface" and "a back cobalt layer surface."
Herein, the back cobalt layer surface is in contact with the dielectric layer
20. The graphene layer is deposited on the front cobalt layer surface. A bulk metal
region is between the front and back cobalt layer surfaces.
[0022] The layer comprising cobalt
30 is deposited by techniques known in the art, including sputtering, evaporation, electron-beam
evaporation, ion beam evaporation, chemical vapor deposition, electrolytic plating,
and metal foil bonding. In some embodiments, the layer comprising cobalt
30 is deposited by sputtering or evaporation using, e.g., a Sputtering and Metal evaporation
Unit. In some embodiments, a cobalt layer may be deposited
via electron-beam evaporation technique in a clean room environment, using, for example,
a Varian Electron Beam Evaporator. Electrolytic metal plating may occur according
to the methods described by
Supriya, L.; Claus, R. O. Solution-Based Assembly of Conductive Gold Film on Flexible
Polymer Substrates: Langmuir 2004, 20, 8870-8876. In some embodiments, the layer comprising cobalt
30 may be deposited by chemical vapor deposition at relatively low temperatures, such
as between 100°C and 300°C, such as 200°C. Preferably, the layer comprising cobalt
30 is between 50 nanometers and 20 micrometers thick, such as between 50 nanometers
and 10 micrometers thick, such as between 50 nanometers and 1000 nanometers (1 micrometer),
such as between 100 nanometers and 500 nanometers, such as between 100 nanometers
and 400 nanometers, such as 300 nanometers or 500 nanometers.
[0023] The use of cobalt for the deposition of a graphene layers is advantageous since,
unlike copper (with carbon solubility of 0.01 wt% at 1084°C), the graphene formation
in Co is precipitation-based. This is due to the high carbon solubility (0.9 wt%)
in Co at high temperature (1320°C). Accordingly, the carbon prefers to precipitate
near the grain boundaries during cooling. It has been observed that high temperature
growth enhances the rapid precipitation and surface nucleation so that graphene nuclei
try to attach to each other preferentially in the same orientation resulting epitaxial
growth of large coverage single-layer graphene.
[0024] After deposition of the metal film, the multilayer structure is cleaned. The multilayer
structure comprises the semiconductor substrate
10, dielectric layer
20 (i.e., silicon dioxide, which may additionally comprise a silicon nitride layer),
and a layer comprising cobalt
30. The multilayer structure may be cleaned by heating the structure in a vacuum furnace
in a reducing atmosphere. A chemical vapor deposition system may be used where only
baking under high vacuum is performed. In preferred embodiments, the reducing atmosphere
comprises hydrogen gas or other reducing gas. An inert carrier gas may be used, such
as argon or helium. The temperature during exposure to the reducing atmosphere is
between 800°C and 1200°C, such as 1000°C. The pressure is preferably sub-atmospheric,
such as less than 100 Pa (less than 1 Torr), preferably less than 1 Pa (less than
0.01 Torr), even more preferably less than 0.1 Pa (less than 0.001 Torr), and even
more preferably less than 0.01 Pa (less than 0.0001 Torr). The cleaning anneal may
adjust the grain size of the metal film, e.g., increase the grain size at elevated
temperatures.
[0025] After heat treatment, the multilayer substrate (FIG. 1C) is analyzed by X-ray diffraction
to confirm crystallographic orientations. The X-ray diffraction analysis reveals a
single crystalline Co film on SiO
2/Si substrate, which enables the formation of very-high quality graphene. Annealing
the multilayer structure after deposition of the layer comprising cobalt promotes
epitaxial growth, as confirmed by analyzing the Co surface before and after annealing
via X-ray diffraction (XRD). See FIGS. 2A through 2D. That is, before anneal, the XRD
pattern for room temperature (RT) evaporated Co reveals three diffraction peaks. See
FIG. 2A. The strong peak at 44° corresponds to either hexagonal closed packed (hcp)
Co(0002) or face centered cubic (fcc) Co(111). See
Ago et al., ACS Nano, 4, 7407 (2010). The XRD pattern for non-annealed cobalt also reveals another two weak peaks at
42° (Co(200)) and 47° (hcp Co(101)). See
J. Mater. Chem., 2009, 19, 7371-7378. These results confirm the polycrystalline nature of the evaporated Co surface prior
to anneal. The layer comprising cobalt that has been subjected to anneal reveals a
different XRD pattern. For example, the Co(0002) or Co(111) peak at 44° for CVD annealed
Co (1000°C for 10 min) become stronger and narrower at its full width. See FIGS. 2B
and 2C. Additionally, anneal causes the weak peaks at 42° and 47° to disappear, which
implies improvement in the crystallinity of the annealed cobalt layer. A weak peak
at 52° appears, which may be due to Co(200). The XRD pattern of Co surface after graphene
formation shows the Co(0002) or Co(111) peak with little less strength because of
formation of the graphene layer. See FIG. 2D.
III. Deposition of Graphene Layer
[0026] According to some embodiments of the method of the present invention and with reference
to FIG. 1C, the multilayer structure comprising the semiconductor substrate
10, a dielectric layer
20, and a layer comprising cobalt
30 may be exposed to a carbon-containing gas to thereby nucleate atomic carbon on the
front cobalt layer surface of the layer comprising cobalt
30 and between crystalline cobalt grains.
[0027] In some embodiments, the structure is placed in an appropriate chamber, such as a
CVD system, and brought to a vacuum, such as a pressure of 0.1 Pa (1 mTorr). Thereafter,
the structure is brought to the appropriate anneal temperature in a reducing atmosphere.
The reducing atmosphere may comprise hydrogen. It may comprise between 1% and 99%
hydrogen, such as between 70% and 99% hydrogen, preferably 95% hydrogen, balance inert
gas.
[0028] In some embodiments, a carbon-containing gas flow may be added to the reducing gas
flow. The carbon-containing gas may be selected from among volatile hydrocarbons,
for example, methane, ethane, ethylene, acetylene, propane, propylene, propyne, butane,
isobutane, butylenes, butynes. The carbon-containing gas, e.g., methane, is a source
of carbon that may precipitate into graphene according to the process of the present
invention. The atmosphere may be a reducing atmosphere, further comprising a reducing
gas, such as hydrogen. In some embodiments, the gas may comprise methane gas and hydrogen
gas in a ratio from 1:1 to 200:1, such as between 1:1 and 100:1, such as 144:15. The
minimum temperature during carbon absorption and/or adsorption is generally at least
500°C. The maximum temperature during carbon absorption and/or adsorption is generally
no more than 1100°C. In general, the temperature is preferably between 700°C and 1000°C.
In general, the pressure inside the reaction chamber during hydrogen gas/methane flow
is between 10 Pa (0.1 Torr) and 1500 Pa (100 Torr), such as between 50 P (0.4 Torr)
and 150 Pa (1 Torr).
[0029] Optionally, after the flow of gases is stopped, the structure may be held at the
absorption temperature in order to promote equilibrium of nucleation and adsorption
between the crystalline cobalt grains. The duration of equilibration after the flow
of carbon-containing gas is stopped may range from 5 seconds to 3600 seconds, such
as 600 seconds to 1800 seconds. In some embodiments, the duration of carbon in-diffusion
is very short, such as 10 seconds.
[0030] Thereafter, the multilayer structure is rapidly cooled, such as at a rate of at least
10°C/min, at least 50°C/min, at least 100°C/min. In general, the pressure inside the
reaction chamber during cooling is between 10 Pa (0.1 Torr) and 1500 Pa (100 Torr),
such as between 50 Pa (0.4 Torr) and 150 Pa (1 Torr). The atmosphere is preferably
a reducing atmosphere, which may comprise between 1% and 99% hydrogen, such as between
70% and 99% hydrogen, preferably 95% hydrogen, balance inert gas. High temperature
growth and rapid cooling enhance the precipitation and surface nucleation fast so
that graphene nuclei try to attach each other preferentially in the same orientation
resulting in epitaxial growth of large coverage, high quality single-layer graphene.
See FIG. 1D, depicting a multilayer structure comprising the semiconductor substrate
10, the dielectric layer
20, the layer comprising cobalt
30, and the single-layer graphene
40.
IV. Graphene Layer Quality Testing
[0031] The deposited and cooled graphene layer
40 in contact with the layer comprising cobalt
30 may be analyzed by Raman spectroscopy to determine the quality of the deposited layer.
Raman spectroscopy is a commanding technique to ascertain the number of graphene layers
and defects. Raman spectroscopy and 2D mapping to determine the quality of the deposited
graphene may be performed with a 532 nm excitation laser. The quality of the deposited
graphene may be determined by reference to several bands in the resultant Raman spectrum.
See FIG. 3. These bands include: (i) the D band (∼1,350 cm
-1) attributing to the breathing mode of sp
2 carbons activated by presence of defects, (ii) the G band (∼1,580 cm
-1) representing the E
2g mode of the C-C stretching vibration in the graphitic lattice at the γ-point, and
(iii) the 2D band (∼2,690 cm
-1) due to the second order two-phonon process in graphene. Additionally, in the representative
sample surface (the D-band map), it is also noticed that the intensity ratio i.e.
I
D/I
G are negligibly small and near the background level for most of the graphene area,
indicating low defect contents and an absence of crystal grain boundaries, which also
indicates the formation of single grain graphene. The G-band map and 2D-band map clearly
show the presence of single-layer graphene in the whole sample surface. The quality
of a single-layer graphene may be determined by the ratio of the intensities of Raman
2D to G-band peaks (I
2D/I
G≥2). This ratio of the intensities of Raman 2D to G-band peaks may be referred to
herein as a "quality factor." High quality graphene exhibits a Raman 2D to G-band
peak ratio (I
2D/I
G) or quality factor ratio of at least 4, such as at least 7, at least 7.5, at least
8, or even at least 10. Additionally, in high quality graphene, no defect induced
D-band is observed. In comparison, I
2D/I
G for high-quality exfoliated graphene is 3 - 4.
[0032] The graphene may be further quality tested by transferring to transmission electron
microscopy grids for analysis of the selected area electron diffraction (SAED) patterns.
The SAED patterns confirm the hexagonal nature of graphene indicating the d-spacing
of 2.15 Å.
[0033] The following examples are provided to further illustrate the present invention.
Example 1. Cobalt Deposition on Silicon Wafer Substrate
[0034] Suitable silicon wafer substrates include:
- 1. A silicon wafer (n++ type) comprising a SiO2 dielectric having a thickness of 90 nm,
- 2. A silicon wafer (n++ type) comprising a SiO2 dielectric having a thickness of 300 nm,
- 3. A silicon wafer (p+ type) comprising a SiO2 dielectric having a thickness of 90 nm, and
- 4. A silicon wafer (p+ type) comprising a SiO2 dielectric having a thickness of 300 nm.
[0035] The bulk silicon substrates were obtained from SunEdison Semiconductor, Ltd. (St.
Peters, MO). The substrates may be provided with thermal silicon oxide layer, or they
may be provided without a thermal oxide layer.
[0036] The silicon wafers were cleaned using Piranha solution (H
2SO
4:H
2O
2 = 3:1) as necessary for durations between 15 minutes and 2 h. After cleaning and
rinsing, a thin film of cobalt having a thickness between about 100 nanometers and
about 300 nanometers were deposited on the silicon oxide layers of each wafer. The
cobalt layer was deposited
via electron-beam evaporation technique in a clean room environment. The instrument used
was a Varian Electron Beam Evaporator. The source of cobalt, i.e., the cobalt target,
was cobalt pellets having 99.99% purity and approximate dimensions of 1/4" diameter
x 1/4" length. The metal evaporation parameters in the reaction chamber were: Pressure:
10
-7 Torr; Voltage: 10 KV; Current: 45 mA; Tooling factor: 140%; Z-Ratio: 0.343; Density:
8.9 kg/m
3; Thickness of the deposited cobalt: 100 nm and 300 nm.
Example 2. Quality Testing of Cobalt Layer
[0037] The crystallinity of the cobalt layer is determined both before anneal and after
anneal. Crystallinity of the cobalt layer was measured by X-ray diffraction and analysis
of the XRD peaks. The multilayer structure (Co/SiO
2/Si) prepared according to Example 1 is heat-treated and subsequently analyzed via
X-ray diffraction (XRD) to confirm crystallographic orientations. See FIGS. 2A through
2D, which are X-ray diffraction spectra of deposited cobalt layers. FIG. 2A is the
spectra after E-beam evaporation according to the parameters set forth in Example
1. FIG. 2B is the spectra after heating to 1000°C. FIG. 2C is the spectra after heating
to 1000°C and annealing for 10 min. FIG. 2D is the spectra after graphene growth.
The X-ray diffraction analysis reveals a single crystalline Co film on SiO
2/Si substrate, which enables the formation of very-high quality graphene.
[0038] The XRD pattern for room temperature (RT) evaporated Co is performed in which three
diffraction peaks were observed. See FIG. 2A. The strong peak at 44° corresponds to
either hexagonal closed packed (hcp) Co(0002) or face centered cubic (fcc) Co(111)
and another two weak peaks are also observed at 42° (CoO (200)) and 47° (hcp Co(101)).
These peaks confirm the polycrystalline nature of evaporated Co surface.
[0039] The structure is subjected to anneal at 1000°C for 10 min. See FIG. 2B (at temperature
and before anneal) and FIG. 2C (after anneal at 1000°C for 10 minutes). The Co(0002)
and Co(111) peak at 44° in the annealed cobalt layer become stronger and narrower
at it full width. The weak peaks at 42° and 47° disappear. The change in XRD peaks
confirms improvement in the crystallinity of Co. A weak peak at 52° appears, which
may be due to Co(200).
Example 3. Growth of graphene on the prepared substrate via chemical vapor deposition (CVD)
[0040] A CVD system was designed where the substrate (1x1 inches) was placed in a split
tube furnace with a fused quartz tube (outside diameter of 1 inch). The precursor
gases included methane (CH
4) and hydrogen (H
2). Initially, the chamber is allowed to achieve a base pressure of 1 mTorr. Substrates
prepared according to Example 1 were directly placed in the center of quartz tube's
heating zone and heated to 1000°C in a hydrogen atmosphere at a flow rate of 100 standard
cubic centimeters per minute (SCCM) to restrict further oxidation. Right after the
temperature reaches 1000°C, the substrates were annealed for 5-10 minutes at the same
temperature at a pressure of 500 mTorr in a hydrogen atmosphere at a flow rate of
15 standard cubic centimeters per minute (SCCM). To nucleate carbon on the cobalt
surface and between cobalt grains, the gas composition was changed to CH
4:H
2 at a vol:vol ratio of 144:15. The pressure during methane:hydrogen flow was 1 Torr
for 10 minutes. This was followed by cooling at a rate of about 100°C/min. See FIG.
2D for the XRD spectra of the structure after deposition of graphene.
Example 4. Quality Testing of Epitaxially Deposited Graphene on Cobalt
[0041] The quality of the epitaxially deposited graphene on cobalt was tested by Raman spectroscopy
and 2D mapping with a 532 nm excitation laser. See FIG. 3, which is Raman spectroscopic
analysis of single-layer graphene on Co surfaces. The spectrum shows graphene's characteristic
G and 2D-bands with ratio of 7.5 with no D-band. The Raman spectrum of the epitaxial
graphene exhibited: (i) a negligible D band (∼1,350 cm
-1) attributing to the breathing mode of sp
2 carbons activated by presence of defects, (ii) a strong and sharp G band (∼1,580
cm
-1) representing the E
2g mode of the C-C stretching vibration in the graphitic lattice at the γ-point, and
(iii) a strong and sharp 2D band (∼2,690 cm
-1) due to the second order two-phonon process in graphene. In the representative sample
surface (the D-band map), it is also noticed that the intensity ratio, i.e. I
D/I
G are negligibly small and near the background level for most of the graphene area,
indicating low defect contents and an absence of crystal grain boundaries, which also
claims the formation of single grain graphene. The G-band map and 2D-band map clearly
show the presence of single-layer graphene in the whole sample surface. The quality
of a single-layer graphene may be determined by the ratio of the intensities of Raman
2D to G-band peaks (I
2D/I
G≥2). A superior Raman 2D to G-band peak ratio (I
2D/I
G) > 7.5 and no defect induced D-band is observed. In comparison, I
2D/I
G for high-quality exfoliated graphene is about 3 - 4.
[0042] The graphene is further transferred to transmission electron microscopy grids for
analysis of the selected area electron diffraction (SAED) patterns. The SAED patterns
confirm the hexagonal nature of graphene indicating the d-spacing of 2.15 Å.
1. A method of forming a multilayer structure, the method comprising:
depositing a layer comprising cobalt on a dielectric layer comprising a silicon dioxide
layer in contact with a front wafer surface of a silicon wafer, wherein the layer
comprising cobalt is deposited by a technique selected from the group consisting of
sputtering, evaporation, electron-beam evaporation, ion beam evaporation, chemical
vapor deposition, electrolytic plating, and metal foil bonding to thereby prepare
a structure comprising the silicon wafer, the dielectric layer, and the layer comprising
cobalt;
annealing the structure comprising the silicon wafer, the dielectric layer comprising
a silicon dioxide layer, and the layer comprising cobalt in a reducing atmosphere
at a temperature between 800°C and 1200°C to thereby prepare the layer comprising
single crystalline cobalt; and
epitaxially depositing a graphene layer on the layer comprising single crystalline
cobalt, wherein the graphene layer has a single mono-atomic thickness.
2. The method of claim 1 wherein the silicon wafer comprises a dopant selected from the
group consisting of boron (p type), gallium (p type), phosphorus (n type), antimony
(n type), and arsenic (n type), and any combination thereof.
3. The method of claim 1 or 2 wherein the layer comprising single crystalline cobalt
comprises a front cobalt layer surface, a back cobalt layer surface, and a bulk cobalt
layer region between the front cobalt layer surface and the back cobalt layer surface,
wherein the back cobalt layer surface is in contact with the dielectric layer.
4. The method of any one of claims 1 through 3 wherein the layer comprising single crystalline
cobalt is between about 50 nanometers and about 20 micrometers thick, preferably between
about 50 nanometers and about 10 micrometers thick, more preferably between about
50 nanometers and about 1 micrometer thick.
5. The method of any one of claims 1 through 4 wherein the layer comprising graphene
having a single mono-atomic thickness is epitaxially deposited on the layer comprising
single crystalline cobalt according to the following steps:
contacting the front cobalt layer surface of the layer comprising single crystalline
cobalt with a carbon-containing gas in a reducing atmosphere at a temperature sufficient
to nucleate carbon atoms on the front cobalt layer surface; and
precipitating carbon atoms to thereby epitaxially deposit the layer of graphene having
a single mono-atomic thickness on the front cobalt layer surface.
6. The method of claim 5 wherein the carbon atoms are precipitated by cooling the layer
comprising single crystalline cobalt in contact with a dielectric layer.
7. The method of claims 5 or 6 wherein the carbon-containing gas is selected from the
group consisting of methane, ethane, ethylene, acetylene, propane, propylene, propyne,
butanes, butylenes, butynes, and combinations thereof.
8. The method of any one of claims 5 through 7 wherein the reducing atmosphere comprises
hydrogen gas.
9. The method of claim 8 wherein the carbon-containing gas comprises methane and a ratio
of the methane and the hydrogen gas is from 1:1 to 200:1.
10. The method of claim 8 wherein the carbon-containing gas comprises methane and a ratio
of the methane and the hydrogen gas is 144:15.
11. The method of any one of claims 1 through 10 wherein the graphene layer having a single
mono-atomic thickness has a quality factor of at least 4, wherein the quality factor
is determined by the ratio of the intensities of the Raman 2D band peak to the Raman
G-band peak (I2D/IG).
12. The method of any one of claims 1 through 10 wherein the graphene layer having a single
mono-atomic thickness has a quality factor of at least 7.5, wherein the quality factor
is determined by the ratio of the intensities of the Raman 2D band peak to the Raman
G-band peak (I2D/IG).
13. The method of claim 12 wherein a Raman spectrum of the graphene layer exhibits a negligible
D band.
1. Ein Verfahren zur Herstellung einer Mehrschicht-Struktur, das Verfahren umfassend:
Ablagern einer kobalthaltigen Schicht auf einer dielektrischen Schicht umfassend eine
Siliciumdioxidschicht in Kontakt mit einer Wafervorderseite eines Siliciumwafers,
wobei die kobalthaltige Schicht abgelagert wird mit einer Technik ausgewählt aus der
Gruppe bestehend aus Sputtern, Verdampfung, Elektronenstrahl-Verdampfung, Ionenstrahl-Verdampfung,
Chemical Vapor Deposition, Elektrolytbeschichtung und Metallfolien-Bonding, um so
eine Struktur herzustellen, die den Siliciumwafer, die dielektrische Schicht und die
kobalthaltige Schicht umfasst;
Annealen der Struktur umfassend den Siliciumwafer, die dielektrische Schicht umfassend
eine Siliciumdioxidschicht, und die kobalthaltige Schicht in einer reduzierenden Atmosphäre
bei einer Temperatur zwischen 800°C und 1200°C, um so die Schicht umfassend Einkristall-Kobalt
zu erzeugen; und
Epitaxial-Ablagerung einer Graphenschicht auf der Schicht umfassend das Einkristall-Kobalt,
wobei die Graphenschicht eine monoatomischen Dicke hat.
2. Das Verfahren gemäß Anspruch 1 wobei der Siliciumwafer ein Dotiermittel enthält, ausgewählt
aus der Gruppe bestehend aus Bor (p-Typ), Gallium (p-Typ), Phosphor (n-Typ), Antimon
(n-Typ), und Arsen (n-Typ) und jeglicher Kombination davon.
3. Das Verfahren gemäß Anspruch 1 oder 2 wobei die Schicht umfassend das Einkristall-Kobalt
eine Kobaltschicht-Frontoberfläche, eine Kobaltschicht-Rückseitenoberfläche und eine
Kobaltschicht-Bulkregion zwischen der Kobaltschicht-Frontoberfläche und der Kobaltschicht-Rückseitenoberfläche
aufweist, wobei Kobaltschicht-Rückseitenoberfläche mit der dielektrischen Schicht
in Kontakt ist.
4. Das Verfahren gemäß irgendeinem der Ansprüche 1 bis 3 wobei die Schicht umfassend
das Einkristall-Kobalt zwischen etwa 50 Nanometern und etwa 20 Mikrometern dick ist,
bevorzugt zwischen etwa 50 Nanometern und etwa 10 Mikrometern dick ist, bevorzugter
zwischen etwa 50 Nanometern und etwa 1 Mikrometer dick ist.
5. Das Verfahren gemäß irgendeinem der Ansprüche 1 bis 4 wobei die graphenhaltige Schicht
mit der monoatomischen Dicke epitaxial abgelagert wird auf der Schicht umfassend das
Einkristall-Kobalt, gemäß den folgenden Schritten:
Kontaktieren der Frontoberfläche der Kobaltschicht der Schicht umfassend das Einkristall-Kobalt
mit einem kohlenstoffhaltigen Gas in einer reduzierenden Atmosphäre bei einer Temperatur,
die ausreicht um Kohlenstoffatome auf der Frontoberfläche der Kobaltschicht als Kristallisationskeime
zu binden; und
Präzipitieren von Kohlenstoffatomen, um so die graphenhaltige Schicht mit der monoatomischen
Dicke auf der Frontoberfläche der Kobaltschicht epitaxial abzulagern.
6. Das Verfahren gemäß Anspruch 5 wobei die Kohlenstoffatome präzipitiert werden indem
die Schicht umfassend das Einkristall-Kobalt in Kontakt mit einer dielektrischen Schicht
gekühlt wird.
7. Das Verfahren gemäß Anspruch 5 oder 6 wobei das kohlenstoffhaltige Gas ausgewählt
ist aus der Gruppe bestehend aus Methan, Ethan, Ethylen, Acetylen, Propan, Propylen,
Propin, Butanen, Butylenen, Butinen und Kombinationen davon.
8. Das Verfahren gemäß irgendeinem der Ansprüche 5 bis 7 wobei die reduzierende Atmosphäre
Wasserstoffgas enthält.
9. Das Verfahren gemäß Anspruch 8 wobei das kohlenstoffhaltige Gas Methan enthält und
das Verhältnis von Methan zu Wasserstoffgas von 1:1 bis 200:1 beträgt.
10. Das Verfahren gemäß Anspruch 8 wobei das kohlenstoffhaltige Gas Methan enthält und
das Verhältnis von Methan zu Wasserstoffgas 144:15 ist.
11. Das Verfahren gemäß irgendeinem der Ansprüche 1 bis 10 wobei die graphenhaltige Schicht
mit der monoatomischen Dicke einen Qualitätsfaktor von wenigstens 4 hat, wobei der
Qualitätsfaktor bestimmt wird durch das Verhältnis der Intensitäten des Raman-2D-Bandenpeaks
zum Raman-G-Bandenpeak (I2D/IG).
12. Das Verfahren gemäß irgendeinem der Ansprüche 1 bis 10 wobei die graphenhaltige Schicht
mit der monoatomischen Dicke einen Qualitätsfaktor von wenigstens 4 hat, wobei der
Qualitätsfaktor bestimmt wird durch das Verhältnis der Intensitäten des Raman-2D-Bandenpeaks
zum Raman-G-Bandenpeak (I2D/IG).
13. Das Verfahren gemäß Anspruch 12 wobei ein Ramanspektrum der Graphenschicht eine vernachlässigbare
D-Bande aufweist.
1. Un procédé de formation d'une structure multicouche, le procédé comprenant :
le fait de déposer une couche comprenant du cobalt sur une couche diélectrique comprenant
une couche de dioxyde de silicium en contact avec une surface de plaquette avant d'une
plaquette de silicium, la couche comprenant du cobalt étant déposée par une technique
choisie dans le groupe constitué par la pulvérisation, l'évaporation, l'évaporation
par faisceau d'électrons, l'évaporation par faisceau d'ions, dépôt chimique en phase
vapeur, placage électrolytique et liaison de feuille métallique, pour préparer ainsi
une structure comprenant la plaquette de silicium, la couche diélectrique et la couche
comprenant du cobalt ;
le fait de recuire la structure comprenant la plaquette de silicium, la couche diélectrique
comprenant une couche de dioxyde de silicium, et la couche comprenant du cobalt dans
une atmosphère réductrice à une température comprise entre 800° C et 1200° C pour
préparer ainsi la couche comprenant du cobalt monocristallin ; et
le fait de déposer de façon épitaxiale une couche de graphène sur la couche comprenant
du cobalt monocristallin, la couche de graphène ayant une seule épaisseur monoatomique.
2. Le procédé selon la revendication 1, dans lequel la plaquette de silicium comprend
un dopant choisi dans le groupe constitué du bore (type p), du gallium (type p), du
phosphore (type n), de l'antimoine (type n) et de l'arsenic (type n), et toute combinaison
de ceux-ci.
3. Le procédé selon la revendication 1 ou la revendication 2, dans lequel la couche comprenant
du cobalt monocristallin comprend une surface avant de couche de cobalt, une surface
arrière de couche de cobalt et une zone pleine de couche de cobalt entre la surface
avant de couche de cobalt et la surface arrière de couche de cobalt, la surface arrière
de couche de cobalt étant en contact avec la couche diélectrique.
4. Le procédé selon l'une quelconque des revendications 1 à 3, dans lequel la couche
comprenant du cobalt monocristallin a une épaisseur comprise entre environ 50 nanomètres
et environ 20 micromètres, de préférence entre environ 50 nanomètres et environ 10
micromètres d'épaisseur, de façon encore préférée entre environ 50 nanomètres et environ
1 micromètre d'épaisseur.
5. Le procédé selon l'une quelconque des revendications 1 à 4, dans lequel la couche
comprenant du graphène ayant une seule épaisseur monoatomique est déposée de façon
épitaxiale sur la couche comprenant du cobalt monocristallin selon les étapes suivantes
:
mettre en contact de la surface avant de couche de cobalt de la couche comprenant
du cobalt monocristallin avec un gaz contenant du carbone dans une atmosphère réductrice
à une température suffisante pour nucléer des atomes de carbone sur la surface avant
de couche de cobalt ; et
précipiter des atomes de carbone pour, ainsi, déposer de façon épitaxiale la couche
de graphène ayant une seule épaisseur monoatomique sur la surface avant de couche
de cobalt.
6. Le procédé selon la revendication 5, dans lequel les atomes de carbone sont précipités
en refroidissant la couche comprenant du cobalt monocristallin en contact avec une
couche diélectrique.
7. Le procédé selon les revendications 5 ou 6, dans lequel le gaz contenant du carbone
est choisi dans le groupe consistant en du méthane, de l'éthane, de l'éthylène, de
l'acétylène, du propane, du propylène, du propyne, des butanes, des butylènes, des
butynes et les combinaisons de ceux-ci.
8. Le procédé selon l'une quelconque des revendications 5 à 7, dans lequel l'atmosphère
réductrice comprend de l'hydrogène gazeux.
9. Le procédé selon la revendication 8, dans lequel le gaz contenant du carbone comprend
du méthane, et un rapport entre le méthane et l'hydrogène gazeux est de 1:1 à 200:1.
10. Le procédé selon la revendication 8, dans lequel le gaz contenant du carbone comprend
du méthane et un rapport du méthane et de l'hydrogène gazeux est de 144:15.
11. Le procédé selon l'une quelconque des revendications 1 à 10, dans lequel la couche
de graphène ayant une seule épaisseur monoatomique a un facteur de qualité d'au moins
4, le facteur de qualité étant déterminé par le rapport des intensités du pic de bande
Raman 2D au pic de bande Raman G (I2D/IG).
12. Le procédé selon l'une quelconque des revendications 1 à 10, dans lequel la couche
de graphène ayant une seule épaisseur monoatomique a un facteur de qualité d'au moins
7,5, le facteur de qualité étant déterminé par le rapport des intensités du pic de
bande Raman 2D au pic de bande Raman G (I2D/IG).
13. Le procédé selon la revendication 12, dans lequel un spectre Raman de la couche de
graphène présente une bande D négligeable.