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(11) | EP 3 229 264 B1 |
| (12) | EUROPEAN PATENT SPECIFICATION |
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ETCHING METHOD AND FABRICATION METHOD OF SEMICONDUCTOR STRUCTURES ÄTZVERFAHREN UND HERSTELLUNGSVERFAHREN VON HALBLEITERSTRUKTUREN PROCÉDÉ DE GRAVURE ET PROCÉDÉ DE FABRICATION DE STRUCTURES À SEMI-CONDUCTEURS |
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| Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention). |
FIELD OF THE DISCLOSURE
[0001] The present invention generally relates to the field of semiconductor manufacturing technology and, more particularly, relates to an etching method and a fabrication method of semiconductor structures.
BACKGROUND
[0002] With the rapid development of semiconductor manufacturing technologies, semiconductor device evolves in a direction towards higher component density and higher integration degree.
[0003] The improvement in the integration degree of the semiconductor device causes a reduction in the distance between adjacent gate electrode structures, and common-drain MOS transistors are emerged. To accommodate the reduced distance between gate electrode structures in the common-drain MOS transistors, the application of self-aligned scheme in semiconductor processes has become more and more important.
[0004] The self-aligned contact (SAC) technology has been applied to fabricate metal contact structures. The SAC technology may realize the etching of relatively deep patterns such as trenches, through-holes, etc., with a relatively high aspect ratio that are disposed between adjacent gate electrode structures, thereby electrically connecting the drain electrodes of the common-drain MOS transistors to the external circuit.
[0005] However, issues are commonly found in the current SAC technology as the etching process can be easily terminated and the damages to the through-hole sidewalls are relatively large.
[0006] US 2015/235860 A1, US 6 617 253 B1, and US 2004/038546 A1 describe methods of etching a dielectric layer.
BRIEF SUMMARY OF THE DISCLOSURE
[0007] It is an object of the present invention to provide an etching method and a corresponding fabrication method of semiconductor structures which at least partially solve one or more problems set forth above and other problems.
[0008] The object is achieved by an etching method according to claim 1, and a fabrication method according to claim 7. Further embodiments are defined in the respective dependent claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009]
FIG. 1 and FIG. 2 illustrate intermediate structures corresponding to each step of an etching method;
FIG. 3 and FIG. 4 illustrate intermediate structures corresponding to each step of an exemplary etching method consistent with the disclosed embodiments;
FIG. 5~FIG. 9 illustrate intermediate structures corresponding to an exemplary fabrication method of a semiconductor structure consistent with the disclosed embodiments; and
FIG. 10 illustrates a flow chart of an exemplary fabrication method of a semiconductor structure consistent with the disclosed embodiments.
DETAILED DESCRIPTION
[0010] Reference will now be made in detail to exemplary embodiments of the disclosure, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
[0011] FIG. 1 and FIG. 2 illustrate intermediate structures corresponding to each step of an etching method.
[0012] FIG. 1 provides a semiconductor structure, and the semiconductor structure may include a substrate 100, a plurality of gate electrodes 101 disposed on the substrate 100, sidewall spacers 102 formed on side surfaces of gate electrodes 101, and a mask layer 103 on top surface of the gate electrodes 101. Trenches may be disposed between adjacent gate electrodes 101, and a dielectric layer 104 may be formed in the trenches.
[0013] Further, a patterned photoresist layer 110 may be formed on surface of the semiconductor structure, and the patterned photoresist layer 110 may have openings (not labeled) exposing top surface of the dielectric layer 104.
[0014] Referring to FIG. 2, the dielectric layer 104 is etched. During the etching process of the dielectric layer 104, the etching conditions may remain unchanged and a polymer may be produced, for example, by a reaction between etchant and the sidewall spacers 102. In the etching method, the distance between adjacent side surfaces of each trench may be relatively small. Thus, after the photoresist layer 110 is formed, due to the resolution limit of the photolithography process, the photoresist layer 110 may expose portions of top surface of the sidewall spacers 102. Accordingly, damages to the sidewall spacers 102 during the etching process may need to be avoided.
[0015] During the etching process of the dielectric layer 104, if the deposition rate of the polymer is greater than the etch rate, the polymer may be deposited on surface of the sidewall spacers 102 and on surface of the dielectric layer 104. If the deposition rate of the polymer is smaller than the etch rate, the sidewall spacers 102 and the dielectric layer 104 may be etched continuously.
[0016] During the whole etching process, the etching conditions may remain unchanged, then during the etching process, polymer may be deposited continuously, or the sidewall spacers 102 and the dielectric layer 104 may be etched continuously. Specifically, if the etch rate of the polymer is relatively large, the sidewall spacers 102 may be etched easily, which increases the loss of the sidewall spacers 102, thus exposing the gate electrodes 101. If the etch rate in the whole etching process is relatively low, a relatively large amount of the polymer may be deposited on surface of the dielectric layer 104, thus terminating the etching of the dielectric layer 104.
[0017] The present invention provides an exemplary etching method, including providing a to-be-etched structure. Trenches are formed in the to-be-etched structure, and a dielectric layer is disposed in the trenches. The etching method further includes etching the dielectric layer in the trenches. When etching the dielectric layer, polymer is formed on side surfaces of the to-be-etched structure. By varying the etching temperature, the etching process includes a deposition stage and a removal stage of the polymer. During the deposition stage, the deposition rate of the polymer is greater than the etch rate of the polymer on the surface of the to-be-etched structure. During the removal stage, the deposition rate of the polymer is smaller than the etch rate of the polymer on the surface of the to-be-etched structure.
[0018] In the disclosed etching method, by varying the etching temperature, the etching process is changed, and the etching process includes a deposition stage and a removal stage of the polymer. During the deposition stage, the deposition rate of the polymer is greater than the etch rate of the polymer on the surface of the to-be-etched structure. During the removal stage, the deposition rate of the polymer is smaller than the etch rate of the polymer on the surface of the to-be-etched structure. Further, during the deposition stage, the polymer is deposited on the surface of the to-be-etched structure, thus protecting the to-be-etched structure in the follow-up removal stage and reducing the loss of the to-be-etched structure. During the removal stage, the polymer deposited on the surface of the to-be-etched structure is etched and removed, thus preventing the termination of the etching process caused by accumulation of too much polymer on the surface of the to-be-etched structure.
[0019] To make the above goals, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be made in detail with reference to the accompanying drawings.
[0020] FIG. 3 and FIG. 4 illustrate intermediate structures corresponding to each step of an exemplary etching method consistent with the disclosed embodiments. Referring to FIG. 3 and FIG. 4, the etching method includes providing a to-be-etched structure 10, forming trenches in the to-be-etched structure 10, and disposing a dielectric layer 11 in the trenches.
[0021] The dielectric layer 11 in the trenches is etched and, during the etching process, polymer is formed on the surface of the to-be-etched structure 10. Further, during the etching process, by varying the etching temperature, the etching process includes a deposition stage and a removal stage of the polymer. During the deposition stage, the deposition rate of the polymer is greater than the etch rate of the polymer on the surface of the to-be-etched structure 10. During the removal stage, the deposition rate of the polymer is smaller than the etch rate of the polymer on the surface of the to-be-etched structure 10.
[0022] Referring to FIG. 3, the trenches are formed in the to-be-etched structure 10, and the dielectric layer 11 is formed in the trenches. According to the invention, the material of the to-be-etched structure 10 is silicon nitride or silicon oxynitride. According to the invention, the material of the dielectric layer 11 is silicon oxide.
[0023] Referring to FIG. 4, the dielectric layer 11 is etched. During the etching process, polymer is formed on the surface of the to-be-etched structure 10, and by varying the etching temperature, the etching process of the dielectric layer 11 includes the deposition stage and the removal stage of the polymer. During the deposition stage, the deposition rate of the polymer is greater than the etch rate of the polymer on the surface of the to-be-etched structure 10. During the removal stage, the deposition rate of the polymer is smaller than the etch rate of the polymer on the surface of the to-be-etched structure 10.
[0024] According to the invention, by varying the etching temperature, the etching process is changed and, thus, the etching process includes the deposition stage of the polymer and the removal stage of the polymer. Specifically, in one embodiment, the deposition stage and the removal stage may appear alternatingly and repeatedly, resulting in the alternating and repeated occurrence of polymer deposition and polymer removal. Accordingly, the loss of the to-be-etched structure 10 may be reduced, and the etching may not be terminated easily.
[0025] From the above analysis, the disclosed etching method may be applied to etch the dielectric layer 11 in the trenches with a relatively large aspect ratio. Specifically, in one embodiment, the aspect ratio of the trenches may be greater than 7.
[0026] In one embodiment, the dielectric layer 11 may be etched via an anisotropic dry etching process, and the vertical etch rate may be greater than the horizontal etch rate in the anisotropic dry etching process. Accordingly, in the etching process, the loss of the to-be-etched structure 10 may be relatively small. The disclosed etching may be anisotropic etching, and the vertical etch rate may be relatively large, that is, the etch rate of the dielectric layer 11 may be relatively large. During the whole etching process, the vertical deposition rate of the polymer may be smaller than the etch rate. Accordingly, the etching of the dielectric layer 11 may not be easily terminated in the whole process.
[0027] The deposition stage and the removal stage form an etching circle. In one embodiment, the etching process may include a plurality of etching circles. In other embodiments, the etching process may only include one etching circle.
[0028] Specifically, the number of the etching circles may be selected according to the thickness of the dielectric layer 11. The thickness of the dielectric layer 11 may refer to the distance from the top surface of the dielectric layer 11 to the bottom of the trenches. In one embodiment, the thickness of the dielectric layer 11 may be approximately 100 Å∼300 Å, and the number of the etching circles included in the etching process may be greater than 4. In one embodiment, when etching the dielectric layer 11, the plurality of etching circles may be the same. In other embodiments, the plurality of etching circles may be different.
[0029] According to the invention, the etching gas is one or more selected from CF4, C3F8, and C4F8. According to the invention, the temperature at which the deposition rate of the polymer is equal to the etch rate of the polymer on the surface of the to-be-etched structure 10 is an equilibrium temperature T0. In the etching process, the etching temperature includes a first temperature higher than the equilibrium temperature and a second temperature lower than the equilibrium temperature.
[0030] According to the invention, the etching temperature is expressed as a sine function of the time. T represents the etching temperature, and t represents the etching time. The relationship between the etching temperature T and the etching time t is shown as follows:
[0031] Where, T0 is the equilibrium temperature, T1 is the amplitude of variation of the etching temperature indicating the maximum value of the etching temperature deviating from the equilibrium temperature T0, and t0 is the duration of the etching circle.
[0032] The first time when the etching temperature equals to the equilibrium temperature may be labeled as t1. In one embodiment, t1 may refer to a moment after the time when the etching begins.
[0033] In one embodiment, the polymer may be a material produced by reaction between the etching gas and the sidewall spacers. The equilibrium temperature T0 may be within the range of approximately 60°C∼80°C.
[0034] In one embodiment, if the amplitude of the variation of the etching temperature is too small, the deposition stage and the removal stage of the polymer may not be easily controlled. For example, the amplitude of the variation of the etching temperature may be greater than 30°C.
[0035] If the duration of the etching circle t0 is too small, the requirements of the device may easily become higher. In one embodiment, the duration of the etching circle t0 may be longer than 10 seconds.
[0036] In one embodiment, as the etching temperature increases, the etch rate of the polymer may be increased and the deposition rate of the polymer may be reduced. That is, when the etching temperature is the second temperature, the etching process may be in the deposition stage. When the etching temperature is the first temperature, the etching process may be in the removal stage. The first temperature and the second temperature may occur alternatingly, and the polymer may be deposited or etched alternatingly, which reduces the loss of the to-be-etched structure, and prevents the etching from being terminated.
[0037] As such, in the disclosed etching method, by varying the etching temperature, the etching process is changed, and the etching process includes a deposition stage and a removal stage of the polymer. During the deposition stage, the deposition rate of the polymer is greater than the etch rate of the polymer on the surface of the to-be-etched structure. During the removal stage, the deposition rate of the polymer is smaller than the etch rate of the polymer on the surface of the to-be-etched structure. In the deposition stage, the polymer is deposited on the surface of the to-be-etched structure, thus protecting the to-be-etched structure in the follow-up removal stage and reducing the loss of the to-be-etched structure. In the removal stage, the polymer deposited on the surface of the to-be-etched structure is etched, thus preventing the termination of the etching process caused by accumulation of too much polymer on the surface of the to-be-etched structure.
[0038] FIG. 5~FIG. 9 illustrate intermediate structures corresponding to an exemplary fabrication method of a semiconductor structure consistent with the disclosed embodiments. FIG. 10 illustrates a flow chart of an exemplary fabrication method of a semiconductor structure consistent with the disclosed embodiments.
[0039] Referring to FIG. 5~FIG. 10, the fabrication method of the semiconductor structure includes providing a substrate 200. A plurality of device structures 201 (e.g., gate electrode structures) are disposed on surface of the substrate 200, and the sidewall spacers 202 are disposed on side surfaces of the device structures 201. A mask layer 203 may be disposed on the top surface of the device structure 201, and trenches are formed between sidewall spacers 202 of adjacent device structures 201.
[0040] A dielectric layer 204 is formed on the surface of the substrate 200 and the surface of the sidewall spacers 202. The dielectric layer 204 in the trenches is etched, and polymer is formed on the surface of the sidewall spacers 202. During the etching process of the dielectric layer 204, by varying the etching temperature, the etching process includes the deposition stage and the removal stage of the polymer. During the deposition stage, the deposition rate of the polymer is greater than the etch rate of the polymer on the surface of the sidewall spacers 202. During the removal stage, the deposition rate of the polymer is smaller than the etch rate of the polymer on the surface of the sidewall spacers 202.
[0041] In the SAC technology, the distance between adjacent gate electrode structures may be relatively small, resulting in a relatively high aspect ratio of the trenches between the gate electrode structures, and the difficulty to etch the dielectric layer 204 in the trenches may be relatively large. In the present invention, the etching method is illustrated in detail in hope of solving the etching difficulty in the SAC technique.
[0042] FIG. 5 provides the substrate 200, and the plurality of device structures 201 are disposed on the surface of the substrate 200 (S1). The sidewall spacers 202 are formed on side surfaces of the device structures 201, the mask layer 203 may be formed on the top surface of the device structures 201, and the trenches are disposed between adjacent device structures 201 and sidewall spacers 202 (S2).
[0043] In one embodiment, the device structures 201 disposed on the substrate 200 may be gate electrode structures. In one embodiment, the sidewall spacers 202 may be used to protect the side surfaces of the gate electrode structures 201. The mask layer 203 may be used to protect the top surface of the gate electrode structures 201.
[0044] To improve the integration degree of the semiconductor device, the aspect ratio of the trenches may be relatively large. Specifically, in one embodiment, the aspect ratio of the trenches may be greater than 7:1. The trench may have a width of less than about 25 nm.
[0045] In one embodiment, the fabrication method may also include forming a source region and a drain region on two sides of the gate electrode structures 201 on the substrate 200. In one embodiment, by ion injection, the two sides of the gate electrode structures 201 on the substrate 200 may be doped to form the source region and the drain region.
[0046] Further, referring to FIG. 5, the dielectric layer 204 is formed on the surface of the substrate 200 and the surfaces of the sidewall spacers 202. That is, the dielectric layer 204 is formed in the trenches (S3). The materials of the dielectric layer 204 and the sidewall spacers 202 are different. During the etching process, the materials of the sidewall spacers 202 and the dielectric layer 204 are different. When etching the dielectric layer 204, the loss of the sidewall spacers 202 may be relatively small.
[0047] According to the invention, the material of the sidewall spacers 202 is silicon nitride or silicon oxynitride. According to the invention, the material of the dielectric layer 204 is silicon oxide.
[0048] In step 4 of FIG. 10 and referring to FIG. 6, after forming the dielectric layer 204, the fabrication method may also include forming a patterned photoresist layer 210 on the semiconductor structure. More specifically, the photoresist layer 210 may be disposed on the gate electrode structures 201 and have openings to expose the trenches. The photoresist layer 210 may be used to protect the gate electrode structures 201 from being etched during the follow-up etching process.
[0049] In one embodiment, the distance between adjacent gate electrode structures 201 may be relatively small. Due to the limit of the photolithography process, the photoresist 210 may only cover portions of top surface of the sidewall spacers 202, and expose other portions of the top surface of the sidewall spacers 202. Accordingly, when etching the dielectric layer 204, the sidewall spacers 202 exposed by the photoresist 210 may be easily etched.
[0050] Referring to FIG. 7 and FIG. 8, FIG. 8 illustrates a curve of etching temperature varying with etching time during an etching process, where the horizontal-axis represents the etching time, and the vertical-axis represents the etching temperature.
[0051] The dielectric layer 204 is etched (S5). The polymer is produced during the etching process, and by varying the etching temperature, the etching process includes a deposition stage and a removal stage of the polymer. During the deposition stage, the deposition rate of the polymer 202 is greater than the etch rate of the polymer on the surface of the sidewall spacers. In the removal stage, the deposition rate of the polymer is smaller than the etch rate of the polymer on the surface of the sidewall spacers 202.
[0052] During the etching process, by varying the etching temperature, the deposition rate of the polymer is greater than the etch rate of the polymer on the surface of the sidewall spacers 202 in the deposition stage (S6). Accordingly, the polymer is deposited on the surface of the sidewall spacers 202, thus protecting the sidewall spacers 202 from being etched in the follow-up removal stage. During the removal stage, the polymer on the surface of the sidewall spacers 202 is etched and removed, thus reducing the polymer deposited on the surface of the sidewall spacers 202, which further decreases the possibility of the etching termination.
[0053] According to the invention, the deposition stage and the removal stage forms an etching circle. The etching process may include a plurality of etching circles. In other embodiments, the etching process may also include one etching circle.
[0054] Specifically, the number of the etching circles may be selected according to the thickness of the dielectric layer 204. The thickness of the dielectric layer 204 may refer to the distance from the top surface of the dielectric layer 204 to the bottom of the trenches. In one embodiment, the thickness of the dielectric layer may be approximately 100 Å ~300 Å. The etching circles included in the etching process may be greater than 4.
[0055] In one embodiment, during the etching process of the dielectric layer 204, the plurality of etching circles may be the same. In other embodiments, the plurality of etching circles may be different.
[0056] In one embodiment, the dielectric layer 204 may be etched by anisotropic dry etching, and the vertical etch rate of the anisotropic dry etching may be greater than the horizontal etch rate. Accordingly, during the etching process, the loss of the sidewall spacers 202 may be relatively small. The etching may be the anisotropic etching, and the vertical etch rate may be relatively large. That is, the etch rate of the dielectric layer 204 may be relatively large. During the whole etching process, the vertical deposition rate of the polymer may be smaller than the etch rate of the polymer. Accordingly, the etching of the dielectric layer 204 may not be terminated easily.
[0057] According to the invention, the etching gas is one or more selected from CF4, C3F8, and C4F8.
[0058] By varying the etching temperature, the etching process is changed, and the etching process includes the deposition stage of the polymer and the removal stage of the polymer. Specifically, in one embodiment, the deposition stage and the removal stage may appear alternatingly and repeatedly, resulting in the alternating occurrence of polymer deposition and polymer removal. Accordingly, the loss of the sidewall spacers 202 may be reduced, and the etching may not be terminated easily.
[0059] According to the invention, the etching temperature varying with the etching time is illustrated in FIG. 8.
[0060] The temperature at which the deposition rate of the polymer is equal to the etch rate of the polymer on the surface of the sidewall spacers 202 (as shown in FIGS. 5-7) is the equilibrium temperature. According to the invention, the etching temperature includes the first temperature higher than the equilibrium temperature and the second temperature lower than the equilibrium temperature.
[0061] According to the invention, the etching temperature is a sine function of the time. T represents the etching temperature, and t represents the etching time. The relationship between the etching temperature T and the etching time t is shown as follows:
wherein T0 is the equilibrium temperature, T1 is the amplitude of variation of the etching temperature indicating the maximum value of the etching temperature deviating from the equilibrium temperature T0, and t0 is the duration of the etching circle.
[0062] The first time when the etching temperature is the equilibrium temperature is t1. In one embodiment, t1 may be greater than the time when the etching begins.
[0063] In one embodiment, the polymer may be a material produced by reaction between the etching gas and the sidewall spacers. The equilibrium temperature T0 may be within the range of approximately 60°C~80°C.
[0064] In one embodiment, if the amplitude of variation of the etching temperature is too small, the deposition stage and the removal stage may not be easily controlled. Specifically, the amplitude of variation of the etching temperature may be greater than 30°C.
[0065] If the time for the etching circle t0 is too small, the requirements of the device may easily increase. In one embodiment, the time for the etching circle t0 may be longer than 10 seconds.
[0066] In one embodiment, as the etching temperature increases, the etch rate of the polymer may be increased and the deposition rate of the polymer may be reduced. That is, when the etching temperature is the second temperature, the etching process may be in the deposition stage. When the etching temperature is the first temperature, the etching process may be in the removal stage. The first temperature and the second temperature may occur alternatingly, and the polymer may be deposited or etched, resulting in a reduction in the loss of the sidewall spacers 202, which may prevent the etching from being terminated.
[0067] By adjusting the etching temperature, the deposition and etching of the polymer may be controlled, the etching process may be carried out continuously, and the etching efficiency may be increased. Accordingly, by controlling the etching temperature, the operation may be relatively simple.
[0068] According to the invention, the deposition stage and the removal stage of the polymer forms an etching circle. The etching stage may vary periodically using the etching circle as a period. Accordingly, the process that the polymer is deposited on the side surfaces of the sidewall spacers 202 and then etched may be continuously repeated during the etching process of the dielectric layer 204. Thus, the loss of the sidewall spacers 202 may be reduced, and the etching termination may be prevented.
[0069] In one embodiment, in a step where the dielectric layer 204 is etched, the etching process may not be terminated until the source region or the drain region is exposed, thus forming contact holes 220 (as shown in FIG. 7). Referring to FIG. 9, in one embodiment, after forming the contact holes 220, plugs 221 may be formed in the contact holes 220.
[0070] The plugs 221 may be formed by any suitable materials. In one embodiment, the material of the plugs 221 may be copper. In other embodiments, the material of the plugs 221 may be tungsten.
[0071] As such, in the fabrication method of the semiconductor structure, by varying the etching temperature, the etching process is controlled and changed, and the etching process of the dielectric layer includes the deposition stage and the removal stage of the polymer. During the deposition stage, the deposition rate of the polymer is greater than the etch rate of the polymer on the surface of the sidewall spacers. During the removal stage, the deposition rate of the polymer is smaller than the etch rate of the polymer on the surface of the sidewall spacers. In the deposition stage, the polymer is deposited on the surface of the sidewall spacers, thus protecting the sidewall spacers in the follow-up removal stage and reducing the loss of the sidewall spacers. In the removal stage, the polymer deposited on the surface of the sidewall spacers is etched, thus preventing the termination of the etching process caused by accumulation of too much polymer on the surface of the sidewall spacers.
forming trenches in a to-be-etched structure (10);
forming (S3) a dielectric layer (11; 204) in the trenches;
etching (S5) the dielectric layer (11; 204) in the trenches by an etching process; and
controlling (S6) at least an etching temperature of the etching process by continuously varying said temperature while a polymer is formed on side surface of the to-be-etched structure,
wherein during the etching process of the dielectric layer (11; 204), the polymer undergoes:
a deposition stage, having a deposition rate of the polymer greater than an etch rate of the polymer; and
a removal stage, having the deposition rate less than the etch rate,
wherein the material of the to-be etched structure is silicon nitride or silicon oxynitride and the material of the dielectric layer (11; 204) is silicon oxide and an etching gas for etching the dielectric layer (11; 204) includes one or more gases selected form CF4, C3F8 and C4F8, and wherein a relationship between an etching temperature T and an etching time t is:wherein T0 is an equilibrium temperature, T1 is a maximum value of the etching temperature deviating from the equilibrium temperature T0, and t0 is a duration of an etching circle, the equilibrium temperature being the temperature at which the deposition rate of the polymer and the etch rate of said polymer are equal, the deposition stage and the removal stage forming an etching circle.
the etching process of the dielectric layer includes one or more etching circles.
a duration of one etching circle is longer than 10 seconds.
the maximum value of the etching temperature deviating from the equilibrium temperature is greater than 30°C.
the equilibrium temperature is in a range of approximately 60 °C ∼80 °C.
the etching process of the dielectric layer (11; 204) includes an anisotropic dry etching.
an etching method according to any one of the claims 1-6,
wherein, in the step of forming trenches in a to-be-etched structure, a plurality of device structures (201) is formed (S1) on a substrate (200), and sidewall spacers (202) are formed (S2) on side surfaces (201) of each device structure to provide the trenches on the substrate (200) between sidewall spacers (202) of adjacent device structures (201).
the device structures (201) include gate electrode structures, and the fabrication method further includes:
forming a source region and a drain region on two sides of each gate electrode structure on the substrate.
the steps of etching (S5) the dielectric layer (204) in the trenches includes etching the dielectric layer (204) till the source region or the drain region is exposed, and forming contact holes (220); and
the fabrication method further includes: forming plugs (221) in the contact holes (220).
the etching temperature for etching the dielectric layer (204) includes a first temperature higher than the equilibrium temperature and a second temperature lower than the equilibrium temperature,
the etching temperature of the dielectric layer (204) in the removal stage of the polymer is the first temperature, and
the etching temperature of the dielectric layer (204) in the deposition stage of the polymer is the second temperature.
an aspect ratio of the trenches is greater than 7:1.
the trench has a width of less than 25 nm.
the sidewall spacers (202) are formed of a material being silicon nitride.
Bilden von Gräben in einer zu ätzenden Struktur (10);
Bilden (S3) einer dielektrischen Schicht (11; 204) in den Gräben;
Ätzen (S5) der dielektrischen Schicht (11; 204) in den Gräben durch einen Ätzprozess; und
Steuern (S6) mindestens einer Ätztemperatur des Ätzprozesses durch kontinuierliches Variieren der Temperatur, während ein Polymer auf der Seitenoberfläche der zu ätzenden Struktur gebildet wird,
wobei während des Ätzprozesses der dielektrischen Schicht (11; 204) das Polymer unterzogen wird:
einer Abscheidungsphase mit einer Abscheidungsrate des Polymers, die größer ist als eine Ätzrate des Polymers; und
eine Entfernungsphase, bei der die Abscheidungsrate geringer als die Ätzrate ist,
wobei das Material der zu ätzenden Struktur Siliziumnitrid oder Siliziumoxynitrid ist und das Material der dielektrischen Schicht (11; 204) Siliziumoxid ist und ein Ätzgas zum Ätzen der dielektrischen Schicht (11; 204) ein oder mehrere Gase enthält, die aus CF4, C3F8 und C4F8 ausgewählt sind, und
wobei eine Beziehung zwischen einer Ätztemperatur T und einer Ätzzeit t ist:
wobei T0 eine Gleichgewichtstemperatur ist, T1 ein Maximalwert der Ätztemperatur ist, der von der Gleichgewichtstemperatur T0 abweicht, und t0 eine Dauer eines Ätzzyklus ist, wobei die Gleichgewichtstemperatur die Temperatur ist, bei der die Abscheidungsrate des Polymers und die Ätzrate des Polymers gleich sind, wobei die Abscheidungsrate und die Entfernungsphase einen Ätzzyklus bilden.
der Ätzprozess der dielektrischen Schicht einen oder mehrere Ätzzyklen aufweist.
eine Dauer eines Ätzzyklus länger als 10 Sekunden ist.
der Maximalwert der von der Gleichgewichtstemperatur abweichenden Ätztemperatur größer als 30°C ist.
die Gleichgewichtstemperatur in einem Bereich von etwa 60°C bis 80°C liegt.
der Ätzprozess der dielektrischen Schicht (11; 204) ein anisotropes Trockenätzen aufweist.
einem Ätzverfahren nach einem der Ansprüche 1-6,
wobei in dem Schritt des Bildens von Gräben in einer zu ätzenden Struktur eine Vielzahl von Vorrichtungsstrukturen (201) auf einem Substrat (200) gebildet wird (S1) und Seitenwandabstandshalter (202) auf Seitenflächen (201) jeder Vorrichtungsstruktur gebildet werden (S2), um die Gräben auf dem Substrat (200) zwischen Seitenwandabstandshaltern (202) von benachbarten Vorrichtungsstrukturen (201) bereitzustellen.
die Vorrichtungsstrukturen (201) Gate-Elektroden-Strukturen aufweisen, und das Herstellungsverfahren ferner aufweist:
Bilden eines Source-Bereichs und eines Drain-Bereichs auf zwei Seiten jeder Gate-Elektrodenstruktur auf dem Substrat.
die Schritte des Ätzens (S5) der dielektrischen Schicht (204) in den Gräben das Ätzen der dielektrischen Schicht (204), bis der Source-Bereich oder der Drain-Bereich freigelegt ist, und das Bilden von Kontaktlöchern (220) aufweisen; und
das Herstellungsverfahren ferner aufweist: Bilden von Stopfen (221) in den Kontaktlöchern (220).
die Ätztemperatur zum Ätzen der dielektrischen Schicht (204) eine erste Temperatur höher als die Gleichgewichtstemperatur und eine zweite Temperatur niedriger als die Gleichgewichtstemperatur aufweist,
die Ätztemperatur der dielektrischen Schicht (204) in der Entfernungsphase des Polymers die erste Temperatur ist, und
die Ätztemperatur der dielektrischen Schicht (204) in der Abscheidungsphase des Polymers die zweite Temperatur ist.
ein Seitenverhältnis der Gräben größer als 7:1 ist.
der Graben eine Breite von weniger als 25 nm aufweist.
die Seitenwandabstandshalter (202) aus einem Material gebildet werden, das Siliziumnitrid ist.
la formation de tranchées dans une structure à graver (10) ;
la formation (S3) d'une couche diélectrique (11 ; 204) dans les tranchées ;
la gravure (S5) de la couche diélectrique (11 ; 204) dans les tranchées au moyen d'un processus de gravure ; et
la régulation (S6) d'au moins une température de gravure du processus de gravure en faisant varier en continu ladite température tandis qu'un polymère est formé sur une surface latérale de la structure à graver ;
dans lequel, pendant le processus de gravure de la couche diélectrique (11 ; 204), le polymère subit :
une étape de dépôt, qui présente une vitesse de dépôt du polymère qui est supérieure à une vitesse de gravure du polymère ; et
une étape d'enlèvement, qui présente la vitesse de dépôt qui est inférieure à la vitesse de gravure ;
dans lequel le matériau de la structure à graver est le nitrure de silicium ou l'oxynitrure
de silicium et le matériau de la couche diélectrique (11 ; 204) est l'oxyde de silicium
et un gaz de gravure pour la gravure de la couche diélectrique (11 ; 204) inclut un
ou plusieurs gaz qui est/sont sélectionné(s) parmi le CF4, le C3F8 et le C4F8, et dans lequel une relation entre une température de gravure T et un temps de gravure
t est :
dans laquelle T0 est une température d'équilibre, T1 est une valeur maximum dont la température de gravure s'écarte de la température d'équilibre T0 et t0 est une durée d'un cercle de gravure, la température d'équilibre étant la température à laquelle la vitesse de dépôt du polymère et la vitesse de gravure dudit polymère sont égales, l'étape de dépôt et l'étape d'enlèvement formant un cercle de gravure.
le processus de gravure de la couche diélectrique inclut un ou plusieurs cercle(s) de gravure.
une durée d'un cercle de gravure est supérieure à 10 secondes.
la valeur maximum dont la température de gravure s'écarte de la température d'équilibre est supérieure à 30 °C.
la température d'équilibre s'inscrit à l'intérieur d'une plage qui va d'approximativement 60 °C à 80 °C.
le processus de gravure de la couche diélectrique (11 ; 204) inclut une gravure anisotrope par voie sèche.
un procédé de gravure selon l'une quelconque des revendications 1 à 6;
dans lequel, au niveau de l'étape de formation de tranchées dans une structure à graver, les structures d'une pluralité de structures de dispositif (201) sont formées (S1) sur un substrat (200), et des espaceurs de paroi latérale (202) sont formés (S2) sur des surfaces latérales (201) de chaque structure de dispositif afin de constituer les tranchées sur le substrat (200) entre des espaceurs de paroi latérale (202) de structures de dispositif adjacentes (201).
les structures de dispositif (201) incluent des structures d'électrode de grille, et le procédé de fabrication inclut en outre :
la formation d'une région de source et d'une région de drain sur deux côtés de chaque structure d'électrode de grille sur le substrat.
l'étape de gravure (S5) de la couche diélectrique (204) dans les tranchées inclut la gravure de la couche diélectrique (204) jusqu'à ce que la région de source ou la région de drain soit exposée, et la formation de trous de contact (220) ; et
le procédé de fabrication inclut en outre : la formation de bouchons (221) dans les trous de contact (220).
la température de gravure pour graver la couche diélectrique (204) inclut une première température qui est supérieure à la température d'équilibre et une seconde température qui est inférieure à la température d'équilibre ;
la température de gravure de la couche diélectrique (204) lors de l'étape d'enlèvement du polymère est la première température ; et
la température de gravure de la couche diélectrique (204) lors de l'étape de dépôt du polymère est la seconde température.
un rapport d'aspect des tranchées est supérieur à 7:1.
la tranchée présente une largeur inférieure à 25 nm.
les espaceurs de paroi latérale (202) sont formés en un matériau qui est le nitrure de silicium.
REFERENCES CITED IN THE DESCRIPTION
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Patent documents cited in the description