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(11) | EP 4 319 533 A3 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | NONVOLATILE MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME |
| (57) Nonvolatile memory devices and memory systems including the same are disclosed. A
vertically-integrated nonvolatile memory device includes a peripheral circuit structure
with a peripheral circuit therein, and cell array structure that is bonded to the
peripheral circuit structure, and has a cell area and a connection area therein. The
cell area includes a plurality of gate electrodes and a plurality of insulating layers
alternately stacked, in the connection area. The plurality of gate electrodes include
a cell stack having a staircase shape, a plurality of capacitor core contact structures
configured to pass through the cell stack in the cell area, and a plurality of capacitor
gate contact structures connected to the plurality of gate electrodes in the connection
area. Each of the plurality of capacitor core contact structures includes: (i) a first
core conductor electrically connected to the peripheral circuit, and (ii) a first
cover insulating layer extending between the first core conductor and the plurality
of gate electrodes, and constitutes a capacitor in which the first core conductor,
the first cover insulating layer, and the plurality of gate electrodes are connected
to the peripheral circuit.
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