EP 0000384 B1 19811230 - ARRANGEMENT FOR PACKING HIGH-SPEED INTEGRATED CIRCUITS, INCLUDING DECOUPLING CAPACITORS FOR THE POWER INPUT TERMINALS, AND METHOD FOR REALIZING IT.
Title (en)
ARRANGEMENT FOR PACKING HIGH-SPEED INTEGRATED CIRCUITS, INCLUDING DECOUPLING CAPACITORS FOR THE POWER INPUT TERMINALS, AND METHOD FOR REALIZING IT.
Publication
Application
Priority
US 81595177 A 19770715
Abstract (en)
[origin: US4153988A] A high performance package for integrated circuit semiconductor devices in which decoupling capacitors are provided in close proximity to the integrated circuit devices for reducing voltage variations in the power driver lines, and/or a ground plate overlying the stripe metallurgy on the surface of the substrate for reducing cross-talk between signal lines. The decoupling capacitors are each comprised of a conductive layer on the inside of a via hole, a concentric dielectric layer on the conductive layer, and an electrically conductive plug in physical contact with the dielectric layer that is associated with the driver line circuitry of the package.
IPC 1-7
IPC 8 full level
H01L 23/02 (2006.01); H05K 1/16 (2006.01); H01L 23/12 (2006.01); H01L 23/52 (2006.01); H01L 23/64 (2006.01); H01L 25/00 (2006.01); H05K 1/18 (2006.01)
CPC (source: EP US)
H01L 23/642 (2013.01 - EP US); H01L 2924/0002 (2013.01 - EP US); H01L 2924/09701 (2013.01 - EP US); H01L 2924/15173 (2013.01 - EP US); Y10T 29/49121 (2015.01 - EP US); Y10T 29/49147 (2015.01 - EP US)
C-Set (source: EP US)
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 0000384 A1 19790124; EP 0000384 B1 19811230; CA 1090002 A 19801118; DE 2861463 D1 19820218; IT 1109828 B 19851223; IT 7824893 A0 19780623; JP S5421170 A 19790217; JP S5710577 B2 19820226; US 4153988 A 19790515
DOCDB simple family (application)
EP 78100332 A 19780707; CA 305588 A 19780615; DE 2861463 T 19780707; IT 2489378 A 19780623; JP 7660878 A 19780626; US 81595177 A 19770715