EP 0076999 A3 19851016 - ARRANGEMENT FOR THE AVOIDANCE OF FAULT IMPULSES OF A SUMMATION CURRENT TRANSFORMER
Title (en)
ARRANGEMENT FOR THE AVOIDANCE OF FAULT IMPULSES OF A SUMMATION CURRENT TRANSFORMER
Publication
Application
Priority
DE 3140866 A 19811014
Abstract (en)
[origin: EP0076999A2] The invention relates to an arrangement for the avoidance of fault impulses of a summation current transformer on its secondary winding (6). In such an arrangement, especially for fault-current protection switches, one lead (3, 4) surrounds the other (5) concentrically, in the region of the transformer core (2). By means of this arrangement, faulty disconnections are avoided, especially in the case of very high currents. <IMAGE>
IPC 1-7
IPC 8 full level
H01H 83/14 (2006.01)
CPC (source: EP)
H01H 83/144 (2013.01); H01H 2083/146 (2013.01); H01H 2083/148 (2013.01)
Citation (search report)
- [X] GB 719219 A 19541201 - ANDERSON BOYES & CO LTD
- [A] US 3665356 A 19720523 - DOUGLAS ELLWOOD S, et al
Designated contracting state (EPC)
AT BE CH DE FR IT LI NL
DOCDB simple family (publication)
EP 0076999 A2 19830420; EP 0076999 A3 19851016; DE 3140866 A1 19830421
DOCDB simple family (application)
EP 82109160 A 19821004; DE 3140866 A 19811014