Global Patent Index - EP 0174950 A4

EP 0174950 A4 19880205 - WAFER SCALE PACKAGE SYSTEM AND HEADER AND METHOD OF MANUFACTURE THEREOF.

Title (en)

WAFER SCALE PACKAGE SYSTEM AND HEADER AND METHOD OF MANUFACTURE THEREOF.

Title (de)

PACKUNGSSYSTEM AUF HALBLEITERSCHEIBENSKALA UND LEITER UND VERFAHREN ZUM HERSTELLEN DERSELBEN.

Title (fr)

SYSTEME DE BOITIER A L'ECHELLE DE LA TRANCHE, BARRETTE, ET PROCEDE DE FABRICATION.

Publication

EP 0174950 A4 19880205 (EN)

Application

EP 85901256 A 19850221

Priority

US 58197584 A 19840221

Abstract (en)

[origin: WO8503804A1] Wafer scale device (10, 201) on which is formed a layer of thin film as an interconnection system (203) with contact sites (202, 207) between the interconnection system (203) and die bonding sites (202) of the wafer (10, 201) to form a monolithic wafer. The interconnection system (203) has bonding sites on the surface of the wafer (10, 201) to which chips (11) are bonded to form a hybrid monolithic wafer system. The wafer (10) is packaged within a wafer package, (Fig. 4), and the packaging system utilizes a header (20) which is a flexible circuit connector between the wafer package and first level circuit board (30).

IPC 1-7

H01L 23/12; H01L 23/32; H01L 23/48; H01L 27/10

IPC 8 full level

H01L 21/60 (2006.01); H01L 23/48 (2006.01); H01L 23/495 (2006.01); H01L 23/50 (2006.01); H01L 23/52 (2006.01); H01L 23/538 (2006.01)

CPC (source: EP)

H01L 23/49541 (2013.01); H01L 23/5383 (2013.01); H01L 24/48 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48472 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/01057 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/12033 (2013.01); H01L 2924/14 (2013.01); H01L 2924/19107 (2013.01)

C-Set (source: EP)

  1. H01L 2224/48472 + H01L 2224/48227 + H01L 2924/00
  2. H01L 2924/10253 + H01L 2924/00
  3. H01L 2924/00014 + H01L 2224/45099
  4. H01L 2924/00014 + H01L 2224/05599
  5. H01L 2924/12033 + H01L 2924/00
  6. H01L 2924/14 + H01L 2924/00

Citation (search report)

  • WO 8202640 A1 19820805 - JOHNSON ROBERT ROYCE [US], et al
  • WO 8202603 A1 19820805 - JOHNSON ROBERT ROYCE [US]
  • 32nd Electronic Components Conference, May 10-12, 1982, San Diego, pages 7-16, IEEE, New York, US; Y. HSIA et al.: "A reconfigurable interconnect for in-silicon electronic assembley", page 8: "Empirical examination of basic concepts"; figures 3-5.
  • See references of WO 8503804A1

Designated contracting state (EPC)

BE DE FR GB NL

DOCDB simple family (publication)

WO 8503804 A1 19850829; EP 0174950 A1 19860326; EP 0174950 A4 19880205; JP H0584668 B2 19931202; JP S61501295 A 19860626

DOCDB simple family (application)

US 8500280 W 19850221; EP 85901256 A 19850221; JP 50099085 A 19850221