EP 0312720 A3 19900613 - DOUBLE BUFFERED GRAPHICS DESIGN SYSTEM
Title (en)
DOUBLE BUFFERED GRAPHICS DESIGN SYSTEM
Publication
Application
Priority
US 11090287 A 19871020
Abstract (en)
[origin: EP0312720A2] A graphic display system comprises a video display controller including two similar frame buffer memories for alternatively receiving and storing incoming pixel data and for periodically refreshing a display on a screen selectively in accordance with pixel data stored by either one of the two frame buffer memories. While the video display controller periodically refreshes the screen display in accordance with the pixel data stored in a first of the frame buffer memories, incoming pixel data is stored in the second frame buffer memory. The video display controller begins periodically refreshing the screen display in accordance with the pixel data stored in the second frame buffer memory. Updated pixel data stored in the second frame buffer memory is then copied into the first frame buffer memory.
IPC 1-7
IPC 8 full level
G06F 3/153 (2006.01); G06T 11/00 (2006.01); G09G 5/399 (2006.01)
CPC (source: EP)
G09G 5/399 (2013.01)
Citation (search report)
- [X] EP 0231061 A2 19870805 - IBM [US]
- [X] EP 0219552 A1 19870429 - ANRITSU CORP [JP]
- [X] EP 0194092 A2 19860910 - COMPUTER GRAPHICS LAB INC [US]
- [X] EP 0237706 A2 19870923 - IBM [US]
- [XP] EP 0268687 A1 19880601 - FANUC LTD [JP]
- [X] IBM TECHNICAL DISCLOSURE BULLETIN vol. 26, no. 6, November 1983, pages 2906,2907, New York, US; W. HALL et al.: "Low cost, high resolution IBM 3101 Graphics"
Designated contracting state (EPC)
DE FR GB NL
DOCDB simple family (publication)
EP 0312720 A2 19890426; EP 0312720 A3 19900613; JP H01134524 A 19890526
DOCDB simple family (application)
EP 88112554 A 19880802; JP 25924788 A 19881014