Global Patent Index - EP 0374641 A3

EP 0374641 A3 19910918 - METHOD TO SUPPRESS AMPLITUDE VARIATIONS OF TWO ALTERNATING, PERIODIC SIGNALS IN PHASE QUADRATURE WITH A RANDOM PHASE SEQUENCE, AND CIRCUIT ARRANGEMENT TO CARRY OUT THE METHOD

Title (en)

METHOD TO SUPPRESS AMPLITUDE VARIATIONS OF TWO ALTERNATING, PERIODIC SIGNALS IN PHASE QUADRATURE WITH A RANDOM PHASE SEQUENCE, AND CIRCUIT ARRANGEMENT TO CARRY OUT THE METHOD

Publication

EP 0374641 A3 19910918 (DE)

Application

EP 89122722 A 19891208

Priority

DE 3843108 A 19881221

Abstract (en)

[origin: EP0374641A2] The invention relates to a method of suppressing amplitude variations of two electrical signals (uS1, uS2) in phase quadrature and a circuit arrangement for carrying out the method. According to the invention, the positive or negative amplitude variation of the signals (uS1, uS2) is monitored for undershooting of a lower or overshooting of an upper reference voltage (+/-US- or +/-US+) in such a way that in the event of undershooting or overshooting a device (20, 22) for changing a prescribed manipulated variable of an actuator (8, 10) is activated, and the signals (uS1, uS2) are respectively converted into rectangular signals (uRS1,uRS2), from which clock pulses (uC11 or uC12) are generated by means of a logic circuit (24 or 26) depending upon the phase sequence of the signals (uS1, uS2) at the positive or negative flanks of the rectangular signals (uRS1, uRS2), which vary the prescribed gain as a function of the result of the amplitude monitoring by a prescribed value (LSB). This yields a method of suppressing amplitude variations of two electrical alternating, periodic signals (uS1, uS2) in phase quadrature with a random phase sequence, and a circuit arrangement for carrying out the method that operates independently of frequency. <IMAGE>

IPC 1-7

G05F 1/45

IPC 8 full level

G05F 1/44 (2006.01); G05F 1/45 (2006.01)

CPC (source: EP)

G05F 1/44 (2013.01); G05F 1/452 (2013.01)

Citation (search report)

  • [A] US 3464022 A 19690826 - LOCHEED EDWARD W JR, et al
  • [A] US 4707840 A 19871117 - NAKAYAMA KENJI [JP]
  • [A] US 3378786 A 19680416 - ANDREA JOHN J
  • [A] ELECTRONIC DESIGN, 16. September 1982, Seiten 133-139; P. BURTON: "Denser CMOS DACs cut hardware, software"
  • [A] ELECTRICAL DESIGN NEWS, Band 31, Nr. 2, Januar 1986, Seiten 214-217; M. BILAC: "Program returns D/A input for new gain"
  • [A] PATENT ABSTRACTS OF JAPAN, Band 9, Nr. 277 (E-355)[2000], 6 November 1985; & JP - A - 60 121 808 (NIPPON DENSHIN DENWA KOSHA) 29-06-1985

Designated contracting state (EPC)

AT CH DE FR GB IT LI

DOCDB simple family (publication)

EP 0374641 A2 19900627; EP 0374641 A3 19910918; EP 0374641 B1 19950215; AT E118626 T1 19950315; DE 3843108 C1 19900215; DE 58909003 D1 19950323

DOCDB simple family (application)

EP 89122722 A 19891208; AT 89122722 T 19891208; DE 3843108 A 19881221; DE 58909003 T 19891208