EP 0419125 A3 19920812 - PIPELINE ARCHITECTURE FOR GENERATING VIDEO SIGNAL
Title (en)
PIPELINE ARCHITECTURE FOR GENERATING VIDEO SIGNAL
Publication
Application
Priority
US 41107689 A 19890922
Abstract (en)
[origin: EP0419125A2] A symbol generator with pipeline architecture comprised of a series of processing stages that regenerate a complete video data signal for each display field is disclosed herein. The pipeline design offers a number of advantages over other systems. Any symbol in a display may be moved in real time and independently of any other symbol, because the display is regenerated for each and every field. The symbol generator includes a cpu microprocessor, vertical sorter, boundary generator, horizontal sorter, and color palette.
IPC 1-7
IPC 8 full level
G09G 5/06 (2006.01); G09G 5/24 (2006.01); G09G 5/42 (2006.01); H04N 5/262 (2006.01)
CPC (source: EP)
Citation (search report)
- [A] US 4831557 A 19890516 - MURATA HIROYUKI [JP]
- [A] DE 3243574 A1 19840530 - FOERST REINER GMBH [DE]
- [A] FR 2408262 A1 19790601 - GEC COMPUTERS LTD [GB]
- [A] GB 2191666 A 19871216 - APPLE COMPUTER
- [A] US 4364037 A 19821214 - WALKER JAMES T
- IEEE TRANSACTIONS ON COMPUTERS, vol. C-30, no. 1, January 1981, pages 41-48, New York, US; B.D. ACKLAND et al.: "The edge flag algorithm - a fill method for raster scan displays", abstract.
Designated contracting state (EPC)
DE FR GB IT NL
DOCDB simple family (publication)
EP 0419125 A2 19910327; EP 0419125 A3 19920812; JP H03220879 A 19910930
DOCDB simple family (application)
EP 90310010 A 19900913; JP 25501390 A 19900925