EP 0667061 A1 19950816 - PLL SYSTEM.
Title (en)
PLL SYSTEM.
Title (de)
PLL-SYSTEM.
Title (fr)
SYSTEME ASSERVI EN PHASE.
Publication
Application
Priority
- DE 9401007 W 19940829
- DE 4329353 A 19930827
Abstract (en)
[origin: WO9506359A1] The invention concerns a phase-locked loop (PLL) system, in particular a PLL system for the generation of the combination frequency for the frequency-conversion stage of an FM receiver. Series-connected to a first PLL circuit with a reference or output signal with a first, low, frequency is a second PLL circuit with a reference or output signal with a second, higher, frequency, the output signal of the first PLL circuit being fed as input to the second PLL circuit. The ratio of the output signal of the first PLL circuit to its reference signal is determined by a first frequency divider which produces, from this output signal, a signal for the phase-comparison switching of the first PLL circuit, whose frequency is decreased by an amount corresponding to the ratio determined by the first frequency divider. The ratio of the output signal of the second PLL circuit to its reference signal is determined by a second frequency divider which produces, from this output signal, a signal for the phase-comparison switching of the second PLL circuit, whose frequency is decreased by an amount corresponding to the ratio determined by the second frequency divider.
IPC 1-7
IPC 8 full level
H03J 5/02 (2006.01); H03L 7/107 (2006.01); H03L 7/23 (2006.01)
CPC (source: EP US)
H03J 5/0272 (2013.01 - EP US); H03L 7/107 (2013.01 - EP US); H03L 7/23 (2013.01 - EP)
Citation (search report)
See references of WO 9506359A1
Designated contracting state (EPC)
DE FR GB NL PT
DOCDB simple family (publication)
DE 4329353 A1 19950302; EP 0667061 A1 19950816; WO 9506359 A1 19950302
DOCDB simple family (application)
DE 4329353 A 19930827; DE 9401007 W 19940829; EP 94925338 A 19940829