EP 0711435 A1 19960515 - PROCESSOR CORE WHICH PROVIDES A LINEAR EXTENSION OF AN ADDRESSABLE MEMORY SPACE
Title (en)
PROCESSOR CORE WHICH PROVIDES A LINEAR EXTENSION OF AN ADDRESSABLE MEMORY SPACE
Title (de)
PROZESSORKERN MIT LINEARER ERWEITERUNG EINES SPEICHERADRESSENBEREICHS
Title (fr)
MEMOIRE CENTRALE DE PROCESSEUR A EXTENSION LINEAIRE DE L'ESPACE DE MEMOIRE ADRESSABLE
Publication
Application
Priority
- US 9504668 W 19950414
- US 24876894 A 19940525
Abstract (en)
[origin: WO9532467A1] A processor core for providing a linear extension of addressable memory space of a microprocessor with minimal additional hardware and software complexity. An N+x bit pointer register (e.g. program counter) holds an N+x bit instruction address. The N+x bit instruction address provides to an execution unit a pointer to an instruction in the memory to be processed by the execution unit. An encoder encodes the N+x bit address into an N bit encoding of the N+x bit address. The processor core can thereby address 2<x> times more memory locations than 2<N>. Two other registers each hold a portion of a data address (i.e. a pointer to a datum in memory to be operated on). An address former concatenates the portions of the address in the two registers to form the data address. Therefore, the address is formed from portions of the data address stored in multiple registers without performing any arithmetic on the portions.
IPC 1-7
IPC 8 full level
G06F 9/32 (2006.01)
CPC (source: EP KR)
G06F 9/32 (2013.01 - EP); G06F 9/321 (2013.01 - EP); G06F 12/06 (2013.01 - KR)
Citation (search report)
See references of WO 9532467A1
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
WO 9532467 A1 19951130; EP 0711435 A1 19960515; KR 960704269 A 19960831
DOCDB simple family (application)
US 9504668 W 19950414; EP 95916414 A 19950414; KR 19960700389 A 19960125