EP 0835549 A1 19980415 - METHODS AND APPARATUS FOR MODULATING, DEMODULATING AND AMPLIFYING
Title (en)
METHODS AND APPARATUS FOR MODULATING, DEMODULATING AND AMPLIFYING
Title (de)
VERFAHREN UND VORRICHTUNG ZUM MODULIEREN, DEMODULIEREN UND VERSTÄRKEN
Title (fr)
PROCEDES ET APPAREIL DE MODULATION, DEMODULATION ET AMPLIFICATION
Publication
Application
Priority
- GB 9601259 W 19960528
- GB 9510679 A 19950525
Abstract (en)
[origin: WO9637948A1] The invention includes apparatus for processing an input signal to generate an output signal. The processing arrangement comprises first and second feedback loops for generating, from said input signal, respective output signal components. Each loop comprises a voltage controlled oscillator, having a frequency or phase which is variable in response to a control signal, for generating a loop output signal which forms one of the components of the output signal and a comparator for generating the control signal. There is also provided combining means for combining the loop output signals to derive a signal representative of the output signal. Means for providing first and second feedback loop operating signals, dependent on the output signal and in phase quadrature with one another are provided. In each loop, the feedback loop operating signal is applied to one input of the comparator and the other input of the comparator is coupled to receive a component of the input signal. Signal-stability means for continuously ensuring that the output signal is stable whatever the phase of the output signal relative to the input signal are provided. The signal-stability means and the comparators derive control signals v1 (I) and v2 (II) for the respective VCOs where k = the loop gain of the feedback loops, r = the amplitude of the input signal as represented by the components x and y, R = the amplitude of the output of the VCOs, DELTA x = the difference between the x component of the input signal and the corresponding Cartesian component of the processed output signal, and ( DELTA y) = the difference between the y component of the input signal and the corresponding Cartesian component of the processed output signal.
IPC 1-7
IPC 8 full level
H03D 3/02 (2006.01); H03C 1/06 (2006.01); H03C 3/00 (2006.01); H03F 1/02 (2006.01); H04L 27/20 (2006.01); H04L 27/22 (2006.01)
CPC (source: EP)
H03C 1/06 (2013.01); H03F 1/0294 (2013.01)
Citation (search report)
See references of WO 9637948A1
Designated contracting state (EPC)
DE DK FI FR GB IT NL SE
DOCDB simple family (publication)
WO 9637948 A1 19961128; CA 2222091 A1 19961128; EP 0835549 A1 19980415; GB 9510679 D0 19950719; JP H11505979 A 19990525
DOCDB simple family (application)
GB 9601259 W 19960528; CA 2222091 A 19960528; EP 96919905 A 19960528; GB 9510679 A 19950525; JP 53551496 A 19960528